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LLVM 20.0.0git
MipsDisassembler.cpp
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1//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the Mips Disassembler.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/MipsMCTargetDesc.h"
14#include "TargetInfo/MipsTargetInfo.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoderOps.h"
18#include "llvm/MC/MCDisassembler/MCDisassembler.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCRegisterInfo.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/MC/TargetRegistry.h"
23#include "llvm/Support/Compiler.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/MathExtras.h"
27#include "llvm/Support/raw_ostream.h"
28#include <cassert>
29#include <cstdint>
30
31using namespacellvm;
32
33#define DEBUG_TYPE "mips-disassembler"
34
35usingDecodeStatus =MCDisassembler::DecodeStatus;
36
37namespace{
38
39classMipsDisassembler :publicMCDisassembler {
40bool IsMicroMips;
41bool IsBigEndian;
42
43public:
44 MipsDisassembler(constMCSubtargetInfo &STI,MCContext &Ctx,bool IsBigEndian)
45 :MCDisassembler(STI, Ctx),
46 IsMicroMips(STI.hasFeature(Mips::FeatureMicroMips)),
47 IsBigEndian(IsBigEndian) {}
48
49bool hasMips2() const{return STI.hasFeature(Mips::FeatureMips2); }
50bool hasMips3() const{return STI.hasFeature(Mips::FeatureMips3); }
51bool hasMips32() const{return STI.hasFeature(Mips::FeatureMips32); }
52
53bool hasMips32r6() const{
54return STI.hasFeature(Mips::FeatureMips32r6);
55 }
56
57bool isFP64() const{return STI.hasFeature(Mips::FeatureFP64Bit); }
58
59bool isGP64() const{return STI.hasFeature(Mips::FeatureGP64Bit); }
60
61bool isPTR64() const{return STI.hasFeature(Mips::FeaturePTR64Bit); }
62
63bool hasCnMips() const{return STI.hasFeature(Mips::FeatureCnMips); }
64
65bool hasCnMipsP() const{return STI.hasFeature(Mips::FeatureCnMipsP); }
66
67bool hasCOP3() const{
68// Only present in MIPS-I and MIPS-II
69return !hasMips32() && !hasMips3();
70 }
71
72DecodeStatusgetInstruction(MCInst &Instr,uint64_t &Size,
73ArrayRef<uint8_t> Bytes,uint64_tAddress,
74raw_ostream &CStream)const override;
75};
76
77}// end anonymous namespace
78
79// Forward declare these because the autogenerated code will reference them.
80// Definitions are further down.
81staticDecodeStatusDecodeGPR64RegisterClass(MCInst &Inst,unsigned RegNo,
82uint64_t Address,
83constMCDisassembler *Decoder);
84
85staticDecodeStatusDecodeCPU16RegsRegisterClass(MCInst &Inst,unsigned RegNo,
86uint64_t Address,
87constMCDisassembler *Decoder);
88
89staticDecodeStatusDecodeGPRMM16RegisterClass(MCInst &Inst,unsigned RegNo,
90uint64_t Address,
91constMCDisassembler *Decoder);
92
93staticDecodeStatus
94DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,unsigned RegNo,uint64_t Address,
95constMCDisassembler *Decoder);
96
97staticDecodeStatus
98DecodeGPRMM16MovePRegisterClass(MCInst &Inst,unsigned RegNo,uint64_t Address,
99constMCDisassembler *Decoder);
100
101staticDecodeStatusDecodeGPR32RegisterClass(MCInst &Inst,unsigned RegNo,
102uint64_t Address,
103constMCDisassembler *Decoder);
104
105staticDecodeStatusDecodePtrRegisterClass(MCInst &Inst,unsignedInsn,
106uint64_t Address,
107constMCDisassembler *Decoder);
108
109staticDecodeStatusDecodeDSPRRegisterClass(MCInst &Inst,unsigned RegNo,
110uint64_t Address,
111constMCDisassembler *Decoder);
112
113staticDecodeStatusDecodeFGR64RegisterClass(MCInst &Inst,unsigned RegNo,
114uint64_t Address,
115constMCDisassembler *Decoder);
116
117staticDecodeStatusDecodeFGR32RegisterClass(MCInst &Inst,unsigned RegNo,
118uint64_t Address,
119constMCDisassembler *Decoder);
120
121staticDecodeStatusDecodeCCRRegisterClass(MCInst &Inst,unsigned RegNo,
122uint64_t Address,
123constMCDisassembler *Decoder);
124
125staticDecodeStatusDecodeFCCRegisterClass(MCInst &Inst,unsigned RegNo,
126uint64_t Address,
127constMCDisassembler *Decoder);
128
129staticDecodeStatusDecodeFGRCCRegisterClass(MCInst &Inst,unsigned RegNo,
130uint64_t Address,
131constMCDisassembler *Decoder);
132
133staticDecodeStatusDecodeHWRegsRegisterClass(MCInst &Inst,unsignedInsn,
134uint64_t Address,
135constMCDisassembler *Decoder);
136
137staticDecodeStatusDecodeAFGR64RegisterClass(MCInst &Inst,unsigned RegNo,
138uint64_t Address,
139constMCDisassembler *Decoder);
140
141staticDecodeStatusDecodeACC64DSPRegisterClass(MCInst &Inst,unsigned RegNo,
142uint64_t Address,
143constMCDisassembler *Decoder);
144
145staticDecodeStatusDecodeHI32DSPRegisterClass(MCInst &Inst,unsigned RegNo,
146uint64_t Address,
147constMCDisassembler *Decoder);
148
149staticDecodeStatusDecodeLO32DSPRegisterClass(MCInst &Inst,unsigned RegNo,
150uint64_t Address,
151constMCDisassembler *Decoder);
152
153staticDecodeStatusDecodeMSA128BRegisterClass(MCInst &Inst,unsigned RegNo,
154uint64_t Address,
155constMCDisassembler *Decoder);
156
157staticDecodeStatusDecodeMSA128HRegisterClass(MCInst &Inst,unsigned RegNo,
158uint64_t Address,
159constMCDisassembler *Decoder);
160
161staticDecodeStatusDecodeMSA128WRegisterClass(MCInst &Inst,unsigned RegNo,
162uint64_t Address,
163constMCDisassembler *Decoder);
164
165staticDecodeStatusDecodeMSA128DRegisterClass(MCInst &Inst,unsigned RegNo,
166uint64_t Address,
167constMCDisassembler *Decoder);
168
169staticDecodeStatusDecodeMSACtrlRegisterClass(MCInst &Inst,unsigned RegNo,
170uint64_t Address,
171constMCDisassembler *Decoder);
172
173staticDecodeStatusDecodeCOP0RegisterClass(MCInst &Inst,unsigned RegNo,
174uint64_t Address,
175constMCDisassembler *Decoder);
176
177staticDecodeStatusDecodeCOP2RegisterClass(MCInst &Inst,unsigned RegNo,
178uint64_t Address,
179constMCDisassembler *Decoder);
180
181staticDecodeStatusDecodeBranchTarget(MCInst &Inst,unsignedOffset,
182uint64_t Address,
183constMCDisassembler *Decoder);
184
185staticDecodeStatusDecodeBranchTarget1SImm16(MCInst &Inst,unsignedOffset,
186uint64_t Address,
187constMCDisassembler *Decoder);
188
189staticDecodeStatusDecodeJumpTarget(MCInst &Inst,unsignedInsn,
190uint64_t Address,
191constMCDisassembler *Decoder);
192
193staticDecodeStatusDecodeBranchTarget21(MCInst &Inst,unsignedOffset,
194uint64_t Address,
195constMCDisassembler *Decoder);
196
197staticDecodeStatusDecodeBranchTarget21MM(MCInst &Inst,unsignedOffset,
198uint64_t Address,
199constMCDisassembler *Decoder);
200
201staticDecodeStatusDecodeBranchTarget26(MCInst &Inst,unsignedOffset,
202uint64_t Address,
203constMCDisassembler *Decoder);
204
205// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
206// shifted left by 1 bit.
207staticDecodeStatusDecodeBranchTarget7MM(MCInst &Inst,unsignedOffset,
208uint64_t Address,
209constMCDisassembler *Decoder);
210
211// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
212// shifted left by 1 bit.
213staticDecodeStatusDecodeBranchTarget10MM(MCInst &Inst,unsignedOffset,
214uint64_t Address,
215constMCDisassembler *Decoder);
216
217// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
218// shifted left by 1 bit.
219staticDecodeStatusDecodeBranchTargetMM(MCInst &Inst,unsignedOffset,
220uint64_t Address,
221constMCDisassembler *Decoder);
222
223// DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
224// shifted left by 1 bit.
225staticDecodeStatusDecodeBranchTarget26MM(MCInst &Inst,unsignedOffset,
226uint64_t Address,
227constMCDisassembler *Decoder);
228
229// DecodeJumpTargetMM - Decode microMIPS jump target, which is
230// shifted left by 1 bit.
231staticDecodeStatusDecodeJumpTargetMM(MCInst &Inst,unsignedInsn,
232uint64_t Address,
233constMCDisassembler *Decoder);
234
235// DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target,
236// which is shifted left by 2 bit.
237staticDecodeStatusDecodeJumpTargetXMM(MCInst &Inst,unsignedInsn,
238uint64_t Address,
239constMCDisassembler *Decoder);
240
241staticDecodeStatusDecodeMem(MCInst &Inst,unsignedInsn,uint64_t Address,
242constMCDisassembler *Decoder);
243
244staticDecodeStatusDecodeMemEVA(MCInst &Inst,unsignedInsn,uint64_t Address,
245constMCDisassembler *Decoder);
246
247staticDecodeStatusDecodeLoadByte15(MCInst &Inst,unsignedInsn,
248uint64_t Address,
249constMCDisassembler *Decoder);
250
251staticDecodeStatusDecodeCacheOp(MCInst &Inst,unsignedInsn,uint64_t Address,
252constMCDisassembler *Decoder);
253
254staticDecodeStatusDecodeCacheeOp_CacheOpR6(MCInst &Inst,unsignedInsn,
255uint64_t Address,
256constMCDisassembler *Decoder);
257
258staticDecodeStatusDecodeCacheOpMM(MCInst &Inst,unsignedInsn,
259uint64_t Address,
260constMCDisassembler *Decoder);
261
262staticDecodeStatusDecodePrefeOpMM(MCInst &Inst,unsignedInsn,
263uint64_t Address,
264constMCDisassembler *Decoder);
265
266staticDecodeStatusDecodeSyncI(MCInst &Inst,unsignedInsn,uint64_t Address,
267constMCDisassembler *Decoder);
268
269staticDecodeStatusDecodeSyncI_MM(MCInst &Inst,unsignedInsn,
270uint64_t Address,
271constMCDisassembler *Decoder);
272
273staticDecodeStatusDecodeSynciR6(MCInst &Inst,unsignedInsn,uint64_t Address,
274constMCDisassembler *Decoder);
275
276staticDecodeStatusDecodeMSA128Mem(MCInst &Inst,unsignedInsn,
277uint64_t Address,
278constMCDisassembler *Decoder);
279
280staticDecodeStatusDecodeMemMMImm4(MCInst &Inst,unsignedInsn,
281uint64_t Address,
282constMCDisassembler *Decoder);
283
284staticDecodeStatusDecodeMemMMSPImm5Lsl2(MCInst &Inst,unsignedInsn,
285uint64_t Address,
286constMCDisassembler *Decoder);
287
288staticDecodeStatusDecodeMemMMGPImm7Lsl2(MCInst &Inst,unsignedInsn,
289uint64_t Address,
290constMCDisassembler *Decoder);
291
292staticDecodeStatusDecodeMemMMReglistImm4Lsl2(MCInst &Inst,unsignedInsn,
293uint64_t Address,
294constMCDisassembler *Decoder);
295
296staticDecodeStatusDecodeMemMMImm9(MCInst &Inst,unsignedInsn,
297uint64_t Address,
298constMCDisassembler *Decoder);
299
300staticDecodeStatusDecodeMemMMImm12(MCInst &Inst,unsignedInsn,
301uint64_t Address,
302constMCDisassembler *Decoder);
303
304staticDecodeStatusDecodeMemMMImm16(MCInst &Inst,unsignedInsn,
305uint64_t Address,
306constMCDisassembler *Decoder);
307
308staticDecodeStatusDecodeFMem(MCInst &Inst,unsignedInsn,uint64_t Address,
309constMCDisassembler *Decoder);
310
311staticDecodeStatusDecodeFMemMMR2(MCInst &Inst,unsignedInsn,
312uint64_t Address,
313constMCDisassembler *Decoder);
314
315staticDecodeStatusDecodeFMem2(MCInst &Inst,unsignedInsn,uint64_t Address,
316constMCDisassembler *Decoder);
317
318staticDecodeStatusDecodeFMem3(MCInst &Inst,unsignedInsn,uint64_t Address,
319constMCDisassembler *Decoder);
320
321staticDecodeStatusDecodeFMemCop2R6(MCInst &Inst,unsignedInsn,
322uint64_t Address,
323constMCDisassembler *Decoder);
324
325staticDecodeStatusDecodeFMemCop2MMR6(MCInst &Inst,unsignedInsn,
326uint64_t Address,
327constMCDisassembler *Decoder);
328
329staticDecodeStatusDecodeSpecial3LlSc(MCInst &Inst,unsignedInsn,
330uint64_t Address,
331constMCDisassembler *Decoder);
332
333staticDecodeStatusDecodeAddiur2Simm7(MCInst &Inst,unsignedValue,
334uint64_t Address,
335constMCDisassembler *Decoder);
336
337staticDecodeStatusDecodeLi16Imm(MCInst &Inst,unsignedValue,
338uint64_t Address,
339constMCDisassembler *Decoder);
340
341staticDecodeStatusDecodePOOL16BEncodedField(MCInst &Inst,unsignedValue,
342uint64_t Address,
343constMCDisassembler *Decoder);
344
345template <unsigned Bits,int Offset,int Scale>
346staticDecodeStatusDecodeUImmWithOffsetAndScale(MCInst &Inst,unsignedValue,
347uint64_t Address,
348constMCDisassembler *Decoder);
349
350template <unsigned Bits,int Offset>
351staticDecodeStatusDecodeUImmWithOffset(MCInst &Inst,unsignedValue,
352uint64_t Address,
353constMCDisassembler *Decoder) {
354return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst,Value,Address,
355 Decoder);
356}
357
358template <unsigned Bits,int Offset = 0,int ScaleBy = 1>
359staticDecodeStatusDecodeSImmWithOffsetAndScale(MCInst &Inst,unsignedValue,
360uint64_t Address,
361constMCDisassembler *Decoder);
362
363staticDecodeStatusDecodeInsSize(MCInst &Inst,unsignedInsn,uint64_t Address,
364constMCDisassembler *Decoder);
365
366staticDecodeStatusDecodeSimm19Lsl2(MCInst &Inst,unsignedInsn,
367uint64_t Address,
368constMCDisassembler *Decoder);
369
370staticDecodeStatusDecodeSimm18Lsl3(MCInst &Inst,unsignedInsn,
371uint64_t Address,
372constMCDisassembler *Decoder);
373
374staticDecodeStatusDecodeSimm9SP(MCInst &Inst,unsignedInsn,uint64_t Address,
375constMCDisassembler *Decoder);
376
377staticDecodeStatusDecodeANDI16Imm(MCInst &Inst,unsignedInsn,
378uint64_t Address,
379constMCDisassembler *Decoder);
380
381staticDecodeStatusDecodeSimm23Lsl2(MCInst &Inst,unsignedInsn,
382uint64_t Address,
383constMCDisassembler *Decoder);
384
385/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
386/// handle.
387template <typename InsnType>
388staticDecodeStatusDecodeINSVE_DF(MCInst &MI, InsnType insn,uint64_t Address,
389constMCDisassembler *Decoder);
390
391template <typename InsnType>
392staticDecodeStatusDecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
393uint64_t Address,
394constMCDisassembler *Decoder);
395
396template <typename InsnType>
397staticDecodeStatusDecodeDAHIDATI(MCInst &MI, InsnType insn,uint64_t Address,
398constMCDisassembler *Decoder);
399
400template <typename InsnType>
401staticDecodeStatusDecodeAddiGroupBranch(MCInst &MI, InsnType insn,
402uint64_t Address,
403constMCDisassembler *Decoder);
404
405template <typename InsnType>
406staticDecodeStatusDecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
407uint64_t Address,
408constMCDisassembler *Decoder);
409
410template <typename InsnType>
411staticDecodeStatusDecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
412uint64_t Address,
413constMCDisassembler *Decoder);
414
415template <typename InsnType>
416staticDecodeStatusDecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
417uint64_t Address,
418constMCDisassembler *Decoder);
419
420template <typename InsnType>
421staticDecodeStatusDecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
422uint64_t Address,
423constMCDisassembler *Decoder);
424
425template <typename InsnType>
426staticDecodeStatusDecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
427uint64_t Address,
428constMCDisassembler *Decoder);
429
430template <typename InsnType>
431staticDecodeStatusDecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
432uint64_t Address,
433constMCDisassembler *Decoder);
434
435template <typename InsnType>
436staticDecodeStatusDecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
437uint64_t Address,
438constMCDisassembler *Decoder);
439
440template <typename InsnType>
441staticDecodeStatusDecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
442uint64_t Address,
443constMCDisassembler *Decoder);
444
445template <typename InsnType>
446staticDecodeStatusDecodeBlezGroupBranch(MCInst &MI, InsnType insn,
447uint64_t Address,
448constMCDisassembler *Decoder);
449
450template <typename InsnType>
451staticDecodeStatusDecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
452uint64_t Address,
453constMCDisassembler *Decoder);
454
455template <typename InsnType>
456staticDecodeStatusDecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
457uint64_t Address,
458constMCDisassembler *Decoder);
459
460template <typename InsnType>
461staticDecodeStatusDecodeDINS(MCInst &MI, InsnTypeInsn,uint64_t Address,
462constMCDisassembler *Decoder);
463
464template <typename InsnType>
465staticDecodeStatusDecodeDEXT(MCInst &MI, InsnTypeInsn,uint64_t Address,
466constMCDisassembler *Decoder);
467
468template <typename InsnType>
469staticDecodeStatusDecodeCRC(MCInst &MI, InsnTypeInsn,uint64_t Address,
470constMCDisassembler *Decoder);
471
472staticDecodeStatusDecodeRegListOperand(MCInst &Inst,unsignedInsn,
473uint64_t Address,
474constMCDisassembler *Decoder);
475
476staticDecodeStatusDecodeRegListOperand16(MCInst &Inst,unsignedInsn,
477uint64_t Address,
478constMCDisassembler *Decoder);
479
480staticDecodeStatusDecodeMovePRegPair(MCInst &Inst,unsigned RegPair,
481uint64_t Address,
482constMCDisassembler *Decoder);
483
484staticDecodeStatusDecodeMovePOperands(MCInst &Inst,unsignedInsn,
485uint64_t Address,
486constMCDisassembler *Decoder);
487
488staticDecodeStatusDecodeFIXMEInstruction(MCInst &Inst,unsignedInsn,
489uint64_t Address,
490constMCDisassembler *Decoder);
491
492staticMCDisassembler *createMipsDisassembler(
493constTarget &T,
494constMCSubtargetInfo &STI,
495MCContext &Ctx) {
496returnnew MipsDisassembler(STI, Ctx,true);
497}
498
499staticMCDisassembler *createMipselDisassembler(
500constTarget &T,
501constMCSubtargetInfo &STI,
502MCContext &Ctx) {
503returnnew MipsDisassembler(STI, Ctx,false);
504}
505
506extern"C"LLVM_EXTERNAL_VISIBILITYvoidLLVMInitializeMipsDisassembler() {
507// Register the disassembler.
508TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(),
509createMipsDisassembler);
510TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(),
511createMipselDisassembler);
512TargetRegistry::RegisterMCDisassembler(getTheMips64Target(),
513createMipsDisassembler);
514TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(),
515createMipselDisassembler);
516}
517
518#include "MipsGenDisassemblerTables.inc"
519
520staticunsignedgetReg(constMCDisassembler *D,unsigned RC,unsigned RegNo) {
521constMCRegisterInfo *RegInfo =D->getContext().getRegisterInfo();
522return *(RegInfo->getRegClass(RC).begin() + RegNo);
523}
524
525template <typename InsnType>
526staticDecodeStatusDecodeINSVE_DF(MCInst &MI, InsnType insn,uint64_t Address,
527constMCDisassembler *Decoder) {
528usingDecodeFN =
529DecodeStatus (*)(MCInst &,unsigned,uint64_t,constMCDisassembler *);
530
531// The size of the n field depends on the element size
532// The register class also depends on this.
533 InsnType tmp = fieldFromInstruction(insn, 17, 5);
534unsigned NSize = 0;
535 DecodeFN RegDecoder =nullptr;
536if ((tmp & 0x18) == 0x00) {// INSVE_B
537 NSize = 4;
538 RegDecoder =DecodeMSA128BRegisterClass;
539 }elseif ((tmp & 0x1c) == 0x10) {// INSVE_H
540 NSize = 3;
541 RegDecoder =DecodeMSA128HRegisterClass;
542 }elseif ((tmp & 0x1e) == 0x18) {// INSVE_W
543 NSize = 2;
544 RegDecoder =DecodeMSA128WRegisterClass;
545 }elseif ((tmp & 0x1f) == 0x1c) {// INSVE_D
546 NSize = 1;
547 RegDecoder =DecodeMSA128DRegisterClass;
548 }else
549llvm_unreachable("Invalid encoding");
550
551assert(NSize != 0 && RegDecoder !=nullptr);
552
553// $wd
554 tmp = fieldFromInstruction(insn, 6, 5);
555if (RegDecoder(MI, tmp,Address, Decoder) ==MCDisassembler::Fail)
556returnMCDisassembler::Fail;
557// $wd_in
558if (RegDecoder(MI, tmp,Address, Decoder) ==MCDisassembler::Fail)
559returnMCDisassembler::Fail;
560// $n
561 tmp = fieldFromInstruction(insn, 16, NSize);
562MI.addOperand(MCOperand::createImm(tmp));
563// $ws
564 tmp = fieldFromInstruction(insn, 11, 5);
565if (RegDecoder(MI, tmp,Address, Decoder) ==MCDisassembler::Fail)
566returnMCDisassembler::Fail;
567// $n2
568MI.addOperand(MCOperand::createImm(0));
569
570returnMCDisassembler::Success;
571}
572
573template <typename InsnType>
574staticDecodeStatusDecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
575uint64_t Address,
576constMCDisassembler *Decoder) {
577 InsnType Rs = fieldFromInstruction(insn, 16, 5);
578 InsnType Imm = fieldFromInstruction(insn, 0, 16);
579MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
580 Rs)));
581MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
582 Rs)));
583MI.addOperand(MCOperand::createImm(Imm));
584
585returnMCDisassembler::Success;
586}
587
588template <typename InsnType>
589staticDecodeStatusDecodeDAHIDATI(MCInst &MI, InsnType insn,uint64_t Address,
590constMCDisassembler *Decoder) {
591 InsnType Rs = fieldFromInstruction(insn, 21, 5);
592 InsnType Imm = fieldFromInstruction(insn, 0, 16);
593MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
594 Rs)));
595MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
596 Rs)));
597MI.addOperand(MCOperand::createImm(Imm));
598
599returnMCDisassembler::Success;
600}
601
602template <typename InsnType>
603staticDecodeStatusDecodeAddiGroupBranch(MCInst &MI, InsnType insn,
604uint64_t Address,
605constMCDisassembler *Decoder) {
606// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
607// (otherwise we would have matched the ADDI instruction from the earlier
608// ISA's instead).
609//
610// We have:
611// 0b001000 sssss ttttt iiiiiiiiiiiiiiii
612// BOVC if rs >= rt
613// BEQZALC if rs == 0 && rt != 0
614// BEQC if rs < rt && rs != 0
615
616 InsnType Rs = fieldFromInstruction(insn, 21, 5);
617 InsnType Rt = fieldFromInstruction(insn, 16, 5);
618 int64_t Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
619bool HasRs =false;
620
621if (Rs >= Rt) {
622MI.setOpcode(Mips::BOVC);
623 HasRs =true;
624 }elseif (Rs != 0 && Rs < Rt) {
625MI.setOpcode(Mips::BEQC);
626 HasRs =true;
627 }else
628MI.setOpcode(Mips::BEQZALC);
629
630if (HasRs)
631MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
632 Rs)));
633
634MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
635 Rt)));
636MI.addOperand(MCOperand::createImm(Imm));
637
638returnMCDisassembler::Success;
639}
640
641template <typename InsnType>
642staticDecodeStatusDecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
643uint64_t Address,
644constMCDisassembler *Decoder) {
645 InsnType Rt = fieldFromInstruction(insn, 21, 5);
646 InsnType Rs = fieldFromInstruction(insn, 16, 5);
647 int64_t Imm = 0;
648
649if (Rs >= Rt) {
650MI.setOpcode(Mips::BOVC_MMR6);
651MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
652 Rt)));
653MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
654 Rs)));
655 Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
656 }elseif (Rs != 0 && Rs < Rt) {
657MI.setOpcode(Mips::BEQC_MMR6);
658MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
659 Rs)));
660MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
661 Rt)));
662 Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
663 }else {
664MI.setOpcode(Mips::BEQZALC_MMR6);
665MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
666 Rt)));
667 Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
668 }
669
670MI.addOperand(MCOperand::createImm(Imm));
671
672returnMCDisassembler::Success;
673}
674
675template <typename InsnType>
676staticDecodeStatusDecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
677uint64_t Address,
678constMCDisassembler *Decoder) {
679// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
680// (otherwise we would have matched the ADDI instruction from the earlier
681// ISA's instead).
682//
683// We have:
684// 0b011000 sssss ttttt iiiiiiiiiiiiiiii
685// BNVC if rs >= rt
686// BNEZALC if rs == 0 && rt != 0
687// BNEC if rs < rt && rs != 0
688
689 InsnType Rs = fieldFromInstruction(insn, 21, 5);
690 InsnType Rt = fieldFromInstruction(insn, 16, 5);
691 int64_t Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
692bool HasRs =false;
693
694if (Rs >= Rt) {
695MI.setOpcode(Mips::BNVC);
696 HasRs =true;
697 }elseif (Rs != 0 && Rs < Rt) {
698MI.setOpcode(Mips::BNEC);
699 HasRs =true;
700 }else
701MI.setOpcode(Mips::BNEZALC);
702
703if (HasRs)
704MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
705 Rs)));
706
707MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
708 Rt)));
709MI.addOperand(MCOperand::createImm(Imm));
710
711returnMCDisassembler::Success;
712}
713
714template <typename InsnType>
715staticDecodeStatusDecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
716uint64_t Address,
717constMCDisassembler *Decoder) {
718 InsnType Rt = fieldFromInstruction(insn, 21, 5);
719 InsnType Rs = fieldFromInstruction(insn, 16, 5);
720 int64_t Imm = 0;
721
722if (Rs >= Rt) {
723MI.setOpcode(Mips::BNVC_MMR6);
724MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
725 Rt)));
726MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
727 Rs)));
728 Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
729 }elseif (Rs != 0 && Rs < Rt) {
730MI.setOpcode(Mips::BNEC_MMR6);
731MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
732 Rs)));
733MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
734 Rt)));
735 Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
736 }else {
737MI.setOpcode(Mips::BNEZALC_MMR6);
738MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
739 Rt)));
740 Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
741 }
742
743MI.addOperand(MCOperand::createImm(Imm));
744
745returnMCDisassembler::Success;
746}
747
748template <typename InsnType>
749staticDecodeStatusDecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
750uint64_t Address,
751constMCDisassembler *Decoder) {
752// We have:
753// 0b110101 ttttt sssss iiiiiiiiiiiiiiii
754// Invalid if rt == 0
755// BGTZC_MMR6 if rs == 0 && rt != 0
756// BLTZC_MMR6 if rs == rt && rt != 0
757// BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
758
759 InsnType Rt = fieldFromInstruction(insn, 21, 5);
760 InsnType Rs = fieldFromInstruction(insn, 16, 5);
761 int64_t Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
762bool HasRs =false;
763
764if (Rt == 0)
765returnMCDisassembler::Fail;
766elseif (Rs == 0)
767MI.setOpcode(Mips::BGTZC_MMR6);
768elseif (Rs == Rt)
769MI.setOpcode(Mips::BLTZC_MMR6);
770else {
771MI.setOpcode(Mips::BLTC_MMR6);
772 HasRs =true;
773 }
774
775if (HasRs)
776MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
777 Rs)));
778
779MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
780 Rt)));
781
782MI.addOperand(MCOperand::createImm(Imm));
783
784returnMCDisassembler::Success;
785}
786
787template <typename InsnType>
788staticDecodeStatusDecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
789uint64_t Address,
790constMCDisassembler *Decoder) {
791// We have:
792// 0b111101 ttttt sssss iiiiiiiiiiiiiiii
793// Invalid if rt == 0
794// BLEZC_MMR6 if rs == 0 && rt != 0
795// BGEZC_MMR6 if rs == rt && rt != 0
796// BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
797
798 InsnType Rt = fieldFromInstruction(insn, 21, 5);
799 InsnType Rs = fieldFromInstruction(insn, 16, 5);
800 int64_t Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
801bool HasRs =false;
802
803if (Rt == 0)
804returnMCDisassembler::Fail;
805elseif (Rs == 0)
806MI.setOpcode(Mips::BLEZC_MMR6);
807elseif (Rs == Rt)
808MI.setOpcode(Mips::BGEZC_MMR6);
809else {
810 HasRs =true;
811MI.setOpcode(Mips::BGEC_MMR6);
812 }
813
814if (HasRs)
815MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
816 Rs)));
817
818MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
819 Rt)));
820
821MI.addOperand(MCOperand::createImm(Imm));
822
823returnMCDisassembler::Success;
824}
825
826template <typename InsnType>
827staticDecodeStatusDecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
828uint64_t Address,
829constMCDisassembler *Decoder) {
830// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
831// (otherwise we would have matched the BLEZL instruction from the earlier
832// ISA's instead).
833//
834// We have:
835// 0b010110 sssss ttttt iiiiiiiiiiiiiiii
836// Invalid if rs == 0
837// BLEZC if rs == 0 && rt != 0
838// BGEZC if rs == rt && rt != 0
839// BGEC if rs != rt && rs != 0 && rt != 0
840
841 InsnType Rs = fieldFromInstruction(insn, 21, 5);
842 InsnType Rt = fieldFromInstruction(insn, 16, 5);
843 int64_t Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
844bool HasRs =false;
845
846if (Rt == 0)
847returnMCDisassembler::Fail;
848elseif (Rs == 0)
849MI.setOpcode(Mips::BLEZC);
850elseif (Rs == Rt)
851MI.setOpcode(Mips::BGEZC);
852else {
853 HasRs =true;
854MI.setOpcode(Mips::BGEC);
855 }
856
857if (HasRs)
858MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
859 Rs)));
860
861MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
862 Rt)));
863
864MI.addOperand(MCOperand::createImm(Imm));
865
866returnMCDisassembler::Success;
867}
868
869template <typename InsnType>
870staticDecodeStatusDecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
871uint64_t Address,
872constMCDisassembler *Decoder) {
873// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
874// (otherwise we would have matched the BGTZL instruction from the earlier
875// ISA's instead).
876//
877// We have:
878// 0b010111 sssss ttttt iiiiiiiiiiiiiiii
879// Invalid if rs == 0
880// BGTZC if rs == 0 && rt != 0
881// BLTZC if rs == rt && rt != 0
882// BLTC if rs != rt && rs != 0 && rt != 0
883
884bool HasRs =false;
885
886 InsnType Rs = fieldFromInstruction(insn, 21, 5);
887 InsnType Rt = fieldFromInstruction(insn, 16, 5);
888 int64_t Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
889
890if (Rt == 0)
891returnMCDisassembler::Fail;
892elseif (Rs == 0)
893MI.setOpcode(Mips::BGTZC);
894elseif (Rs == Rt)
895MI.setOpcode(Mips::BLTZC);
896else {
897MI.setOpcode(Mips::BLTC);
898 HasRs =true;
899 }
900
901if (HasRs)
902MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
903 Rs)));
904
905MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
906 Rt)));
907
908MI.addOperand(MCOperand::createImm(Imm));
909
910returnMCDisassembler::Success;
911}
912
913template <typename InsnType>
914staticDecodeStatusDecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
915uint64_t Address,
916constMCDisassembler *Decoder) {
917// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
918// (otherwise we would have matched the BGTZ instruction from the earlier
919// ISA's instead).
920//
921// We have:
922// 0b000111 sssss ttttt iiiiiiiiiiiiiiii
923// BGTZ if rt == 0
924// BGTZALC if rs == 0 && rt != 0
925// BLTZALC if rs != 0 && rs == rt
926// BLTUC if rs != 0 && rs != rt
927
928 InsnType Rs = fieldFromInstruction(insn, 21, 5);
929 InsnType Rt = fieldFromInstruction(insn, 16, 5);
930 int64_t Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
931bool HasRs =false;
932bool HasRt =false;
933
934if (Rt == 0) {
935MI.setOpcode(Mips::BGTZ);
936 HasRs =true;
937 }elseif (Rs == 0) {
938MI.setOpcode(Mips::BGTZALC);
939 HasRt =true;
940 }elseif (Rs == Rt) {
941MI.setOpcode(Mips::BLTZALC);
942 HasRs =true;
943 }else {
944MI.setOpcode(Mips::BLTUC);
945 HasRs =true;
946 HasRt =true;
947 }
948
949if (HasRs)
950MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
951 Rs)));
952
953if (HasRt)
954MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
955 Rt)));
956
957MI.addOperand(MCOperand::createImm(Imm));
958
959returnMCDisassembler::Success;
960}
961
962template <typename InsnType>
963staticDecodeStatusDecodeBlezGroupBranch(MCInst &MI, InsnType insn,
964uint64_t Address,
965constMCDisassembler *Decoder) {
966// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
967// (otherwise we would have matched the BLEZL instruction from the earlier
968// ISA's instead).
969//
970// We have:
971// 0b000110 sssss ttttt iiiiiiiiiiiiiiii
972// Invalid if rs == 0
973// BLEZALC if rs == 0 && rt != 0
974// BGEZALC if rs == rt && rt != 0
975// BGEUC if rs != rt && rs != 0 && rt != 0
976
977 InsnType Rs = fieldFromInstruction(insn, 21, 5);
978 InsnType Rt = fieldFromInstruction(insn, 16, 5);
979 int64_t Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
980bool HasRs =false;
981
982if (Rt == 0)
983returnMCDisassembler::Fail;
984elseif (Rs == 0)
985MI.setOpcode(Mips::BLEZALC);
986elseif (Rs == Rt)
987MI.setOpcode(Mips::BGEZALC);
988else {
989 HasRs =true;
990MI.setOpcode(Mips::BGEUC);
991 }
992
993if (HasRs)
994MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
995 Rs)));
996MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
997 Rt)));
998
999MI.addOperand(MCOperand::createImm(Imm));
1000
1001returnMCDisassembler::Success;
1002}
1003
1004// Override the generated disassembler to produce DEXT all the time. This is
1005// for feature / behaviour parity with binutils.
1006template <typename InsnType>
1007staticDecodeStatusDecodeDEXT(MCInst &MI, InsnTypeInsn,uint64_t Address,
1008constMCDisassembler *Decoder) {
1009unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1010unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1011unsignedSize = 0;
1012unsigned Pos = 0;
1013
1014switch (MI.getOpcode()) {
1015case Mips::DEXT:
1016 Pos = Lsb;
1017Size = Msbd + 1;
1018break;
1019case Mips::DEXTM:
1020 Pos = Lsb;
1021Size = Msbd + 1 + 32;
1022break;
1023case Mips::DEXTU:
1024 Pos = Lsb + 32;
1025Size = Msbd + 1;
1026break;
1027default:
1028llvm_unreachable("Unknown DEXT instruction!");
1029 }
1030
1031MI.setOpcode(Mips::DEXT);
1032
1033 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1034 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1035
1036MI.addOperand(
1037MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1038MI.addOperand(
1039MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1040MI.addOperand(MCOperand::createImm(Pos));
1041MI.addOperand(MCOperand::createImm(Size));
1042
1043returnMCDisassembler::Success;
1044}
1045
1046// Override the generated disassembler to produce DINS all the time. This is
1047// for feature / behaviour parity with binutils.
1048template <typename InsnType>
1049staticDecodeStatusDecodeDINS(MCInst &MI, InsnTypeInsn,uint64_t Address,
1050constMCDisassembler *Decoder) {
1051unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1052unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1053unsignedSize = 0;
1054unsigned Pos = 0;
1055
1056switch (MI.getOpcode()) {
1057case Mips::DINS:
1058 Pos = Lsb;
1059Size = Msbd + 1 - Pos;
1060break;
1061case Mips::DINSM:
1062 Pos = Lsb;
1063Size = Msbd + 33 - Pos;
1064break;
1065case Mips::DINSU:
1066 Pos = Lsb + 32;
1067// mbsd = pos + size - 33
1068// mbsd - pos + 33 = size
1069Size = Msbd + 33 - Pos;
1070break;
1071default:
1072llvm_unreachable("Unknown DINS instruction!");
1073 }
1074
1075 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1076 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1077
1078MI.setOpcode(Mips::DINS);
1079MI.addOperand(
1080MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1081MI.addOperand(
1082MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1083MI.addOperand(MCOperand::createImm(Pos));
1084MI.addOperand(MCOperand::createImm(Size));
1085
1086returnMCDisassembler::Success;
1087}
1088
1089// Auto-generated decoder wouldn't add the third operand for CRC32*.
1090template <typename InsnType>
1091staticDecodeStatusDecodeCRC(MCInst &MI, InsnTypeInsn,uint64_t Address,
1092constMCDisassembler *Decoder) {
1093 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1094 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1095MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1096 Rt)));
1097MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1098 Rs)));
1099MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1100 Rt)));
1101returnMCDisassembler::Success;
1102}
1103
1104/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1105/// according to the given endianness.
1106staticDecodeStatusreadInstruction16(ArrayRef<uint8_t> Bytes,uint64_t Address,
1107uint64_t &Size,uint32_t &Insn,
1108bool IsBigEndian) {
1109// We want to read exactly 2 Bytes of data.
1110if (Bytes.size() < 2) {
1111Size = 0;
1112returnMCDisassembler::Fail;
1113 }
1114
1115if (IsBigEndian) {
1116Insn = (Bytes[0] << 8) | Bytes[1];
1117 }else {
1118Insn = (Bytes[1] << 8) | Bytes[0];
1119 }
1120
1121returnMCDisassembler::Success;
1122}
1123
1124/// Read four bytes from the ArrayRef and return 32 bit word sorted
1125/// according to the given endianness.
1126staticDecodeStatusreadInstruction32(ArrayRef<uint8_t> Bytes,uint64_t Address,
1127uint64_t &Size,uint32_t &Insn,
1128bool IsBigEndian,bool IsMicroMips) {
1129// We want to read exactly 4 Bytes of data.
1130if (Bytes.size() < 4) {
1131Size = 0;
1132returnMCDisassembler::Fail;
1133 }
1134
1135// High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1136// always precede the low 16 bits in the instruction stream (that is, they
1137// are placed at lower addresses in the instruction stream).
1138//
1139// microMIPS byte ordering:
1140// Big-endian: 0 | 1 | 2 | 3
1141// Little-endian: 1 | 0 | 3 | 2
1142
1143if (IsBigEndian) {
1144// Encoded as a big-endian 32-bit word in the stream.
1145Insn =
1146 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1147 }else {
1148if (IsMicroMips) {
1149Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1150 (Bytes[1] << 24);
1151 }else {
1152Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1153 (Bytes[3] << 24);
1154 }
1155 }
1156
1157returnMCDisassembler::Success;
1158}
1159
1160DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr,uint64_t &Size,
1161ArrayRef<uint8_t> Bytes,
1162uint64_t Address,
1163raw_ostream &CStream) const{
1164uint32_tInsn;
1165DecodeStatusResult;
1166Size = 0;
1167
1168if (IsMicroMips) {
1169Result =readInstruction16(Bytes, Address,Size,Insn, IsBigEndian);
1170if (Result ==MCDisassembler::Fail)
1171returnMCDisassembler::Fail;
1172
1173if (hasMips32r6()) {
1174LLVM_DEBUG(
1175dbgs() <<"Trying MicroMipsR616 table (16-bit instructions):\n");
1176// Calling the auto-generated decoder function for microMIPS32R6
1177// 16-bit instructions.
1178Result = decodeInstruction(DecoderTableMicroMipsR616, Instr,Insn,
1179 Address,this, STI);
1180if (Result !=MCDisassembler::Fail) {
1181Size = 2;
1182returnResult;
1183 }
1184 }
1185
1186LLVM_DEBUG(dbgs() <<"Trying MicroMips16 table (16-bit instructions):\n");
1187// Calling the auto-generated decoder function for microMIPS 16-bit
1188// instructions.
1189Result = decodeInstruction(DecoderTableMicroMips16, Instr,Insn, Address,
1190this, STI);
1191if (Result !=MCDisassembler::Fail) {
1192Size = 2;
1193returnResult;
1194 }
1195
1196Result =readInstruction32(Bytes, Address,Size,Insn, IsBigEndian,true);
1197if (Result ==MCDisassembler::Fail)
1198returnMCDisassembler::Fail;
1199
1200if (hasMips32r6()) {
1201LLVM_DEBUG(
1202dbgs() <<"Trying MicroMips32r632 table (32-bit instructions):\n");
1203// Calling the auto-generated decoder function.
1204Result = decodeInstruction(DecoderTableMicroMipsR632, Instr,Insn,
1205 Address,this, STI);
1206if (Result !=MCDisassembler::Fail) {
1207Size = 4;
1208returnResult;
1209 }
1210 }
1211
1212LLVM_DEBUG(dbgs() <<"Trying MicroMips32 table (32-bit instructions):\n");
1213// Calling the auto-generated decoder function.
1214Result = decodeInstruction(DecoderTableMicroMips32, Instr,Insn, Address,
1215this, STI);
1216if (Result !=MCDisassembler::Fail) {
1217Size = 4;
1218returnResult;
1219 }
1220
1221if (isFP64()) {
1222LLVM_DEBUG(dbgs() <<"Trying MicroMipsFP64 table (32-bit opcodes):\n");
1223Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr,Insn,
1224 Address,this, STI);
1225if (Result !=MCDisassembler::Fail) {
1226Size = 4;
1227returnResult;
1228 }
1229 }
1230
1231// This is an invalid instruction. Claim that the Size is 2 bytes. Since
1232// microMIPS instructions have a minimum alignment of 2, the next 2 bytes
1233// could form a valid instruction. The two bytes we rejected as an
1234// instruction could have actually beeen an inline constant pool that is
1235// unconditionally branched over.
1236Size = 2;
1237returnMCDisassembler::Fail;
1238 }
1239
1240// Attempt to read the instruction so that we can attempt to decode it. If
1241// the buffer is not 4 bytes long, let the higher level logic figure out
1242// what to do with a size of zero and MCDisassembler::Fail.
1243Result =readInstruction32(Bytes, Address,Size,Insn, IsBigEndian,false);
1244if (Result ==MCDisassembler::Fail)
1245returnMCDisassembler::Fail;
1246
1247// The only instruction size for standard encoded MIPS.
1248Size = 4;
1249
1250if (hasCOP3()) {
1251LLVM_DEBUG(dbgs() <<"Trying COP3_ table (32-bit opcodes):\n");
1252Result =
1253 decodeInstruction(DecoderTableCOP3_32, Instr,Insn, Address,this, STI);
1254if (Result !=MCDisassembler::Fail)
1255returnResult;
1256 }
1257
1258if (hasMips32r6() && isGP64()) {
1259LLVM_DEBUG(
1260dbgs() <<"Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1261Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr,Insn,
1262 Address,this, STI);
1263if (Result !=MCDisassembler::Fail)
1264returnResult;
1265 }
1266
1267if (hasMips32r6() && isPTR64()) {
1268LLVM_DEBUG(
1269dbgs() <<"Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1270Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr,Insn,
1271 Address,this, STI);
1272if (Result !=MCDisassembler::Fail)
1273returnResult;
1274 }
1275
1276if (hasMips32r6()) {
1277LLVM_DEBUG(dbgs() <<"Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1278Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr,Insn,
1279 Address,this, STI);
1280if (Result !=MCDisassembler::Fail)
1281returnResult;
1282 }
1283
1284if (hasMips2() && isPTR64()) {
1285LLVM_DEBUG(
1286dbgs() <<"Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1287Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr,Insn,
1288 Address,this, STI);
1289if (Result !=MCDisassembler::Fail)
1290returnResult;
1291 }
1292
1293if (hasCnMips()) {
1294LLVM_DEBUG(dbgs() <<"Trying CnMips table (32-bit opcodes):\n");
1295Result = decodeInstruction(DecoderTableCnMips32, Instr,Insn,
1296 Address,this, STI);
1297if (Result !=MCDisassembler::Fail)
1298returnResult;
1299 }
1300
1301if (hasCnMipsP()) {
1302LLVM_DEBUG(dbgs() <<"Trying CnMipsP table (32-bit opcodes):\n");
1303Result = decodeInstruction(DecoderTableCnMipsP32, Instr,Insn,
1304 Address,this, STI);
1305if (Result !=MCDisassembler::Fail)
1306returnResult;
1307 }
1308
1309if (isGP64()) {
1310LLVM_DEBUG(dbgs() <<"Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1311Result = decodeInstruction(DecoderTableMips6432, Instr,Insn,
1312 Address,this, STI);
1313if (Result !=MCDisassembler::Fail)
1314returnResult;
1315 }
1316
1317if (isFP64()) {
1318LLVM_DEBUG(
1319dbgs() <<"Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
1320Result = decodeInstruction(DecoderTableMipsFP6432, Instr,Insn,
1321 Address,this, STI);
1322if (Result !=MCDisassembler::Fail)
1323returnResult;
1324 }
1325
1326LLVM_DEBUG(dbgs() <<"Trying Mips table (32-bit opcodes):\n");
1327// Calling the auto-generated decoder function.
1328Result =
1329 decodeInstruction(DecoderTableMips32, Instr,Insn, Address,this, STI);
1330if (Result !=MCDisassembler::Fail)
1331returnResult;
1332
1333returnMCDisassembler::Fail;
1334}
1335
1336staticDecodeStatus
1337DecodeCPU16RegsRegisterClass(MCInst &Inst,unsigned RegNo,uint64_t Address,
1338constMCDisassembler *Decoder) {
1339returnMCDisassembler::Fail;
1340}
1341
1342staticDecodeStatusDecodeGPR64RegisterClass(MCInst &Inst,unsigned RegNo,
1343uint64_t Address,
1344constMCDisassembler *Decoder) {
1345if (RegNo > 31)
1346returnMCDisassembler::Fail;
1347
1348unsigned Reg =getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1349 Inst.addOperand(MCOperand::createReg(Reg));
1350returnMCDisassembler::Success;
1351}
1352
1353staticDecodeStatusDecodeGPRMM16RegisterClass(MCInst &Inst,unsigned RegNo,
1354uint64_t Address,
1355constMCDisassembler *Decoder) {
1356if (RegNo > 7)
1357returnMCDisassembler::Fail;
1358unsigned Reg =getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1359 Inst.addOperand(MCOperand::createReg(Reg));
1360returnMCDisassembler::Success;
1361}
1362
1363staticDecodeStatus
1364DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,unsigned RegNo,uint64_t Address,
1365constMCDisassembler *Decoder) {
1366if (RegNo > 7)
1367returnMCDisassembler::Fail;
1368unsigned Reg =getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1369 Inst.addOperand(MCOperand::createReg(Reg));
1370returnMCDisassembler::Success;
1371}
1372
1373staticDecodeStatus
1374DecodeGPRMM16MovePRegisterClass(MCInst &Inst,unsigned RegNo,uint64_t Address,
1375constMCDisassembler *Decoder) {
1376if (RegNo > 7)
1377returnMCDisassembler::Fail;
1378unsigned Reg =getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1379 Inst.addOperand(MCOperand::createReg(Reg));
1380returnMCDisassembler::Success;
1381}
1382
1383staticDecodeStatusDecodeGPR32RegisterClass(MCInst &Inst,unsigned RegNo,
1384uint64_t Address,
1385constMCDisassembler *Decoder) {
1386if (RegNo > 31)
1387returnMCDisassembler::Fail;
1388unsigned Reg =getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1389 Inst.addOperand(MCOperand::createReg(Reg));
1390returnMCDisassembler::Success;
1391}
1392
1393staticDecodeStatusDecodePtrRegisterClass(MCInst &Inst,unsigned RegNo,
1394uint64_t Address,
1395constMCDisassembler *Decoder) {
1396if (static_cast<constMipsDisassembler *>(Decoder)->isGP64())
1397returnDecodeGPR64RegisterClass(Inst, RegNo,Address, Decoder);
1398
1399returnDecodeGPR32RegisterClass(Inst, RegNo,Address, Decoder);
1400}
1401
1402staticDecodeStatusDecodeDSPRRegisterClass(MCInst &Inst,unsigned RegNo,
1403uint64_t Address,
1404constMCDisassembler *Decoder) {
1405returnDecodeGPR32RegisterClass(Inst, RegNo,Address, Decoder);
1406}
1407
1408staticDecodeStatusDecodeFGR64RegisterClass(MCInst &Inst,unsigned RegNo,
1409uint64_t Address,
1410constMCDisassembler *Decoder) {
1411if (RegNo > 31)
1412returnMCDisassembler::Fail;
1413
1414unsigned Reg =getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1415 Inst.addOperand(MCOperand::createReg(Reg));
1416returnMCDisassembler::Success;
1417}
1418
1419staticDecodeStatusDecodeFGR32RegisterClass(MCInst &Inst,unsigned RegNo,
1420uint64_t Address,
1421constMCDisassembler *Decoder) {
1422if (RegNo > 31)
1423returnMCDisassembler::Fail;
1424
1425unsigned Reg =getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1426 Inst.addOperand(MCOperand::createReg(Reg));
1427returnMCDisassembler::Success;
1428}
1429
1430staticDecodeStatusDecodeCCRRegisterClass(MCInst &Inst,unsigned RegNo,
1431uint64_t Address,
1432constMCDisassembler *Decoder) {
1433if (RegNo > 31)
1434returnMCDisassembler::Fail;
1435unsigned Reg =getReg(Decoder, Mips::CCRRegClassID, RegNo);
1436 Inst.addOperand(MCOperand::createReg(Reg));
1437returnMCDisassembler::Success;
1438}
1439
1440staticDecodeStatusDecodeFCCRegisterClass(MCInst &Inst,unsigned RegNo,
1441uint64_t Address,
1442constMCDisassembler *Decoder) {
1443if (RegNo > 7)
1444returnMCDisassembler::Fail;
1445unsigned Reg =getReg(Decoder, Mips::FCCRegClassID, RegNo);
1446 Inst.addOperand(MCOperand::createReg(Reg));
1447returnMCDisassembler::Success;
1448}
1449
1450staticDecodeStatusDecodeFGRCCRegisterClass(MCInst &Inst,unsigned RegNo,
1451uint64_t Address,
1452constMCDisassembler *Decoder) {
1453if (RegNo > 31)
1454returnMCDisassembler::Fail;
1455
1456unsigned Reg =getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1457 Inst.addOperand(MCOperand::createReg(Reg));
1458returnMCDisassembler::Success;
1459}
1460
1461staticDecodeStatusDecodeMem(MCInst &Inst,unsignedInsn,uint64_t Address,
1462constMCDisassembler *Decoder) {
1463intOffset = SignExtend32<16>(Insn & 0xffff);
1464unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1465unsignedBase = fieldFromInstruction(Insn, 21, 5);
1466
1467 Reg =getReg(Decoder, Mips::GPR32RegClassID, Reg);
1468Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1469
1470if (Inst.getOpcode() == Mips::SC ||
1471 Inst.getOpcode() == Mips::SCD)
1472 Inst.addOperand(MCOperand::createReg(Reg));
1473
1474 Inst.addOperand(MCOperand::createReg(Reg));
1475 Inst.addOperand(MCOperand::createReg(Base));
1476 Inst.addOperand(MCOperand::createImm(Offset));
1477
1478returnMCDisassembler::Success;
1479}
1480
1481staticDecodeStatusDecodeMemEVA(MCInst &Inst,unsignedInsn,uint64_t Address,
1482constMCDisassembler *Decoder) {
1483intOffset = SignExtend32<9>(Insn >> 7);
1484unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1485unsignedBase = fieldFromInstruction(Insn, 21, 5);
1486
1487 Reg =getReg(Decoder, Mips::GPR32RegClassID, Reg);
1488Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1489
1490if (Inst.getOpcode() == Mips::SCE)
1491 Inst.addOperand(MCOperand::createReg(Reg));
1492
1493 Inst.addOperand(MCOperand::createReg(Reg));
1494 Inst.addOperand(MCOperand::createReg(Base));
1495 Inst.addOperand(MCOperand::createImm(Offset));
1496
1497returnMCDisassembler::Success;
1498}
1499
1500staticDecodeStatusDecodeLoadByte15(MCInst &Inst,unsignedInsn,
1501uint64_t Address,
1502constMCDisassembler *Decoder) {
1503intOffset = SignExtend32<16>(Insn & 0xffff);
1504unsignedBase = fieldFromInstruction(Insn, 16, 5);
1505unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1506
1507Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1508 Reg =getReg(Decoder, Mips::GPR32RegClassID, Reg);
1509
1510 Inst.addOperand(MCOperand::createReg(Reg));
1511 Inst.addOperand(MCOperand::createReg(Base));
1512 Inst.addOperand(MCOperand::createImm(Offset));
1513
1514returnMCDisassembler::Success;
1515}
1516
1517staticDecodeStatusDecodeCacheOp(MCInst &Inst,unsignedInsn,uint64_t Address,
1518constMCDisassembler *Decoder) {
1519intOffset = SignExtend32<16>(Insn & 0xffff);
1520unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1521unsignedBase = fieldFromInstruction(Insn, 21, 5);
1522
1523Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1524
1525 Inst.addOperand(MCOperand::createReg(Base));
1526 Inst.addOperand(MCOperand::createImm(Offset));
1527 Inst.addOperand(MCOperand::createImm(Hint));
1528
1529returnMCDisassembler::Success;
1530}
1531
1532staticDecodeStatusDecodeCacheOpMM(MCInst &Inst,unsignedInsn,
1533uint64_t Address,
1534constMCDisassembler *Decoder) {
1535intOffset = SignExtend32<12>(Insn & 0xfff);
1536unsignedBase = fieldFromInstruction(Insn, 16, 5);
1537unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1538
1539Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1540
1541 Inst.addOperand(MCOperand::createReg(Base));
1542 Inst.addOperand(MCOperand::createImm(Offset));
1543 Inst.addOperand(MCOperand::createImm(Hint));
1544
1545returnMCDisassembler::Success;
1546}
1547
1548staticDecodeStatusDecodePrefeOpMM(MCInst &Inst,unsignedInsn,
1549uint64_t Address,
1550constMCDisassembler *Decoder) {
1551intOffset = SignExtend32<9>(Insn & 0x1ff);
1552unsignedBase = fieldFromInstruction(Insn, 16, 5);
1553unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1554
1555Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1556
1557 Inst.addOperand(MCOperand::createReg(Base));
1558 Inst.addOperand(MCOperand::createImm(Offset));
1559 Inst.addOperand(MCOperand::createImm(Hint));
1560
1561returnMCDisassembler::Success;
1562}
1563
1564staticDecodeStatusDecodeCacheeOp_CacheOpR6(MCInst &Inst,unsignedInsn,
1565uint64_t Address,
1566constMCDisassembler *Decoder) {
1567intOffset = SignExtend32<9>(Insn >> 7);
1568unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1569unsignedBase = fieldFromInstruction(Insn, 21, 5);
1570
1571Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1572
1573 Inst.addOperand(MCOperand::createReg(Base));
1574 Inst.addOperand(MCOperand::createImm(Offset));
1575 Inst.addOperand(MCOperand::createImm(Hint));
1576
1577returnMCDisassembler::Success;
1578}
1579
1580staticDecodeStatusDecodeSyncI(MCInst &Inst,unsignedInsn,uint64_t Address,
1581constMCDisassembler *Decoder) {
1582intOffset = SignExtend32<16>(Insn & 0xffff);
1583unsignedBase = fieldFromInstruction(Insn, 21, 5);
1584
1585Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1586
1587 Inst.addOperand(MCOperand::createReg(Base));
1588 Inst.addOperand(MCOperand::createImm(Offset));
1589
1590returnMCDisassembler::Success;
1591}
1592
1593staticDecodeStatusDecodeSyncI_MM(MCInst &Inst,unsignedInsn,
1594uint64_t Address,
1595constMCDisassembler *Decoder) {
1596intOffset = SignExtend32<16>(Insn & 0xffff);
1597unsignedBase = fieldFromInstruction(Insn, 16, 5);
1598
1599Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1600
1601 Inst.addOperand(MCOperand::createReg(Base));
1602 Inst.addOperand(MCOperand::createImm(Offset));
1603
1604returnMCDisassembler::Success;
1605}
1606
1607staticDecodeStatusDecodeSynciR6(MCInst &Inst,unsignedInsn,uint64_t Address,
1608constMCDisassembler *Decoder) {
1609int Immediate = SignExtend32<16>(Insn & 0xffff);
1610unsignedBase = fieldFromInstruction(Insn, 16, 5);
1611
1612Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1613
1614 Inst.addOperand(MCOperand::createReg(Base));
1615 Inst.addOperand(MCOperand::createImm(Immediate));
1616
1617returnMCDisassembler::Success;
1618}
1619
1620staticDecodeStatusDecodeMSA128Mem(MCInst &Inst,unsignedInsn,
1621uint64_t Address,
1622constMCDisassembler *Decoder) {
1623intOffset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1624unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1625unsignedBase = fieldFromInstruction(Insn, 11, 5);
1626
1627 Reg =getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1628Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1629
1630 Inst.addOperand(MCOperand::createReg(Reg));
1631 Inst.addOperand(MCOperand::createReg(Base));
1632
1633// The immediate field of an LD/ST instruction is scaled which means it must
1634// be multiplied (when decoding) by the size (in bytes) of the instructions'
1635// data format.
1636// .b - 1 byte
1637// .h - 2 bytes
1638// .w - 4 bytes
1639// .d - 8 bytes
1640switch(Inst.getOpcode())
1641 {
1642default:
1643assert(false &&"Unexpected instruction");
1644returnMCDisassembler::Fail;
1645break;
1646case Mips::LD_B:
1647case Mips::ST_B:
1648 Inst.addOperand(MCOperand::createImm(Offset));
1649break;
1650case Mips::LD_H:
1651case Mips::ST_H:
1652 Inst.addOperand(MCOperand::createImm(Offset * 2));
1653break;
1654case Mips::LD_W:
1655case Mips::ST_W:
1656 Inst.addOperand(MCOperand::createImm(Offset * 4));
1657break;
1658case Mips::LD_D:
1659case Mips::ST_D:
1660 Inst.addOperand(MCOperand::createImm(Offset * 8));
1661break;
1662 }
1663
1664returnMCDisassembler::Success;
1665}
1666
1667staticDecodeStatusDecodeMemMMImm4(MCInst &Inst,unsignedInsn,
1668uint64_t Address,
1669constMCDisassembler *Decoder) {
1670unsignedOffset =Insn & 0xf;
1671unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1672unsignedBase = fieldFromInstruction(Insn, 4, 3);
1673
1674switch (Inst.getOpcode()) {
1675case Mips::LBU16_MM:
1676case Mips::LHU16_MM:
1677case Mips::LW16_MM:
1678if (DecodeGPRMM16RegisterClass(Inst, Reg,Address, Decoder)
1679 ==MCDisassembler::Fail)
1680returnMCDisassembler::Fail;
1681break;
1682case Mips::SB16_MM:
1683case Mips::SB16_MMR6:
1684case Mips::SH16_MM:
1685case Mips::SH16_MMR6:
1686case Mips::SW16_MM:
1687case Mips::SW16_MMR6:
1688if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg,Address, Decoder)
1689 ==MCDisassembler::Fail)
1690returnMCDisassembler::Fail;
1691break;
1692 }
1693
1694if (DecodeGPRMM16RegisterClass(Inst,Base,Address, Decoder)
1695 ==MCDisassembler::Fail)
1696returnMCDisassembler::Fail;
1697
1698switch (Inst.getOpcode()) {
1699case Mips::LBU16_MM:
1700if (Offset == 0xf)
1701 Inst.addOperand(MCOperand::createImm(-1));
1702else
1703 Inst.addOperand(MCOperand::createImm(Offset));
1704break;
1705case Mips::SB16_MM:
1706case Mips::SB16_MMR6:
1707 Inst.addOperand(MCOperand::createImm(Offset));
1708break;
1709case Mips::LHU16_MM:
1710case Mips::SH16_MM:
1711case Mips::SH16_MMR6:
1712 Inst.addOperand(MCOperand::createImm(Offset << 1));
1713break;
1714case Mips::LW16_MM:
1715case Mips::SW16_MM:
1716case Mips::SW16_MMR6:
1717 Inst.addOperand(MCOperand::createImm(Offset << 2));
1718break;
1719 }
1720
1721returnMCDisassembler::Success;
1722}
1723
1724staticDecodeStatusDecodeMemMMSPImm5Lsl2(MCInst &Inst,unsignedInsn,
1725uint64_t Address,
1726constMCDisassembler *Decoder) {
1727unsignedOffset =Insn & 0x1F;
1728unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1729
1730 Reg =getReg(Decoder, Mips::GPR32RegClassID, Reg);
1731
1732 Inst.addOperand(MCOperand::createReg(Reg));
1733 Inst.addOperand(MCOperand::createReg(Mips::SP));
1734 Inst.addOperand(MCOperand::createImm(Offset << 2));
1735
1736returnMCDisassembler::Success;
1737}
1738
1739staticDecodeStatusDecodeMemMMGPImm7Lsl2(MCInst &Inst,unsignedInsn,
1740uint64_t Address,
1741constMCDisassembler *Decoder) {
1742unsignedOffset =Insn & 0x7F;
1743unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1744
1745 Reg =getReg(Decoder, Mips::GPR32RegClassID, Reg);
1746
1747 Inst.addOperand(MCOperand::createReg(Reg));
1748 Inst.addOperand(MCOperand::createReg(Mips::GP));
1749 Inst.addOperand(MCOperand::createImm(Offset << 2));
1750
1751returnMCDisassembler::Success;
1752}
1753
1754staticDecodeStatusDecodeMemMMReglistImm4Lsl2(MCInst &Inst,unsignedInsn,
1755uint64_t Address,
1756constMCDisassembler *Decoder) {
1757intOffset;
1758switch (Inst.getOpcode()) {
1759case Mips::LWM16_MMR6:
1760case Mips::SWM16_MMR6:
1761Offset = fieldFromInstruction(Insn, 4, 4);
1762break;
1763default:
1764Offset = SignExtend32<4>(Insn & 0xf);
1765break;
1766 }
1767
1768if (DecodeRegListOperand16(Inst,Insn,Address, Decoder)
1769 ==MCDisassembler::Fail)
1770returnMCDisassembler::Fail;
1771
1772 Inst.addOperand(MCOperand::createReg(Mips::SP));
1773 Inst.addOperand(MCOperand::createImm(Offset << 2));
1774
1775returnMCDisassembler::Success;
1776}
1777
1778staticDecodeStatusDecodeMemMMImm9(MCInst &Inst,unsignedInsn,
1779uint64_t Address,
1780constMCDisassembler *Decoder) {
1781intOffset = SignExtend32<9>(Insn & 0x1ff);
1782unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1783unsignedBase = fieldFromInstruction(Insn, 16, 5);
1784
1785 Reg =getReg(Decoder, Mips::GPR32RegClassID, Reg);
1786Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1787
1788if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1789 Inst.addOperand(MCOperand::createReg(Reg));
1790
1791 Inst.addOperand(MCOperand::createReg(Reg));
1792 Inst.addOperand(MCOperand::createReg(Base));
1793 Inst.addOperand(MCOperand::createImm(Offset));
1794
1795returnMCDisassembler::Success;
1796}
1797
1798staticDecodeStatusDecodeMemMMImm12(MCInst &Inst,unsignedInsn,
1799uint64_t Address,
1800constMCDisassembler *Decoder) {
1801intOffset = SignExtend32<12>(Insn & 0x0fff);
1802unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1803unsignedBase = fieldFromInstruction(Insn, 16, 5);
1804
1805 Reg =getReg(Decoder, Mips::GPR32RegClassID, Reg);
1806Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1807
1808switch (Inst.getOpcode()) {
1809case Mips::SWM32_MM:
1810case Mips::LWM32_MM:
1811if (DecodeRegListOperand(Inst,Insn,Address, Decoder)
1812 ==MCDisassembler::Fail)
1813returnMCDisassembler::Fail;
1814 Inst.addOperand(MCOperand::createReg(Base));
1815 Inst.addOperand(MCOperand::createImm(Offset));
1816break;
1817case Mips::SC_MM:
1818 Inst.addOperand(MCOperand::createReg(Reg));
1819 [[fallthrough]];
1820default:
1821 Inst.addOperand(MCOperand::createReg(Reg));
1822if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1823 Inst.addOperand(MCOperand::createReg(Reg+1));
1824
1825 Inst.addOperand(MCOperand::createReg(Base));
1826 Inst.addOperand(MCOperand::createImm(Offset));
1827 }
1828
1829returnMCDisassembler::Success;
1830}
1831
1832staticDecodeStatusDecodeMemMMImm16(MCInst &Inst,unsignedInsn,
1833uint64_t Address,
1834constMCDisassembler *Decoder) {
1835intOffset = SignExtend32<16>(Insn & 0xffff);
1836unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1837unsignedBase = fieldFromInstruction(Insn, 16, 5);
1838
1839 Reg =getReg(Decoder, Mips::GPR32RegClassID, Reg);
1840Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1841
1842 Inst.addOperand(MCOperand::createReg(Reg));
1843 Inst.addOperand(MCOperand::createReg(Base));
1844 Inst.addOperand(MCOperand::createImm(Offset));
1845
1846returnMCDisassembler::Success;
1847}
1848
1849staticDecodeStatusDecodeFMem(MCInst &Inst,unsignedInsn,uint64_t Address,
1850constMCDisassembler *Decoder) {
1851intOffset = SignExtend32<16>(Insn & 0xffff);
1852unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1853unsignedBase = fieldFromInstruction(Insn, 21, 5);
1854
1855 Reg =getReg(Decoder, Mips::FGR64RegClassID, Reg);
1856Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1857
1858 Inst.addOperand(MCOperand::createReg(Reg));
1859 Inst.addOperand(MCOperand::createReg(Base));
1860 Inst.addOperand(MCOperand::createImm(Offset));
1861
1862returnMCDisassembler::Success;
1863}
1864
1865staticDecodeStatusDecodeFMemMMR2(MCInst &Inst,unsignedInsn,
1866uint64_t Address,
1867constMCDisassembler *Decoder) {
1868// This function is the same as DecodeFMem but with the Reg and Base fields
1869// swapped according to microMIPS spec.
1870intOffset = SignExtend32<16>(Insn & 0xffff);
1871unsignedBase = fieldFromInstruction(Insn, 16, 5);
1872unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1873
1874 Reg =getReg(Decoder, Mips::FGR64RegClassID, Reg);
1875Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1876
1877 Inst.addOperand(MCOperand::createReg(Reg));
1878 Inst.addOperand(MCOperand::createReg(Base));
1879 Inst.addOperand(MCOperand::createImm(Offset));
1880
1881returnMCDisassembler::Success;
1882}
1883
1884staticDecodeStatusDecodeFMem2(MCInst &Inst,unsignedInsn,uint64_t Address,
1885constMCDisassembler *Decoder) {
1886intOffset = SignExtend32<16>(Insn & 0xffff);
1887unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1888unsignedBase = fieldFromInstruction(Insn, 21, 5);
1889
1890 Reg =getReg(Decoder, Mips::COP2RegClassID, Reg);
1891Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1892
1893 Inst.addOperand(MCOperand::createReg(Reg));
1894 Inst.addOperand(MCOperand::createReg(Base));
1895 Inst.addOperand(MCOperand::createImm(Offset));
1896
1897returnMCDisassembler::Success;
1898}
1899
1900staticDecodeStatusDecodeFMem3(MCInst &Inst,unsignedInsn,uint64_t Address,
1901constMCDisassembler *Decoder) {
1902intOffset = SignExtend32<16>(Insn & 0xffff);
1903unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1904unsignedBase = fieldFromInstruction(Insn, 21, 5);
1905
1906 Reg =getReg(Decoder, Mips::COP3RegClassID, Reg);
1907Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1908
1909 Inst.addOperand(MCOperand::createReg(Reg));
1910 Inst.addOperand(MCOperand::createReg(Base));
1911 Inst.addOperand(MCOperand::createImm(Offset));
1912
1913returnMCDisassembler::Success;
1914}
1915
1916staticDecodeStatusDecodeFMemCop2R6(MCInst &Inst,unsignedInsn,
1917uint64_t Address,
1918constMCDisassembler *Decoder) {
1919intOffset = SignExtend32<11>(Insn & 0x07ff);
1920unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1921unsignedBase = fieldFromInstruction(Insn, 11, 5);
1922
1923 Reg =getReg(Decoder, Mips::COP2RegClassID, Reg);
1924Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1925
1926 Inst.addOperand(MCOperand::createReg(Reg));
1927 Inst.addOperand(MCOperand::createReg(Base));
1928 Inst.addOperand(MCOperand::createImm(Offset));
1929
1930returnMCDisassembler::Success;
1931}
1932
1933staticDecodeStatusDecodeFMemCop2MMR6(MCInst &Inst,unsignedInsn,
1934uint64_t Address,
1935constMCDisassembler *Decoder) {
1936intOffset = SignExtend32<11>(Insn & 0x07ff);
1937unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1938unsignedBase = fieldFromInstruction(Insn, 16, 5);
1939
1940 Reg =getReg(Decoder, Mips::COP2RegClassID, Reg);
1941Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1942
1943 Inst.addOperand(MCOperand::createReg(Reg));
1944 Inst.addOperand(MCOperand::createReg(Base));
1945 Inst.addOperand(MCOperand::createImm(Offset));
1946
1947returnMCDisassembler::Success;
1948}
1949
1950staticDecodeStatusDecodeSpecial3LlSc(MCInst &Inst,unsignedInsn,
1951uint64_t Address,
1952constMCDisassembler *Decoder) {
1953 int64_tOffset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1954unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1955unsignedBase = fieldFromInstruction(Insn, 21, 5);
1956
1957 Rt =getReg(Decoder, Mips::GPR32RegClassID, Rt);
1958Base =getReg(Decoder, Mips::GPR32RegClassID,Base);
1959
1960if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1961 Inst.addOperand(MCOperand::createReg(Rt));
1962 }
1963
1964 Inst.addOperand(MCOperand::createReg(Rt));
1965 Inst.addOperand(MCOperand::createReg(Base));
1966 Inst.addOperand(MCOperand::createImm(Offset));
1967
1968returnMCDisassembler::Success;
1969}
1970
1971staticDecodeStatusDecodeHWRegsRegisterClass(MCInst &Inst,unsigned RegNo,
1972uint64_t Address,
1973constMCDisassembler *Decoder) {
1974// Currently only hardware register 29 is supported.
1975if (RegNo != 29)
1976returnMCDisassembler::Fail;
1977 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1978returnMCDisassembler::Success;
1979}
1980
1981staticDecodeStatusDecodeAFGR64RegisterClass(MCInst &Inst,unsigned RegNo,
1982uint64_t Address,
1983constMCDisassembler *Decoder) {
1984if (RegNo > 30 || RegNo %2)
1985returnMCDisassembler::Fail;
1986
1987unsigned Reg =getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1988 Inst.addOperand(MCOperand::createReg(Reg));
1989returnMCDisassembler::Success;
1990}
1991
1992staticDecodeStatusDecodeACC64DSPRegisterClass(MCInst &Inst,unsigned RegNo,
1993uint64_t Address,
1994constMCDisassembler *Decoder) {
1995if (RegNo >= 4)
1996returnMCDisassembler::Fail;
1997
1998unsigned Reg =getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1999 Inst.addOperand(MCOperand::createReg(Reg));
2000returnMCDisassembler::Success;
2001}
2002
2003staticDecodeStatusDecodeHI32DSPRegisterClass(MCInst &Inst,unsigned RegNo,
2004uint64_t Address,
2005constMCDisassembler *Decoder) {
2006if (RegNo >= 4)
2007returnMCDisassembler::Fail;
2008
2009unsigned Reg =getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
2010 Inst.addOperand(MCOperand::createReg(Reg));
2011returnMCDisassembler::Success;
2012}
2013
2014staticDecodeStatusDecodeLO32DSPRegisterClass(MCInst &Inst,unsigned RegNo,
2015uint64_t Address,
2016constMCDisassembler *Decoder) {
2017if (RegNo >= 4)
2018returnMCDisassembler::Fail;
2019
2020unsigned Reg =getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
2021 Inst.addOperand(MCOperand::createReg(Reg));
2022returnMCDisassembler::Success;
2023}
2024
2025staticDecodeStatusDecodeMSA128BRegisterClass(MCInst &Inst,unsigned RegNo,
2026uint64_t Address,
2027constMCDisassembler *Decoder) {
2028if (RegNo > 31)
2029returnMCDisassembler::Fail;
2030
2031unsigned Reg =getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
2032 Inst.addOperand(MCOperand::createReg(Reg));
2033returnMCDisassembler::Success;
2034}
2035
2036staticDecodeStatusDecodeMSA128HRegisterClass(MCInst &Inst,unsigned RegNo,
2037uint64_t Address,
2038constMCDisassembler *Decoder) {
2039if (RegNo > 31)
2040returnMCDisassembler::Fail;
2041
2042unsigned Reg =getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
2043 Inst.addOperand(MCOperand::createReg(Reg));
2044returnMCDisassembler::Success;
2045}
2046
2047staticDecodeStatusDecodeMSA128WRegisterClass(MCInst &Inst,unsigned RegNo,
2048uint64_t Address,
2049constMCDisassembler *Decoder) {
2050if (RegNo > 31)
2051returnMCDisassembler::Fail;
2052
2053unsigned Reg =getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
2054 Inst.addOperand(MCOperand::createReg(Reg));
2055returnMCDisassembler::Success;
2056}
2057
2058staticDecodeStatusDecodeMSA128DRegisterClass(MCInst &Inst,unsigned RegNo,
2059uint64_t Address,
2060constMCDisassembler *Decoder) {
2061if (RegNo > 31)
2062returnMCDisassembler::Fail;
2063
2064unsigned Reg =getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
2065 Inst.addOperand(MCOperand::createReg(Reg));
2066returnMCDisassembler::Success;
2067}
2068
2069staticDecodeStatusDecodeMSACtrlRegisterClass(MCInst &Inst,unsigned RegNo,
2070uint64_t Address,
2071constMCDisassembler *Decoder) {
2072if (RegNo > 7)
2073returnMCDisassembler::Fail;
2074
2075unsigned Reg =getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
2076 Inst.addOperand(MCOperand::createReg(Reg));
2077returnMCDisassembler::Success;
2078}
2079
2080staticDecodeStatusDecodeCOP0RegisterClass(MCInst &Inst,unsigned RegNo,
2081uint64_t Address,
2082constMCDisassembler *Decoder) {
2083if (RegNo > 31)
2084returnMCDisassembler::Fail;
2085
2086unsigned Reg =getReg(Decoder, Mips::COP0RegClassID, RegNo);
2087 Inst.addOperand(MCOperand::createReg(Reg));
2088returnMCDisassembler::Success;
2089}
2090
2091staticDecodeStatusDecodeCOP2RegisterClass(MCInst &Inst,unsigned RegNo,
2092uint64_t Address,
2093constMCDisassembler *Decoder) {
2094if (RegNo > 31)
2095returnMCDisassembler::Fail;
2096
2097unsigned Reg =getReg(Decoder, Mips::COP2RegClassID, RegNo);
2098 Inst.addOperand(MCOperand::createReg(Reg));
2099returnMCDisassembler::Success;
2100}
2101
2102staticDecodeStatusDecodeBranchTarget(MCInst &Inst,unsignedOffset,
2103uint64_t Address,
2104constMCDisassembler *Decoder) {
2105 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
2106 Inst.addOperand(MCOperand::createImm(BranchOffset));
2107returnMCDisassembler::Success;
2108}
2109
2110staticDecodeStatusDecodeBranchTarget1SImm16(MCInst &Inst,unsignedOffset,
2111uint64_t Address,
2112constMCDisassembler *Decoder) {
2113 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
2114 Inst.addOperand(MCOperand::createImm(BranchOffset));
2115returnMCDisassembler::Success;
2116}
2117
2118staticDecodeStatusDecodeJumpTarget(MCInst &Inst,unsignedInsn,
2119uint64_t Address,
2120constMCDisassembler *Decoder) {
2121unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2122 Inst.addOperand(MCOperand::createImm(JumpOffset));
2123returnMCDisassembler::Success;
2124}
2125
2126staticDecodeStatusDecodeBranchTarget21(MCInst &Inst,unsignedOffset,
2127uint64_t Address,
2128constMCDisassembler *Decoder) {
2129 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2130
2131 Inst.addOperand(MCOperand::createImm(BranchOffset));
2132returnMCDisassembler::Success;
2133}
2134
2135staticDecodeStatusDecodeBranchTarget21MM(MCInst &Inst,unsignedOffset,
2136uint64_t Address,
2137constMCDisassembler *Decoder) {
2138 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2139
2140 Inst.addOperand(MCOperand::createImm(BranchOffset));
2141returnMCDisassembler::Success;
2142}
2143
2144staticDecodeStatusDecodeBranchTarget26(MCInst &Inst,unsignedOffset,
2145uint64_t Address,
2146constMCDisassembler *Decoder) {
2147 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
2148
2149 Inst.addOperand(MCOperand::createImm(BranchOffset));
2150returnMCDisassembler::Success;
2151}
2152
2153staticDecodeStatusDecodeBranchTarget7MM(MCInst &Inst,unsignedOffset,
2154uint64_t Address,
2155constMCDisassembler *Decoder) {
2156 int32_t BranchOffset = SignExtend32<8>(Offset << 1);
2157 Inst.addOperand(MCOperand::createImm(BranchOffset));
2158returnMCDisassembler::Success;
2159}
2160
2161staticDecodeStatusDecodeBranchTarget10MM(MCInst &Inst,unsignedOffset,
2162uint64_t Address,
2163constMCDisassembler *Decoder) {
2164 int32_t BranchOffset = SignExtend32<11>(Offset << 1);
2165 Inst.addOperand(MCOperand::createImm(BranchOffset));
2166returnMCDisassembler::Success;
2167}
2168
2169staticDecodeStatusDecodeBranchTargetMM(MCInst &Inst,unsignedOffset,
2170uint64_t Address,
2171constMCDisassembler *Decoder) {
2172 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
2173 Inst.addOperand(MCOperand::createImm(BranchOffset));
2174returnMCDisassembler::Success;
2175}
2176
2177staticDecodeStatusDecodeBranchTarget26MM(MCInst &Inst,unsignedOffset,
2178uint64_t Address,
2179constMCDisassembler *Decoder) {
2180 int32_t BranchOffset = SignExtend32<27>(Offset << 1);
2181
2182 Inst.addOperand(MCOperand::createImm(BranchOffset));
2183returnMCDisassembler::Success;
2184}
2185
2186staticDecodeStatusDecodeJumpTargetMM(MCInst &Inst,unsignedInsn,
2187uint64_t Address,
2188constMCDisassembler *Decoder) {
2189unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
2190 Inst.addOperand(MCOperand::createImm(JumpOffset));
2191returnMCDisassembler::Success;
2192}
2193
2194staticDecodeStatusDecodeJumpTargetXMM(MCInst &Inst,unsignedInsn,
2195uint64_t Address,
2196constMCDisassembler *Decoder) {
2197unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2198 Inst.addOperand(MCOperand::createImm(JumpOffset));
2199returnMCDisassembler::Success;
2200}
2201
2202staticDecodeStatusDecodeAddiur2Simm7(MCInst &Inst,unsignedValue,
2203uint64_t Address,
2204constMCDisassembler *Decoder) {
2205if (Value == 0)
2206 Inst.addOperand(MCOperand::createImm(1));
2207elseif (Value == 0x7)
2208 Inst.addOperand(MCOperand::createImm(-1));
2209else
2210 Inst.addOperand(MCOperand::createImm(Value << 2));
2211returnMCDisassembler::Success;
2212}
2213
2214staticDecodeStatusDecodeLi16Imm(MCInst &Inst,unsignedValue,
2215uint64_t Address,
2216constMCDisassembler *Decoder) {
2217if (Value == 0x7F)
2218 Inst.addOperand(MCOperand::createImm(-1));
2219else
2220 Inst.addOperand(MCOperand::createImm(Value));
2221returnMCDisassembler::Success;
2222}
2223
2224staticDecodeStatusDecodePOOL16BEncodedField(MCInst &Inst,unsignedValue,
2225uint64_t Address,
2226constMCDisassembler *Decoder) {
2227 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 :Value));
2228returnMCDisassembler::Success;
2229}
2230
2231template <unsigned Bits,int Offset,int Scale>
2232staticDecodeStatus
2233DecodeUImmWithOffsetAndScale(MCInst &Inst,unsignedValue,uint64_t Address,
2234constMCDisassembler *Decoder) {
2235Value &= ((1 << Bits) - 1);
2236Value *= Scale;
2237 Inst.addOperand(MCOperand::createImm(Value +Offset));
2238returnMCDisassembler::Success;
2239}
2240
2241template <unsigned Bits,int Offset,int ScaleBy>
2242staticDecodeStatus
2243DecodeSImmWithOffsetAndScale(MCInst &Inst,unsignedValue,uint64_t Address,
2244constMCDisassembler *Decoder) {
2245 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
2246 Inst.addOperand(MCOperand::createImm(Imm +Offset));
2247returnMCDisassembler::Success;
2248}
2249
2250staticDecodeStatusDecodeInsSize(MCInst &Inst,unsignedInsn,uint64_t Address,
2251constMCDisassembler *Decoder) {
2252// First we need to grab the pos(lsb) from MCInst.
2253// This function only handles the 32 bit variants of ins, as dins
2254// variants are handled differently.
2255int Pos = Inst.getOperand(2).getImm();
2256intSize = (int)Insn - Pos + 1;
2257 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2258returnMCDisassembler::Success;
2259}
2260
2261staticDecodeStatusDecodeSimm19Lsl2(MCInst &Inst,unsignedInsn,
2262uint64_t Address,
2263constMCDisassembler *Decoder) {
2264 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2265returnMCDisassembler::Success;
2266}
2267
2268staticDecodeStatusDecodeSimm18Lsl3(MCInst &Inst,unsignedInsn,
2269uint64_t Address,
2270constMCDisassembler *Decoder) {
2271 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2272returnMCDisassembler::Success;
2273}
2274
2275staticDecodeStatusDecodeSimm9SP(MCInst &Inst,unsignedInsn,uint64_t Address,
2276constMCDisassembler *Decoder) {
2277 int32_t DecodedValue;
2278switch (Insn) {
2279case 0: DecodedValue = 256;break;
2280case 1: DecodedValue = 257;break;
2281case 510: DecodedValue = -258;break;
2282case 511: DecodedValue = -257;break;
2283default: DecodedValue = SignExtend32<9>(Insn);break;
2284 }
2285 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
2286returnMCDisassembler::Success;
2287}
2288
2289staticDecodeStatusDecodeANDI16Imm(MCInst &Inst,unsignedInsn,
2290uint64_t Address,
2291constMCDisassembler *Decoder) {
2292// Insn must be >= 0, since it is unsigned that condition is always true.
2293assert(Insn < 16);
2294 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
2295 255, 32768, 65535};
2296 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
2297returnMCDisassembler::Success;
2298}
2299
2300staticDecodeStatusDecodeRegListOperand(MCInst &Inst,unsignedInsn,
2301uint64_t Address,
2302constMCDisassembler *Decoder) {
2303unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2304 Mips::S6, Mips::S7, Mips::FP};
2305unsigned RegNum;
2306
2307unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2308
2309// Empty register lists are not allowed.
2310if (RegLst == 0)
2311returnMCDisassembler::Fail;
2312
2313 RegNum = RegLst & 0xf;
2314
2315// RegLst values 10-15, and 26-31 are reserved.
2316if (RegNum > 9)
2317returnMCDisassembler::Fail;
2318
2319for (unsigned i = 0; i < RegNum; i++)
2320 Inst.addOperand(MCOperand::createReg(Regs[i]));
2321
2322if (RegLst & 0x10)
2323 Inst.addOperand(MCOperand::createReg(Mips::RA));
2324
2325returnMCDisassembler::Success;
2326}
2327
2328staticDecodeStatusDecodeRegListOperand16(MCInst &Inst,unsignedInsn,
2329uint64_t Address,
2330constMCDisassembler *Decoder) {
2331unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2332unsigned RegLst;
2333switch(Inst.getOpcode()) {
2334default:
2335 RegLst = fieldFromInstruction(Insn, 4, 2);
2336break;
2337case Mips::LWM16_MMR6:
2338case Mips::SWM16_MMR6:
2339 RegLst = fieldFromInstruction(Insn, 8, 2);
2340break;
2341 }
2342unsigned RegNum = RegLst & 0x3;
2343
2344for (unsigned i = 0; i <= RegNum; i++)
2345 Inst.addOperand(MCOperand::createReg(Regs[i]));
2346
2347 Inst.addOperand(MCOperand::createReg(Mips::RA));
2348
2349returnMCDisassembler::Success;
2350}
2351
2352staticDecodeStatusDecodeMovePOperands(MCInst &Inst,unsignedInsn,
2353uint64_t Address,
2354constMCDisassembler *Decoder) {
2355unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2356if (DecodeMovePRegPair(Inst, RegPair,Address, Decoder) ==
2357MCDisassembler::Fail)
2358returnMCDisassembler::Fail;
2359
2360unsigned RegRs;
2361if (static_cast<constMipsDisassembler*>(Decoder)->hasMips32r6())
2362 RegRs = fieldFromInstruction(Insn, 0, 2) |
2363 (fieldFromInstruction(Insn, 3, 1) << 2);
2364else
2365 RegRs = fieldFromInstruction(Insn, 1, 3);
2366if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs,Address, Decoder) ==
2367MCDisassembler::Fail)
2368returnMCDisassembler::Fail;
2369
2370unsigned RegRt = fieldFromInstruction(Insn, 4, 3);
2371if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt,Address, Decoder) ==
2372MCDisassembler::Fail)
2373returnMCDisassembler::Fail;
2374
2375returnMCDisassembler::Success;
2376}
2377
2378staticDecodeStatusDecodeMovePRegPair(MCInst &Inst,unsigned RegPair,
2379uint64_t Address,
2380constMCDisassembler *Decoder) {
2381switch (RegPair) {
2382default:
2383returnMCDisassembler::Fail;
2384case 0:
2385 Inst.addOperand(MCOperand::createReg(Mips::A1));
2386 Inst.addOperand(MCOperand::createReg(Mips::A2));
2387break;
2388case 1:
2389 Inst.addOperand(MCOperand::createReg(Mips::A1));
2390 Inst.addOperand(MCOperand::createReg(Mips::A3));
2391break;
2392case 2:
2393 Inst.addOperand(MCOperand::createReg(Mips::A2));
2394 Inst.addOperand(MCOperand::createReg(Mips::A3));
2395break;
2396case 3:
2397 Inst.addOperand(MCOperand::createReg(Mips::A0));
2398 Inst.addOperand(MCOperand::createReg(Mips::S5));
2399break;
2400case 4:
2401 Inst.addOperand(MCOperand::createReg(Mips::A0));
2402 Inst.addOperand(MCOperand::createReg(Mips::S6));
2403break;
2404case 5:
2405 Inst.addOperand(MCOperand::createReg(Mips::A0));
2406 Inst.addOperand(MCOperand::createReg(Mips::A1));
2407break;
2408case 6:
2409 Inst.addOperand(MCOperand::createReg(Mips::A0));
2410 Inst.addOperand(MCOperand::createReg(Mips::A2));
2411break;
2412case 7:
2413 Inst.addOperand(MCOperand::createReg(Mips::A0));
2414 Inst.addOperand(MCOperand::createReg(Mips::A3));
2415break;
2416 }
2417
2418returnMCDisassembler::Success;
2419}
2420
2421staticDecodeStatusDecodeSimm23Lsl2(MCInst &Inst,unsignedInsn,
2422uint64_t Address,
2423constMCDisassembler *Decoder) {
2424 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2425returnMCDisassembler::Success;
2426}
2427
2428template <typename InsnType>
2429staticDecodeStatusDecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
2430uint64_t Address,
2431constMCDisassembler *Decoder) {
2432// We have:
2433// 0b000111 ttttt sssss iiiiiiiiiiiiiiii
2434// Invalid if rt == 0
2435// BGTZALC_MMR6 if rs == 0 && rt != 0
2436// BLTZALC_MMR6 if rs != 0 && rs == rt
2437// BLTUC_MMR6 if rs != 0 && rs != rt
2438
2439 InsnType Rt = fieldFromInstruction(insn, 21, 5);
2440 InsnType Rs = fieldFromInstruction(insn, 16, 5);
2441 InsnType Imm = 0;
2442bool HasRs =false;
2443bool HasRt =false;
2444
2445if (Rt == 0)
2446returnMCDisassembler::Fail;
2447elseif (Rs == 0) {
2448MI.setOpcode(Mips::BGTZALC_MMR6);
2449 HasRt =true;
2450 Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2451 }
2452elseif (Rs == Rt) {
2453MI.setOpcode(Mips::BLTZALC_MMR6);
2454 HasRs =true;
2455 Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2456 }
2457else {
2458MI.setOpcode(Mips::BLTUC_MMR6);
2459 HasRs =true;
2460 HasRt =true;
2461 Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2462 }
2463
2464if (HasRs)
2465MI.addOperand(
2466MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2467
2468if (HasRt)
2469MI.addOperand(
2470MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2471
2472MI.addOperand(MCOperand::createImm(Imm));
2473
2474returnMCDisassembler::Success;
2475}
2476
2477template <typename InsnType>
2478staticDecodeStatusDecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
2479uint64_t Address,
2480constMCDisassembler *Decoder) {
2481// We have:
2482// 0b000110 ttttt sssss iiiiiiiiiiiiiiii
2483// Invalid if rt == 0
2484// BLEZALC_MMR6 if rs == 0 && rt != 0
2485// BGEZALC_MMR6 if rs == rt && rt != 0
2486// BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
2487
2488 InsnType Rt = fieldFromInstruction(insn, 21, 5);
2489 InsnType Rs = fieldFromInstruction(insn, 16, 5);
2490 InsnType Imm = 0;
2491bool HasRs =false;
2492
2493if (Rt == 0)
2494returnMCDisassembler::Fail;
2495elseif (Rs == 0) {
2496MI.setOpcode(Mips::BLEZALC_MMR6);
2497 Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2498 }
2499elseif (Rs == Rt) {
2500MI.setOpcode(Mips::BGEZALC_MMR6);
2501 Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2502 }
2503else {
2504 HasRs =true;
2505MI.setOpcode(Mips::BGEUC_MMR6);
2506 Imm =SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2507 }
2508
2509if (HasRs)
2510MI.addOperand(
2511MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2512MI.addOperand(
2513MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2514
2515MI.addOperand(MCOperand::createImm(Imm));
2516
2517returnMCDisassembler::Success;
2518}
2519
2520// This instruction does not have a working decoder, and needs to be
2521// fixed. This "fixme" function was introduced to keep the backend compiling,
2522// while making changes to tablegen code.
2523staticDecodeStatusDecodeFIXMEInstruction(MCInst &Inst,unsignedInsn,
2524uint64_t Address,
2525constMCDisassembler *Decoder) {
2526returnMCDisassembler::Fail;
2527}
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition:AArch64MIPeepholeOpt.cpp:167
ArrayRef.h
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Compiler.h
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition:Compiler.h:128
Debug.h
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition:Debug.h:106
Size
uint64_t Size
Definition:ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition:IRTranslator.cpp:112
MCContext.h
MCDecoderOps.h
MCDisassembler.h
MCInst.h
MCRegisterInfo.h
MCSubtargetInfo.h
MathExtras.h
DecodePOOL16BEncodedField
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2224
DecodeFMemCop2MMR6
static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1933
DecodeSimm19Lsl2
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2261
DecodeMemEVA
static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1481
DecodeBgtzlGroupBranch
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:870
DecodeRegListOperand
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2300
readInstruction32
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness.
Definition:MipsDisassembler.cpp:1126
DecodeBranchTarget21
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2126
DecodeJumpTargetXMM
static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2194
DecodeFGR32RegisterClass
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1419
DecodeCCRRegisterClass
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1430
DecodeCOP2RegisterClass
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2091
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition:MipsDisassembler.cpp:520
DecodeFCCRegisterClass
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1440
DecodeCacheOpMM
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1532
readInstruction16
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness.
Definition:MipsDisassembler.cpp:1106
DecodeGPRMM16RegisterClass
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1353
DecodeSImmWithOffsetAndScale
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2243
DecodeSimm23Lsl2
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2421
DecodeGPRMM16MovePRegisterClass
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1374
DecodeBranchTarget1SImm16
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2110
DecodeMemMMImm9
static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1778
DecodeMovePOperands
static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2352
DecodeCRC
static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1091
DecodePOP75GroupBranchMMR6
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:788
DecodeDINS
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1049
DecodeMSA128Mem
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1620
DecodePrefeOpMM
static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1548
DecodeCPU16RegsRegisterClass
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1337
DecodeMSA128WRegisterClass
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2047
DecodeBranchTarget26
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2144
DecodeFMem
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1849
DecodeCacheOp
static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1517
DecodeSyncI_MM
static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1593
DecodeLoadByte15
static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1500
DecodeSimm9SP
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2275
DecodeFMem2
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1884
DecodeUImmWithOffsetAndScale
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2233
DecodeMemMMImm12
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1798
DecodeDEXT
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1007
DecodeGPRMM16ZeroRegisterClass
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1364
DecodePtrRegisterClass
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1393
DecodeLi16Imm
static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2214
createMipselDisassembler
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition:MipsDisassembler.cpp:499
DecodeSimm18Lsl3
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2268
DecodeFMem3
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1900
DecodeBlezlGroupBranch
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:827
DecodeCOP0RegisterClass
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2080
DecodeBranchTarget
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2102
DecodeMemMMReglistImm4Lsl2
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1754
DecodeBgtzGroupBranch
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:914
DecodeBranchTargetMM
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2169
DecodePOP35GroupBranchMMR6
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:642
DecodeFIXMEInstruction
static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2523
DecodeBranchTarget10MM
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2161
DecodeANDI16Imm
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2289
DecodeMSA128DRegisterClass
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2058
DecodeMemMMImm4
static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1667
createMipsDisassembler
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition:MipsDisassembler.cpp:492
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1383
DecodeMSA128BRegisterClass
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2025
DecodeHWRegsRegisterClass
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1971
DecodeDaddiGroupBranch
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:676
DecodeMovePRegPair
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2378
DecodeDAHIDATIMMR6
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:574
DecodeBranchTarget21MM
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2135
DecodeBranchTarget26MM
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2177
DecodeAFGR64RegisterClass
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1981
DecodeDAHIDATI
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:589
DecodeLO32DSPRegisterClass
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2014
DecodeSpecial3LlSc
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1950
DecodeHI32DSPRegisterClass
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2003
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition:MipsDisassembler.cpp:35
DecodeSynciR6
static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1607
DecodeUImmWithOffset
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:351
DecodeRegListOperand16
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2328
DecodeAddiGroupBranch
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:603
DecodeMemMMSPImm5Lsl2
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1724
DecodeAddiur2Simm7
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2202
DecodeMSACtrlRegisterClass
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2069
DecodeMSA128HRegisterClass
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2036
DecodeFMemMMR2
static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1865
DecodeCacheeOp_CacheOpR6
static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1564
DecodeMemMMImm16
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1832
DecodeBranchTarget7MM
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2153
DecodeFGR64RegisterClass
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1408
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1342
DecodeBlezGroupBranchMMR6
static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2478
DecodeJumpTargetMM
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2186
DecodePOP37GroupBranchMMR6
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:715
DecodeSyncI
static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1580
DecodeJumpTarget
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2118
DecodeACC64DSPRegisterClass
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1992
DecodeFMemCop2R6
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1916
DecodeBgtzGroupBranchMMR6
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2429
DecodePOP65GroupBranchMMR6
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:749
DecodeDSPRRegisterClass
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1402
DecodeInsSize
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:2250
LLVMInitializeMipsDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler()
Definition:MipsDisassembler.cpp:506
DecodeBlezGroupBranch
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:963
DecodeMem
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1461
DecodeFGRCCRegisterClass
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1450
DecodeINSVE_DF
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
INSVE_[BHWD] have an implicit operand that the generated decoder doesn't handle.
Definition:MipsDisassembler.cpp:526
DecodeMemMMGPImm7Lsl2
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:MipsDisassembler.cpp:1739
MipsMCTargetDesc.h
MipsTargetInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Address
@ Address
Definition:SPIRVEmitNonSemanticDI.cpp:68
TargetRegistry.h
T
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition:ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition:ArrayRef.h:168
llvm::MCContext
Context object for machine code objects.
Definition:MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition:MCDisassembler.h:84
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition:MCDisassembler.h:108
llvm::MCDisassembler::Fail
@ Fail
Definition:MCDisassembler.h:109
llvm::MCDisassembler::Success
@ Success
Definition:MCDisassembler.h:111
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition:MCInst.h:185
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition:MCInst.h:199
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition:MCInst.h:211
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition:MCInst.h:207
llvm::MCOperand::getImm
int64_t getImm() const
Definition:MCInst.h:81
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition:MCInst.h:135
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition:MCInst.h:142
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition:MCRegisterInfo.h:149
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition:MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition:MCSubtargetInfo.h:121
llvm::Target
Target - Wrapper for Target specific information.
Definition:TargetRegistry.h:144
llvm::Value
LLVM Value Representation.
Definition:Value.h:74
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition:raw_ostream.h:52
uint32_t
uint64_t
unsigned
ErrorHandling.h
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition:ErrorHandling.h:143
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::sampleprof::Base
@ Base
Definition:Discriminator.h:58
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:AddressRanges.h:18
llvm::Offset
@ Offset
Definition:DWP.cpp:480
llvm::getTheMips64Target
Target & getTheMips64Target()
Definition:MipsTargetInfo.cpp:21
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition:Debug.cpp:163
llvm::getTheMips64elTarget
Target & getTheMips64elTarget()
Definition:MipsTargetInfo.cpp:25
llvm::getTheMipselTarget
Target & getTheMipselTarget()
Definition:MipsTargetInfo.cpp:17
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition:MathExtras.h:582
llvm::getTheMipsTarget
Target & getTheMipsTarget()
Definition:MipsTargetInfo.cpp:13
raw_ostream.h
RegInfo
Definition:AMDGPUAsmParser.cpp:2770
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition:TargetRegistry.h:878
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