1//===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7//===----------------------------------------------------------------------===// 9// This file contains the declaration of the MachineOperand class. 11//===----------------------------------------------------------------------===// 13#ifndef LLVM_CODEGEN_MACHINEOPERAND_H 14#define LLVM_CODEGEN_MACHINEOPERAND_H 29classMachineBasicBlock;
31classMachineRegisterInfo;
34classModuleSlotTracker;
35classTargetIntrinsicInfo;
36classTargetRegisterInfo;
41/// MachineOperand class - Representation of each machine instruction operand. 43/// This class isn't a POD type because it has a private constructor, but its 44/// destructor must be trivial. Functions like MachineInstr::addOperand(), 45/// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on 46/// not having to call the MachineOperand destructor. 76 /// OpKind - Specify what kind of operand this is. This discriminates the 80 /// Subregister number for MO_Register. A value of 0 indicates the 81 /// MO_Register has no subReg. 83 /// For all other kinds of operands, this field holds target-specific flags. 84unsigned SubReg_TargetFlags : 12;
86 /// TiedTo - Non-zero when this register operand is tied to another register 87 /// operand. The encoding of this field is described in the block comment 88 /// before MachineInstr::tieOperands(). 91 /// IsDef - True if this is a def, false if this is a use of the register. 92 /// This is only valid on register operands. 96 /// IsImp - True if this is an implicit def or use, false if it is explicit. 97 /// This is only valid on register opderands. 102 /// For uses: IsKill - Conservatively indicates the last use of a register 103 /// on this path through the function. A register operand with true value of 104 /// this flag must be the last use of the register, a register operand with 105 /// false value may or may not be the last use of the register. After regalloc 106 /// we can use recomputeLivenessFlags to get precise kill flags. 107 /// For defs: IsDead - True if this register is never used by a subsequent 109 /// This is only valid on register operands. 110unsigned IsDeadOrKill : 1;
112 /// See isRenamable(). 113unsigned IsRenamable : 1;
115 /// IsUndef - True if this register operand reads an "undef" value, i.e. the 116 /// read value doesn't matter. This flag can be set on both use and def 117 /// operands. On a sub-register def operand, it refers to the part of the 118 /// register that isn't written. On a full-register def operand, it is a 119 /// noop. See readsReg(). 121 /// This is only valid on registers. 123 /// Note that an instruction may have multiple <undef> operands referring to 124 /// the same register. In that case, the instruction may depend on those 125 /// operands reading the same dont-care value. For example: 127 /// %1 = XOR undef %2, undef %2 129 /// Any register can be used for %2, and its value doesn't matter, but 130 /// the two operands must be the same register. 134 /// IsInternalRead - True if this operand reads a value that was defined 135 /// inside the same instruction or bundle. This flag can be set on both use 136 /// and def operands. On a sub-register def operand, it refers to the part 137 /// of the register that isn't written. On a full-register def operand, it 140 /// When this flag is set, the instruction bundle must contain at least one 141 /// other def of the register. If multiple instructions in the bundle define 142 /// the register, the meaning is target-defined. 143unsigned IsInternalRead : 1;
145 /// IsEarlyClobber - True if this MO_Register 'def' operand is written to 146 /// by the MachineInstr before all input registers are read. This is used to 147 /// model the GCC inline asm '&' constraint modifier. 148unsigned IsEarlyClobber : 1;
150 /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo, 151 /// not a real instruction. Such uses should be ignored during codegen. 154 /// SmallContents - This really should be part of the Contents union, but 155 /// lives out here so we can get a better packed struct. 156 /// MO_Register: Register number. 157 /// OffsetedInfo: Low bits of offset. 160unsignedOffsetLo;
// Matches Contents.OffsetedInfo.OffsetHi. 163 /// ParentMI - This is the instruction that this operand is embedded into. 164 /// This is valid for all operand types, when the operand is in an instr. 167 /// Contents union - This contains the payload for the various operand types. 170 MachineBasicBlock *
MBB;
// For MO_MachineBasicBlock. 171const ConstantFP *CFP;
// For MO_FPImmediate. 172const ConstantInt *CI;
// For MO_CImmediate. Integers > 64bit. 173 int64_t ImmVal;
// For MO_Immediate. 174constuint32_t *RegMask;
// For MO_RegisterMask and MO_RegisterLiveOut. 175const MDNode *MD;
// For MO_Metadata. 176 MCSymbol *
Sym;
// For MO_MCSymbol. 177unsigned CFIIndex;
// For MO_CFI. 179unsigned Pred;
// For MO_Predicate 180 ArrayRef<int> ShuffleMask;
// For MO_ShuffleMask 182struct{
// For MO_Register. 183// Register number is in SmallContents.RegNo. 184 MachineOperand *Prev;
// Access list for register. See MRI. 185 MachineOperand *Next;
188struct{
// For MO_DbgInstrRef. 193 /// OffsetedInfo - This struct contains the offset and an object identifier. 194 /// this represent the object as with an optional offset from it. 197intIndex;
// For MO_*Index - The index itself. 198constchar *
SymbolName;
// For MO_ExternalSymbol. 199const GlobalValue *GV;
// For MO_GlobalAddress. 202// Low bits of offset are in SmallContents.OffsetLo. 203int OffsetHi;
// An offset from the object, high 32 bits. 208 : OpKind(
K), SubReg_TargetFlags(0) {
209// Assert that the layout is what we expect. It's easy to grow this object. 210static_assert(
alignof(MachineOperand) <=
alignof(int64_t),
211"MachineOperand shouldn't be more than 8 byte aligned");
212static_assert(
sizeof(Contents) <= 2 *
sizeof(
void *),
213"Contents should be at most two pointers");
214static_assert(
sizeof(MachineOperand) <=
217"MachineOperand too big. Should be Kind, SmallContents, " 218"ParentMI, and Contents");
222 /// getType - Returns the MachineOperandType for this operand. 227returnisReg() ? 0 : SubReg_TargetFlags;
230assert(!
isReg() &&
"Register operands can't have target flags");
231 SubReg_TargetFlags =
F;
232assert(SubReg_TargetFlags ==
F &&
"Target flags out of range");
235assert(!
isReg() &&
"Register operands can't have target flags");
236 SubReg_TargetFlags |=
F;
237assert((SubReg_TargetFlags &
F) &&
"Target flags out of range");
241 /// getParent - Return the instruction that this operand belongs to. 246 /// clearParent - Reset the parent pointer. 248 /// The MachineOperand copy constructor also copies ParentMI, expecting the 249 /// original to be deleted. If a MachineOperand is ever stored outside a 250 /// MachineInstr, the parent pointer must be cleared. 252 /// Never call clearParent() on an operand in a MachineInstr. 256 /// Returns the index of this operand in the instruction that it belongs to. 259 /// Print a subreg index operand. 260 /// MO_Immediate operands can also be subreg idices. If it's the case, the 261 /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be 262 /// called to check this. 266 /// Print operand target flags. 269 /// Print a MCSymbol as an operand. 272 /// Print a stack object reference. 276 /// Print the offset with explicit +/- signs. 279 /// Print an IRSlotNumber. 282 /// Print the MachineOperand to \p os. 283 /// Providing a valid \p TRI and \p IntrinsicInfo results in a more 284 /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the 285 /// function will try to pick it up from the parent. 289 /// More complex way of printing a MachineOperand. 290 /// \param TypeToPrint specifies the generic type to be printed on uses and 291 /// defs. It can be determined using MachineInstr::getTypeToPrint. 292 /// \param OpIdx - specifies the index of the operand in machine instruction. 293 /// This will be used by target dependent MIR formatter. Could be std::nullopt 294 /// if the index is unknown, e.g. called by dump(). 295 /// \param PrintDef - whether we want to print `def` on an operand which 296 /// isDef. Sometimes, if the operand is printed before '=', we don't print 298 /// \param IsStandalone - whether we want a verbose output of the MO. This 299 /// prints extra information that can be easily inferred when printing the 300 /// whole function, but not when printing only a fragment of it. 301 /// \param ShouldPrintRegisterTies - whether we want to print register ties. 302 /// Sometimes they are easily determined by the instruction's descriptor 303 /// (MachineInstr::hasComplexRegiterTies can determine if it's needed). 304 /// \param TiedOperandIdx - if we need to print register ties this needs to 305 /// provide the index of the tied register. If not, it will be ignored. 306 /// \param TRI - provide more target-specific information to the printer. 307 /// Unlike the previous function, this one will not try and get the 308 /// information from it's parent. 309 /// \param IntrinsicInfo - same as \p TRI. 311 std::optional<unsigned> OpIdx,
bool PrintDef,
bool IsStandalone,
312bool ShouldPrintRegisterTies,
unsigned TiedOperandIdx,
316 /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level 317 /// type to be printed the same way the full version of print(...) does it. 324//===--------------------------------------------------------------------===// 325// Accessors that tell you what kind of MachineOperand you're looking at. 326//===--------------------------------------------------------------------===// 328 /// isReg - Tests if this is a MO_Register operand. 330 /// isImm - Tests if this is a MO_Immediate operand. 332 /// isCImm - Test if this is a MO_CImmediate operand. 334 /// isFPImm - Tests if this is a MO_FPImmediate operand. 336 /// isMBB - Tests if this is a MO_MachineBasicBlock operand. 338 /// isFI - Tests if this is a MO_FrameIndex operand. 340 /// isCPI - Tests if this is a MO_ConstantPoolIndex operand. 342 /// isTargetIndex - Tests if this is a MO_TargetIndex operand. 344 /// isJTI - Tests if this is a MO_JumpTableIndex operand. 346 /// isGlobal - Tests if this is a MO_GlobalAddress operand. 348 /// isSymbol - Tests if this is a MO_ExternalSymbol operand. 350 /// isBlockAddress - Tests if this is a MO_BlockAddress operand. 352 /// isRegMask - Tests if this is a MO_RegisterMask operand. 354 /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand. 356 /// isMetadata - Tests if this is a MO_Metadata operand. 364//===--------------------------------------------------------------------===// 365// Accessors for Register Operands 366//===--------------------------------------------------------------------===// 368 /// getReg - Returns the register number. 370assert(
isReg() &&
"This is not a register operand!");
376return SubReg_TargetFlags;
396return IsDeadOrKill & IsDef;
401return IsDeadOrKill & !IsDef;
409 /// isRenamable - Returns true if this register may be renamed, i.e. it does 410 /// not generate a value that is somehow read in a way that is not represented 411 /// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only 412 /// valid on physical register operands. Virtual registers are assumed to 413 /// always be renamable regardless of the value of this field. 415 /// Operands that are renamable can freely be changed to any other register 416 /// that is a member of the register class returned by 417 /// MI->getRegClassConstraint(). 419 /// isRenamable can return false for several different reasons: 421 /// - ABI constraints (since liveness is not always precisely modeled). We 422 /// conservatively handle these cases by setting all physical register 423 /// operands that didn’t start out as virtual regs to not be renamable. 424 /// Also any physical register operands created after register allocation or 425 /// whose register is changed after register allocation will not be 426 /// renamable. This state is tracked in the MachineOperand::IsRenamable 429 /// - Opcode/target constraints: for opcodes that have complex register class 430 /// requirements (e.g. that depend on other operands/instructions), we set 431 /// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode 432 /// description. Operands belonging to instructions with opcodes that are 433 /// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from 434 /// isRenamable(). Additionally, the AllowRegisterRenaming target property 435 /// prevents any operands from being marked renamable for targets that don't 436 /// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq 442return IsInternalRead;
447return IsEarlyClobber;
460 /// readsReg - Returns true if this operand reads the previous value of its 461 /// register. A use operand with the <undef> flag set doesn't read its 462 /// register. A sub-register def implicitly reads the other parts of the 463 /// register being redefined unless the <undef> flag is set. 465 /// This refers to reading the register value from before the current 466 /// instruction or bundle. Internal bundle reads are not included. 472 /// Return true if this operand can validly be appended to an arbitrary 473 /// operand list. i.e. this behaves like an implicit operand. 482//===--------------------------------------------------------------------===// 483// Mutators for Register Operands 484//===--------------------------------------------------------------------===// 486 /// Change the register this operand corresponds to. 492 SubReg_TargetFlags = subReg;
493assert(SubReg_TargetFlags == subReg &&
"SubReg out of range");
496 /// substVirtReg - Substitute the current register with the virtual 497 /// subregister Reg:SubReg. Take any existing SubReg index into account, 498 /// using TargetRegisterInfo to compose the subreg indices if necessary. 499 /// Reg must be a virtual register, SubIdx can be 0. 503 /// substPhysReg - Substitute the current register with the physical register 504 /// Reg, taking any existing SubReg into account. For instance, 505 /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al. 511 /// Change a def to a use, or a use to a def. 520assert(
isReg() && !IsDef &&
"Wrong MachineOperand mutator");
521assert((!Val || !
isDebug()) &&
"Marking a debug operation as kill");
526assert(
isReg() && IsDef &&
"Wrong MachineOperand mutator");
539 IsInternalRead = Val;
543assert(
isReg() && IsDef &&
"Wrong MachineOperand mutator");
544 IsEarlyClobber = Val;
548assert(
isReg() && !IsDef &&
"Wrong MachineOperand mutator");
552//===--------------------------------------------------------------------===// 553// Accessors for various operand types. 554//===--------------------------------------------------------------------===// 558return Contents.ImmVal;
578"Wrong MachineOperand accessor");
579return Contents.OffsetedInfo.Val.Index;
584return Contents.OffsetedInfo.Val.GV;
589return Contents.OffsetedInfo.Val.BA;
599return Contents.InstrRef.InstrIdx;
604return Contents.InstrRef.OpIdx;
609return Contents.CFIIndex;
614return Contents.IntrinsicID;
624return Contents.ShuffleMask;
627 /// Return the offset from the symbol in this operand. This always returns 0 628 /// for ExternalSymbol operands. 632"Wrong MachineOperand accessor");
633return int64_t(
uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
634 SmallContents.OffsetLo;
639return Contents.OffsetedInfo.Val.SymbolName;
642 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg. 643 /// It is sometimes necessary to detach the register mask pointer from its 644 /// machine operand. This static method can be used for such detached bit 647// See TargetRegisterInfo.h. 649"Not a physical register");
650return !(RegMask[PhysReg.
id() / 32] & (1u << PhysReg.
id() % 32));
653 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. 658 /// getRegMask - Returns a bit mask of registers preserved by this RegMask 662return Contents.RegMask;
665 /// Returns number of elements needed for a regmask array. 667return (NumRegs + 31) / 32;
670 /// getRegLiveOut - Returns a bit mask of live-out registers. 673return Contents.RegMask;
681//===--------------------------------------------------------------------===// 682// Mutators for various operand types. 683//===--------------------------------------------------------------------===// 687 Contents.ImmVal = immVal;
703"Wrong MachineOperand mutator");
705 Contents.OffsetedInfo.OffsetHi = int(
Offset >> 32);
710"Wrong MachineOperand mutator");
711 Contents.OffsetedInfo.Val.Index =
Idx;
721 Contents.InstrRef.InstrIdx = InstrIdx;
725 Contents.InstrRef.OpIdx = OpIdx;
733 /// Sets value of register mask operand referencing Mask. The 734 /// operand does not take ownership of the memory referenced by Mask, it must 735 /// remain valid for the lifetime of the operand. See CreateRegMask(). 736 /// Any physreg with a 0 bit in the mask is clobbered by the instruction. 739 Contents.RegMask = RegMaskPtr;
744 Contents.IntrinsicID = IID;
752//===--------------------------------------------------------------------===// 754//===--------------------------------------------------------------------===// 756 /// Returns true if this operand is identical to the specified operand except 757 /// for liveness related flags (isKill, isUndef and isDead). Note that this 758 /// should stay in sync with the hash_value overload below. 761 /// MachineOperand hash_value overload. 763 /// Note that this includes the same information in the hash that 764 /// isIdenticalTo uses for comparison. It is thus suited for use in hash 765 /// tables which use that function for equality comparisons only. This must 766 /// stay exactly in sync with isIdenticalTo above. 769 /// ChangeToImmediate - Replace this operand with a new immediate operand of 770 /// the specified value. If an operand is known to be an immediate already, 771 /// the setImm method should be used. 774 /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand 775 /// of the specified value. If an operand is known to be an FP immediate 776 /// already, the setFPImm method should be used. 779 /// ChangeToES - Replace this operand with a new external symbol operand. 780voidChangeToES(
constchar *SymName,
unsigned TargetFlags = 0);
782 /// ChangeToGA - Replace this operand with a new global address operand. 784unsigned TargetFlags = 0);
786 /// ChangeToBA - Replace this operand with a new block address operand. 788unsigned TargetFlags = 0);
790 /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand. 793 /// Replace this operand with a frame index. 796 /// Replace this operand with a target index. 798unsigned TargetFlags = 0);
800 /// Replace this operand with an Instruction Reference. 802unsigned TargetFlags = 0);
804 /// ChangeToRegister - Replace this operand with a new register operand of 805 /// the specified value. If an operand is known to be an register already, 806 /// the setReg method should be used. 811 /// getTargetIndexName - If this MachineOperand is a TargetIndex that has a 812 /// name, attempt to get the name. Returns nullptr if the TargetIndex does not 813 /// have a name. Asserts if MO is not a TargetIndex. 816//===--------------------------------------------------------------------===// 817// Construction methods. 818//===--------------------------------------------------------------------===// 834Op.Contents.CFP = CFP;
857Op.SmallContents.RegNo =
Reg.id();
858Op.Contents.Reg.Prev =
nullptr;
859Op.Contents.Reg.Next =
nullptr;
864unsigned TargetFlags = 0) {
867Op.setTargetFlags(TargetFlags);
876unsigned TargetFlags = 0) {
880Op.setTargetFlags(TargetFlags);
884unsigned TargetFlags = 0) {
888Op.setTargetFlags(TargetFlags);
894Op.setTargetFlags(TargetFlags);
898unsigned TargetFlags = 0) {
900Op.Contents.OffsetedInfo.Val.GV = GV;
902Op.setTargetFlags(TargetFlags);
906unsigned TargetFlags = 0) {
908Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
909Op.setOffset(0);
// Offset is always 0. 910Op.setTargetFlags(TargetFlags);
914unsigned TargetFlags = 0) {
916Op.Contents.OffsetedInfo.Val.BA = BA;
918Op.setTargetFlags(TargetFlags);
921 /// CreateRegMask - Creates a register mask operand referencing Mask. The 922 /// operand does not take ownership of the memory referenced by Mask, it 923 /// must remain valid for the lifetime of the operand. 925 /// A RegMask operand represents a set of non-clobbered physical registers 926 /// on an instruction that clobbers many registers, typically a call. The 927 /// bit mask has a bit set for each physreg that is preserved by this 928 /// instruction, as described in the documentation for 929 /// TargetRegisterInfo::getCallPreservedMask(). 931 /// Any physreg with a 0 bit in the mask is clobbered by the instruction. 934assert(Mask &&
"Missing register mask");
936Op.Contents.RegMask = Mask;
940assert(Mask &&
"Missing live-out register mask");
942Op.Contents.RegMask = Mask;
947Op.Contents.MD = Meta;
952unsigned TargetFlags = 0) {
956Op.setTargetFlags(TargetFlags);
962Op.Contents.InstrRef.InstrIdx = InstrIdx;
963Op.Contents.InstrRef.OpIdx = OpIdx;
969Op.Contents.CFIIndex = CFIIndex;
975Op.Contents.IntrinsicID =
ID;
981Op.Contents.Pred = Pred;
987Op.Contents.ShuffleMask = Mask;
995// If this operand is currently a register operand, and if this is in a 996// function, deregister the operand from the register's use/def list. 997void removeRegFromUses();
999 /// Artificial kinds for DenseMap usage. 1000 enum :
unsignedchar {
1007//===--------------------------------------------------------------------===// 1008// Methods for handling register use/def lists. 1009//===--------------------------------------------------------------------===// 1011 /// isOnRegUseList - Return true if this operand is on a register use/def 1012 /// list or false if not. This can only be called for register operands 1013 /// that are part of a machine instruction. 1014bool isOnRegUseList()
const{
1015assert(
isReg() &&
"Can only add reg operand to use lists");
1016return Contents.Reg.Prev !=
nullptr;
1023 MachineOperand::MO_Empty));
1027 MachineOperand::MO_Tombstone));
1034 MachineOperand::MO_Empty) ||
1036 MachineOperand::MO_Tombstone))
1037returnLHS.getType() ==
RHS.getType();
1038returnLHS.isIdenticalTo(
RHS);
1047// See friend declaration above. This additional declaration is required in 1048// order to compile LLVM with IBM xlC compiler. 1049hash_code
hash_value(
const MachineOperand &MO);
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines DenseMapInfo traits for DenseMap.
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
The address of a basic block.
ConstantFP - Floating Point Values [float, double].
This is the shared class of boolean and integer constants.
This class represents an Operation in the Expression.
Wrapper class representing physical registers. Should be passed by value.
constexpr bool isValid() const
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
constexpr unsigned id() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
void setIsUse(bool Val=true)
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
unsigned getInstrRefOpIndex() const
void setInstrRefInstrIndex(unsigned InstrIdx)
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
const GlobalValue * getGlobal() const
void setImplicit(bool Val=true)
void setIsInternalRead(bool Val=true)
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
void setInstrRefOpIndex(unsigned OpIdx)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
const ConstantInt * getCImm() const
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
static MachineOperand CreateFPImm(const ConstantFP *CFP)
void setImm(int64_t immVal)
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
void setRegMask(const uint32_t *RegMaskPtr)
Sets value of register mask operand referencing Mask.
unsigned getInstrRefInstrIndex() const
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
void setFPImm(const ConstantFP *CFP)
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
bool isIntrinsicID() const
void setIsRenamable(bool Val=true)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MDNode * getMetadata() const
MachineBasicBlock * getMBB() const
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
friend hash_code hash_value(const MachineOperand &MO)
MachineOperand hash_value overload.
static MachineOperand CreateCImm(const ConstantInt *CI)
void setIsDead(bool Val=true)
ArrayRef< int > getShuffleMask() const
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
void setReg(Register Reg)
Change the register this operand corresponds to.
void setMetadata(const MDNode *MD)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isValidExcessOperand() const
Return true if this operand can validly be appended to an arbitrary operand list.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
bool clobbersPhysReg(MCRegister PhysReg) const
clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
void clearParent()
clearParent - Reset the parent pointer.
bool isShuffleMask() const
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
unsigned getCFIIndex() const
void setIsKill(bool Val=true)
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
void ChangeToBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
ChangeToBA - Replace this operand with a new block address operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
static MachineOperand CreateMetadata(const MDNode *Meta)
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
void ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx, unsigned TargetFlags=0)
Replace this operand with an Instruction Reference.
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
const BlockAddress * getBlockAddress() const
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
static MachineOperand CreatePredicate(unsigned Pred)
void setMBB(MachineBasicBlock *MBB)
bool isRegLiveOut() const
isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
void setIsEarlyClobber(bool Val=true)
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
void setOffset(int64_t Offset)
void setCImm(const ConstantInt *CI)
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
unsigned getTargetFlags() const
static MachineOperand CreateImm(int64_t Val)
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
void setPredicate(unsigned Predicate)
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
const char * getSymbolName() const
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
void setIsUndef(bool Val=true)
void setIsDebug(bool Val=true)
bool isEarlyClobber() const
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Register getReg() const
getReg - Returns the register number.
bool isTargetIndex() const
isTargetIndex - Tests if this is a MO_TargetIndex operand.
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
void setIntrinsicID(Intrinsic::ID IID)
void addTargetFlag(unsigned F)
bool isDbgInstrRef() const
Intrinsic::ID getIntrinsicID() const
bool isInternalRead() const
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
void setTargetFlags(unsigned F)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
const ConstantFP * getFPImm() const
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
const MachineInstr * getParent() const
unsigned getPredicate() const
MCSymbol * getMCSymbol() const
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_Predicate
Generic predicate for ISel.
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
@ MO_CImmediate
Immediate >64bit operand.
@ MO_BlockAddress
Address of a basic block.
@ MO_DbgInstrRef
Integer indices referring to an instruction+operand.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_IntrinsicID
Intrinsic ID for ISel.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
@ MO_TargetIndex
Target-dependent index+offset operand.
@ MO_Metadata
Metadata reference (for debug info)
@ MO_FPImmediate
Floating-point immediate operand.
@ MO_RegisterLiveOut
Mask of live-out registers.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
int64_t getOffset() const
Return the offset from the symbol in this operand.
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
static MachineOperand CreateFI(int Idx)
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Manage lifetime of a slot tracker for printing IR.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
TargetIntrinsicInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
An opaque object representing a hash code.
This class implements an extremely fast bulk output stream that can only output to a stream.
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
hash_code hash_value(const FixedPointSemantics &Val)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
DWARFExpression::Operation Op
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
static unsigned getHashValue(const MachineOperand &MO)
static MachineOperand getTombstoneKey()
static MachineOperand getEmptyKey()
static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS)
An information struct used to provide DenseMap with the various necessary components for a given valu...
