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LLVM 20.0.0git
MachineOperand.cpp
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1//===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file Methods common to all machine operands.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineOperand.h"
14#include "llvm/ADT/StableHashing.h"
15#include "llvm/ADT/StringExtras.h"
16#include "llvm/Analysis/Loads.h"
17#include "llvm/CodeGen/MIRFormatter.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineJumpTableInfo.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/CodeGen/PseudoSourceValueManager.h"
22#include "llvm/CodeGen/TargetInstrInfo.h"
23#include "llvm/CodeGen/TargetRegisterInfo.h"
24#include "llvm/Config/llvm-config.h"
25#include "llvm/IR/Constants.h"
26#include "llvm/IR/IRPrintingPasses.h"
27#include "llvm/IR/Instructions.h"
28#include "llvm/IR/ModuleSlotTracker.h"
29#include "llvm/MC/MCDwarf.h"
30#include "llvm/Target/TargetIntrinsicInfo.h"
31#include "llvm/Target/TargetMachine.h"
32#include <optional>
33
34using namespacellvm;
35
36staticcl::opt<int>
37PrintRegMaskNumRegs("print-regmask-num-regs",
38cl::desc("Number of registers to limit to when "
39"printing regmask operands in IR dumps. "
40"unlimited = -1"),
41cl::init(32),cl::Hidden);
42
43staticconstMachineFunction *getMFIfAvailable(constMachineOperand &MO) {
44if (constMachineInstr *MI = MO.getParent())
45if (constMachineBasicBlock *MBB =MI->getParent())
46if (constMachineFunction *MF =MBB->getParent())
47return MF;
48returnnullptr;
49}
50
51staticMachineFunction *getMFIfAvailable(MachineOperand &MO) {
52returnconst_cast<MachineFunction *>(
53getMFIfAvailable(const_cast<constMachineOperand &>(MO)));
54}
55
56unsignedMachineOperand::getOperandNo() const{
57assert(getParent() &&"Operand does not belong to any instruction!");
58returngetParent()->getOperandNo(this);
59}
60
61voidMachineOperand::setReg(Register Reg) {
62if (getReg() == Reg)
63return;// No change.
64
65// Clear the IsRenamable bit to keep it conservatively correct.
66 IsRenamable =false;
67
68// Otherwise, we have to change the register. If this operand is embedded
69// into a machine function, we need to update the old and new register's
70// use/def lists.
71if (MachineFunction *MF =getMFIfAvailable(*this)) {
72MachineRegisterInfo &MRI = MF->getRegInfo();
73MRI.removeRegOperandFromUseList(this);
74 SmallContents.RegNo = Reg.id();
75MRI.addRegOperandToUseList(this);
76return;
77 }
78
79// Otherwise, just change the register, no problem. :)
80 SmallContents.RegNo = Reg.id();
81}
82
83voidMachineOperand::substVirtReg(Register Reg,unsigned SubIdx,
84constTargetRegisterInfo &TRI) {
85assert(Reg.isVirtual());
86if (SubIdx &&getSubReg())
87 SubIdx =TRI.composeSubRegIndices(SubIdx,getSubReg());
88setReg(Reg);
89if (SubIdx)
90setSubReg(SubIdx);
91}
92
93voidMachineOperand::substPhysReg(MCRegister Reg,constTargetRegisterInfo &TRI) {
94assert(Reg.isPhysical());
95if (getSubReg()) {
96 Reg =TRI.getSubReg(Reg,getSubReg());
97// Note that getSubReg() may return 0 if the sub-register doesn't exist.
98// That won't happen in legal code.
99setSubReg(0);
100if (isDef())
101setIsUndef(false);
102 }
103setReg(Reg);
104}
105
106/// Change a def to a use, or a use to a def.
107voidMachineOperand::setIsDef(bool Val) {
108assert(isReg() &&"Wrong MachineOperand accessor");
109assert((!Val || !isDebug()) &&"Marking a debug operation as def");
110if (IsDef == Val)
111return;
112assert(!IsDeadOrKill &&"Changing def/use with dead/kill set not supported");
113// MRI may keep uses and defs in different list positions.
114if (MachineFunction *MF =getMFIfAvailable(*this)) {
115MachineRegisterInfo &MRI = MF->getRegInfo();
116MRI.removeRegOperandFromUseList(this);
117 IsDef = Val;
118MRI.addRegOperandToUseList(this);
119return;
120 }
121 IsDef = Val;
122}
123
124boolMachineOperand::isRenamable() const{
125assert(isReg() &&"Wrong MachineOperand accessor");
126assert(getReg().isPhysical() &&
127"isRenamable should only be checked on physical registers");
128if (!IsRenamable)
129returnfalse;
130
131constMachineInstr *MI =getParent();
132if (!MI)
133returntrue;
134
135if (isDef())
136return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
137
138assert(isUse() &&"Reg is not def or use");
139return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
140}
141
142voidMachineOperand::setIsRenamable(bool Val) {
143assert(isReg() &&"Wrong MachineOperand accessor");
144assert(getReg().isPhysical() &&
145"setIsRenamable should only be called on physical registers");
146 IsRenamable = Val;
147}
148
149// If this operand is currently a register operand, and if this is in a
150// function, deregister the operand from the register's use/def list.
151void MachineOperand::removeRegFromUses() {
152if (!isReg() || !isOnRegUseList())
153return;
154
155if (MachineFunction *MF =getMFIfAvailable(*this))
156 MF->getRegInfo().removeRegOperandFromUseList(this);
157}
158
159/// ChangeToImmediate - Replace this operand with a new immediate operand of
160/// the specified value. If an operand is known to be an immediate already,
161/// the setImm method should be used.
162voidMachineOperand::ChangeToImmediate(int64_t ImmVal,unsigned TargetFlags) {
163assert((!isReg() || !isTied()) &&"Cannot change a tied operand into an imm");
164
165 removeRegFromUses();
166
167 OpKind =MO_Immediate;
168 Contents.ImmVal = ImmVal;
169setTargetFlags(TargetFlags);
170}
171
172voidMachineOperand::ChangeToFPImmediate(constConstantFP *FPImm,
173unsigned TargetFlags) {
174assert((!isReg() || !isTied()) &&"Cannot change a tied operand into an imm");
175
176 removeRegFromUses();
177
178 OpKind =MO_FPImmediate;
179 Contents.CFP = FPImm;
180setTargetFlags(TargetFlags);
181}
182
183voidMachineOperand::ChangeToES(constchar *SymName,
184unsigned TargetFlags) {
185assert((!isReg() || !isTied()) &&
186"Cannot change a tied operand into an external symbol");
187
188 removeRegFromUses();
189
190 OpKind =MO_ExternalSymbol;
191 Contents.OffsetedInfo.Val.SymbolName = SymName;
192setOffset(0);// Offset is always 0.
193setTargetFlags(TargetFlags);
194}
195
196voidMachineOperand::ChangeToGA(constGlobalValue *GV, int64_tOffset,
197unsigned TargetFlags) {
198assert((!isReg() || !isTied()) &&
199"Cannot change a tied operand into a global address");
200
201 removeRegFromUses();
202
203 OpKind =MO_GlobalAddress;
204 Contents.OffsetedInfo.Val.GV = GV;
205setOffset(Offset);
206setTargetFlags(TargetFlags);
207}
208
209voidMachineOperand::ChangeToBA(constBlockAddress *BA, int64_tOffset,
210unsigned TargetFlags) {
211assert((!isReg() || !isTied()) &&
212"Cannot change a tied operand into a block address");
213
214 removeRegFromUses();
215
216 OpKind =MO_BlockAddress;
217 Contents.OffsetedInfo.Val.BA = BA;
218setOffset(Offset);
219setTargetFlags(TargetFlags);
220}
221
222voidMachineOperand::ChangeToMCSymbol(MCSymbol *Sym,unsigned TargetFlags) {
223assert((!isReg() || !isTied()) &&
224"Cannot change a tied operand into an MCSymbol");
225
226 removeRegFromUses();
227
228 OpKind =MO_MCSymbol;
229 Contents.Sym =Sym;
230setTargetFlags(TargetFlags);
231}
232
233voidMachineOperand::ChangeToFrameIndex(intIdx,unsigned TargetFlags) {
234assert((!isReg() || !isTied()) &&
235"Cannot change a tied operand into a FrameIndex");
236
237 removeRegFromUses();
238
239 OpKind =MO_FrameIndex;
240setIndex(Idx);
241setTargetFlags(TargetFlags);
242}
243
244voidMachineOperand::ChangeToTargetIndex(unsignedIdx, int64_tOffset,
245unsigned TargetFlags) {
246assert((!isReg() || !isTied()) &&
247"Cannot change a tied operand into a FrameIndex");
248
249 removeRegFromUses();
250
251 OpKind =MO_TargetIndex;
252setIndex(Idx);
253setOffset(Offset);
254setTargetFlags(TargetFlags);
255}
256
257voidMachineOperand::ChangeToDbgInstrRef(unsigned InstrIdx,unsigned OpIdx,
258unsigned TargetFlags) {
259assert((!isReg() || !isTied()) &&
260"Cannot change a tied operand into a DbgInstrRef");
261
262 removeRegFromUses();
263
264 OpKind =MO_DbgInstrRef;
265setInstrRefInstrIndex(InstrIdx);
266setInstrRefOpIndex(OpIdx);
267setTargetFlags(TargetFlags);
268}
269
270/// ChangeToRegister - Replace this operand with a new register operand of
271/// the specified value. If an operand is known to be an register already,
272/// the setReg method should be used.
273voidMachineOperand::ChangeToRegister(Register Reg,bool isDef,bool isImp,
274bool isKill,boolisDead,boolisUndef,
275boolisDebug) {
276MachineRegisterInfo *RegInfo =nullptr;
277if (MachineFunction *MF =getMFIfAvailable(*this))
278 RegInfo = &MF->getRegInfo();
279// If this operand is already a register operand, remove it from the
280// register's use/def lists.
281bool WasReg =isReg();
282if (RegInfo && WasReg)
283 RegInfo->removeRegOperandFromUseList(this);
284
285// Ensure debug instructions set debug flag on register uses.
286constMachineInstr *MI =getParent();
287if (!isDef &&MI &&MI->isDebugInstr())
288isDebug =true;
289
290// Change this to a register and set the reg#.
291assert(!(isDead && !isDef) &&"Dead flag on non-def");
292assert(!(isKill &&isDef) &&"Kill flag on def");
293 OpKind =MO_Register;
294 SmallContents.RegNo = Reg.id();
295 SubReg_TargetFlags = 0;
296 IsDef =isDef;
297 IsImp = isImp;
298 IsDeadOrKill =isKill |isDead;
299 IsRenamable =false;
300 IsUndef =isUndef;
301 IsInternalRead =false;
302 IsEarlyClobber =false;
303 IsDebug =isDebug;
304// Ensure isOnRegUseList() returns false.
305 Contents.Reg.Prev =nullptr;
306// Preserve the tie when the operand was already a register.
307if (!WasReg)
308 TiedTo = 0;
309
310// If this operand is embedded in a function, add the operand to the
311// register's use/def list.
312if (RegInfo)
313 RegInfo->addRegOperandToUseList(this);
314}
315
316/// isIdenticalTo - Return true if this operand is identical to the specified
317/// operand. Note that this should stay in sync with the hash_value overload
318/// below.
319boolMachineOperand::isIdenticalTo(constMachineOperand &Other) const{
320if (getType() !=Other.getType() ||
321getTargetFlags() !=Other.getTargetFlags())
322returnfalse;
323
324switch (getType()) {
325caseMachineOperand::MO_Register:
326returngetReg() ==Other.getReg() &&isDef() ==Other.isDef() &&
327getSubReg() ==Other.getSubReg();
328caseMachineOperand::MO_Immediate:
329returngetImm() ==Other.getImm();
330caseMachineOperand::MO_CImmediate:
331returngetCImm() ==Other.getCImm();
332caseMachineOperand::MO_FPImmediate:
333returngetFPImm() ==Other.getFPImm();
334caseMachineOperand::MO_MachineBasicBlock:
335returngetMBB() ==Other.getMBB();
336caseMachineOperand::MO_FrameIndex:
337returngetIndex() ==Other.getIndex();
338caseMachineOperand::MO_ConstantPoolIndex:
339caseMachineOperand::MO_TargetIndex:
340returngetIndex() ==Other.getIndex() &&getOffset() ==Other.getOffset();
341caseMachineOperand::MO_JumpTableIndex:
342returngetIndex() ==Other.getIndex();
343caseMachineOperand::MO_GlobalAddress:
344returngetGlobal() ==Other.getGlobal() &&getOffset() ==Other.getOffset();
345caseMachineOperand::MO_ExternalSymbol:
346return strcmp(getSymbolName(),Other.getSymbolName()) == 0 &&
347getOffset() ==Other.getOffset();
348caseMachineOperand::MO_BlockAddress:
349returngetBlockAddress() ==Other.getBlockAddress() &&
350getOffset() ==Other.getOffset();
351caseMachineOperand::MO_RegisterMask:
352caseMachineOperand::MO_RegisterLiveOut: {
353// Shallow compare of the two RegMasks
354constuint32_t *RegMask =getRegMask();
355constuint32_t *OtherRegMask =Other.getRegMask();
356if (RegMask == OtherRegMask)
357returntrue;
358
359if (constMachineFunction *MF =getMFIfAvailable(*this)) {
360constTargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
361unsigned RegMaskSize =MachineOperand::getRegMaskSize(TRI->getNumRegs());
362// Deep compare of the two RegMasks
363return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
364 }
365// We don't know the size of the RegMask, so we can't deep compare the two
366// reg masks.
367returnfalse;
368 }
369caseMachineOperand::MO_MCSymbol:
370returngetMCSymbol() ==Other.getMCSymbol();
371caseMachineOperand::MO_DbgInstrRef:
372returngetInstrRefInstrIndex() ==Other.getInstrRefInstrIndex() &&
373getInstrRefOpIndex() ==Other.getInstrRefOpIndex();
374caseMachineOperand::MO_CFIIndex:
375returngetCFIIndex() ==Other.getCFIIndex();
376caseMachineOperand::MO_Metadata:
377returngetMetadata() ==Other.getMetadata();
378caseMachineOperand::MO_IntrinsicID:
379returngetIntrinsicID() ==Other.getIntrinsicID();
380caseMachineOperand::MO_Predicate:
381returngetPredicate() ==Other.getPredicate();
382caseMachineOperand::MO_ShuffleMask:
383returngetShuffleMask() ==Other.getShuffleMask();
384 }
385llvm_unreachable("Invalid machine operand type");
386}
387
388// Note: this must stay exactly in sync with isIdenticalTo above.
389hash_codellvm::hash_value(constMachineOperand &MO) {
390switch (MO.getType()) {
391caseMachineOperand::MO_Register:
392// Register operands don't have target flags.
393returnhash_combine(MO.getType(), MO.getReg().id(), MO.getSubReg(),
394 MO.isDef());
395caseMachineOperand::MO_Immediate:
396returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
397caseMachineOperand::MO_CImmediate:
398returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
399caseMachineOperand::MO_FPImmediate:
400returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
401caseMachineOperand::MO_MachineBasicBlock:
402returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
403caseMachineOperand::MO_FrameIndex:
404returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
405caseMachineOperand::MO_ConstantPoolIndex:
406caseMachineOperand::MO_TargetIndex:
407returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
408 MO.getOffset());
409caseMachineOperand::MO_JumpTableIndex:
410returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
411caseMachineOperand::MO_ExternalSymbol:
412returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
413StringRef(MO.getSymbolName()));
414caseMachineOperand::MO_GlobalAddress:
415returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
416 MO.getOffset());
417caseMachineOperand::MO_BlockAddress:
418returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
419 MO.getOffset());
420caseMachineOperand::MO_RegisterMask:
421caseMachineOperand::MO_RegisterLiveOut: {
422if (constMachineFunction *MF =getMFIfAvailable(MO)) {
423constTargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
424unsigned RegMaskSize =MachineOperand::getRegMaskSize(TRI->getNumRegs());
425constuint32_t *RegMask = MO.getRegMask();
426 std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);
427returnhash_combine(MO.getType(), MO.getTargetFlags(),
428stable_hash_combine(RegMaskHashes));
429 }
430
431assert(0 &&"MachineOperand not associated with any MachineFunction");
432returnhash_combine(MO.getType(), MO.getTargetFlags());
433 }
434caseMachineOperand::MO_Metadata:
435returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
436caseMachineOperand::MO_MCSymbol:
437returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
438caseMachineOperand::MO_DbgInstrRef:
439returnhash_combine(MO.getType(), MO.getTargetFlags(),
440 MO.getInstrRefInstrIndex(), MO.getInstrRefOpIndex());
441caseMachineOperand::MO_CFIIndex:
442returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
443caseMachineOperand::MO_IntrinsicID:
444returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
445caseMachineOperand::MO_Predicate:
446returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
447caseMachineOperand::MO_ShuffleMask:
448returnhash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
449 }
450llvm_unreachable("Invalid machine operand type");
451}
452
453// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
454// it.
455staticvoidtryToGetTargetInfo(constMachineOperand &MO,
456constTargetRegisterInfo *&TRI,
457constTargetIntrinsicInfo *&IntrinsicInfo) {
458if (constMachineFunction *MF =getMFIfAvailable(MO)) {
459TRI = MF->getSubtarget().getRegisterInfo();
460 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
461 }
462}
463
464staticconstchar *getTargetIndexName(constMachineFunction &MF,int Index) {
465constauto *TII = MF.getSubtarget().getInstrInfo();
466assert(TII &&"expected instruction info");
467auto Indices =TII->getSerializableTargetIndices();
468auto Found =find_if(Indices, [&](const std::pair<int, const char *> &I) {
469returnI.first == Index;
470 });
471if (Found != Indices.end())
472return Found->second;
473returnnullptr;
474}
475
476constchar *MachineOperand::getTargetIndexName() const{
477constMachineFunction *MF =getMFIfAvailable(*this);
478return MF ?::getTargetIndexName(*MF, this->getIndex()) :nullptr;
479}
480
481staticconstchar *getTargetFlagName(constTargetInstrInfo *TII,unsigned TF) {
482auto Flags =TII->getSerializableDirectMachineOperandTargetFlags();
483for (constauto &I : Flags) {
484if (I.first == TF) {
485returnI.second;
486 }
487 }
488returnnullptr;
489}
490
491staticvoidprintCFIRegister(unsigned DwarfReg,raw_ostream &OS,
492constTargetRegisterInfo *TRI) {
493if (!TRI) {
494OS <<"%dwarfreg." << DwarfReg;
495return;
496 }
497
498if (std::optional<MCRegister> Reg =TRI->getLLVMRegNum(DwarfReg,true))
499OS <<printReg(*Reg,TRI);
500else
501OS <<"<badreg>";
502}
503
504staticvoidprintIRBlockReference(raw_ostream &OS,constBasicBlock &BB,
505ModuleSlotTracker &MST) {
506OS <<"%ir-block.";
507if (BB.hasName()) {
508printLLVMNameWithoutPrefix(OS, BB.getName());
509return;
510 }
511 std::optional<int> Slot;
512if (constFunction *F = BB.getParent()) {
513if (F == MST.getCurrentFunction()) {
514 Slot = MST.getLocalSlot(&BB);
515 }elseif (constModule *M =F->getParent()) {
516ModuleSlotTracker CustomMST(M,/*ShouldInitializeAllMetadata=*/false);
517 CustomMST.incorporateFunction(*F);
518 Slot = CustomMST.getLocalSlot(&BB);
519 }
520 }
521if (Slot)
522MachineOperand::printIRSlotNumber(OS, *Slot);
523else
524OS <<"<unknown>";
525}
526
527staticvoidprintSyncScope(raw_ostream &OS,constLLVMContext &Context,
528SyncScope::ID SSID,
529SmallVectorImpl<StringRef> &SSNs) {
530switch (SSID) {
531caseSyncScope::System:
532break;
533default:
534if (SSNs.empty())
535 Context.getSyncScopeNames(SSNs);
536
537OS <<"syncscope(\"";
538 printEscapedString(SSNs[SSID],OS);
539OS <<"\") ";
540break;
541 }
542}
543
544staticconstchar *getTargetMMOFlagName(constTargetInstrInfo &TII,
545unsigned TMMOFlag) {
546auto Flags =TII.getSerializableMachineMemOperandTargetFlags();
547for (constauto &I : Flags) {
548if (I.first == TMMOFlag) {
549returnI.second;
550 }
551 }
552returnnullptr;
553}
554
555staticvoidprintFrameIndex(raw_ostream&OS,int FrameIndex,bool IsFixed,
556constMachineFrameInfo *MFI) {
557StringRefName;
558if (MFI) {
559 IsFixed = MFI->isFixedObjectIndex(FrameIndex);
560if (constAllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
561if (Alloca->hasName())
562Name = Alloca->getName();
563if (IsFixed)
564 FrameIndex -= MFI->getObjectIndexBegin();
565 }
566MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed,Name);
567}
568
569voidMachineOperand::printSubRegIdx(raw_ostream &OS,uint64_t Index,
570constTargetRegisterInfo *TRI) {
571OS <<"%subreg.";
572if (TRI && Index != 0 && Index < TRI->getNumSubRegIndices())
573OS <<TRI->getSubRegIndexName(Index);
574else
575OS << Index;
576}
577
578voidMachineOperand::printTargetFlags(raw_ostream &OS,
579constMachineOperand &Op) {
580if (!Op.getTargetFlags())
581return;
582constMachineFunction *MF =getMFIfAvailable(Op);
583if (!MF)
584return;
585
586constauto *TII = MF->getSubtarget().getInstrInfo();
587assert(TII &&"expected instruction info");
588auto Flags =TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
589OS <<"target-flags(";
590constbool HasDirectFlags = Flags.first;
591constbool HasBitmaskFlags = Flags.second;
592if (!HasDirectFlags && !HasBitmaskFlags) {
593OS <<"<unknown>) ";
594return;
595 }
596if (HasDirectFlags) {
597if (constauto *Name =getTargetFlagName(TII, Flags.first))
598OS <<Name;
599else
600OS <<"<unknown target flag>";
601 }
602if (!HasBitmaskFlags) {
603OS <<") ";
604return;
605 }
606bool IsCommaNeeded = HasDirectFlags;
607unsigned BitMask = Flags.second;
608auto BitMasks =TII->getSerializableBitmaskMachineOperandTargetFlags();
609for (constauto &Mask : BitMasks) {
610// Check if the flag's bitmask has the bits of the current mask set.
611if ((BitMask & Mask.first) == Mask.first) {
612if (IsCommaNeeded)
613OS <<", ";
614 IsCommaNeeded =true;
615OS << Mask.second;
616// Clear the bits which were serialized from the flag's bitmask.
617 BitMask &= ~(Mask.first);
618 }
619 }
620if (BitMask) {
621// When the resulting flag's bitmask isn't zero, we know that we didn't
622// serialize all of the bit flags.
623if (IsCommaNeeded)
624OS <<", ";
625OS <<"<unknown bitmask target flag>";
626 }
627OS <<") ";
628}
629
630voidMachineOperand::printSymbol(raw_ostream &OS,MCSymbol &Sym) {
631OS <<"<mcsymbol " <<Sym <<">";
632}
633
634voidMachineOperand::printStackObjectReference(raw_ostream &OS,
635unsigned FrameIndex,
636bool IsFixed,StringRefName) {
637if (IsFixed) {
638OS <<"%fixed-stack." << FrameIndex;
639return;
640 }
641
642OS <<"%stack." << FrameIndex;
643if (!Name.empty())
644OS <<'.' <<Name;
645}
646
647voidMachineOperand::printOperandOffset(raw_ostream &OS, int64_tOffset) {
648if (Offset == 0)
649return;
650if (Offset < 0) {
651OS <<" - " << -Offset;
652return;
653 }
654OS <<" + " <<Offset;
655}
656
657voidMachineOperand::printIRSlotNumber(raw_ostream &OS,int Slot) {
658if (Slot == -1)
659OS <<"<badref>";
660else
661OS << Slot;
662}
663
664staticvoidprintCFI(raw_ostream &OS,constMCCFIInstruction &CFI,
665constTargetRegisterInfo *TRI) {
666switch (CFI.getOperation()) {
667caseMCCFIInstruction::OpSameValue:
668OS <<"same_value ";
669if (MCSymbol *Label = CFI.getLabel())
670MachineOperand::printSymbol(OS, *Label);
671printCFIRegister(CFI.getRegister(),OS,TRI);
672break;
673caseMCCFIInstruction::OpRememberState:
674OS <<"remember_state ";
675if (MCSymbol *Label = CFI.getLabel())
676MachineOperand::printSymbol(OS, *Label);
677break;
678caseMCCFIInstruction::OpRestoreState:
679OS <<"restore_state ";
680if (MCSymbol *Label = CFI.getLabel())
681MachineOperand::printSymbol(OS, *Label);
682break;
683caseMCCFIInstruction::OpOffset:
684OS <<"offset ";
685if (MCSymbol *Label = CFI.getLabel())
686MachineOperand::printSymbol(OS, *Label);
687printCFIRegister(CFI.getRegister(),OS,TRI);
688OS <<", " << CFI.getOffset();
689break;
690caseMCCFIInstruction::OpDefCfaRegister:
691OS <<"def_cfa_register ";
692if (MCSymbol *Label = CFI.getLabel())
693MachineOperand::printSymbol(OS, *Label);
694printCFIRegister(CFI.getRegister(),OS,TRI);
695break;
696caseMCCFIInstruction::OpDefCfaOffset:
697OS <<"def_cfa_offset ";
698if (MCSymbol *Label = CFI.getLabel())
699MachineOperand::printSymbol(OS, *Label);
700OS << CFI.getOffset();
701break;
702caseMCCFIInstruction::OpDefCfa:
703OS <<"def_cfa ";
704if (MCSymbol *Label = CFI.getLabel())
705MachineOperand::printSymbol(OS, *Label);
706printCFIRegister(CFI.getRegister(),OS,TRI);
707OS <<", " << CFI.getOffset();
708break;
709caseMCCFIInstruction::OpLLVMDefAspaceCfa:
710OS <<"llvm_def_aspace_cfa ";
711if (MCSymbol *Label = CFI.getLabel())
712MachineOperand::printSymbol(OS, *Label);
713printCFIRegister(CFI.getRegister(),OS,TRI);
714OS <<", " << CFI.getOffset();
715OS <<", " << CFI.getAddressSpace();
716break;
717caseMCCFIInstruction::OpRelOffset:
718OS <<"rel_offset ";
719if (MCSymbol *Label = CFI.getLabel())
720MachineOperand::printSymbol(OS, *Label);
721printCFIRegister(CFI.getRegister(),OS,TRI);
722OS <<", " << CFI.getOffset();
723break;
724caseMCCFIInstruction::OpAdjustCfaOffset:
725OS <<"adjust_cfa_offset ";
726if (MCSymbol *Label = CFI.getLabel())
727MachineOperand::printSymbol(OS, *Label);
728OS << CFI.getOffset();
729break;
730caseMCCFIInstruction::OpRestore:
731OS <<"restore ";
732if (MCSymbol *Label = CFI.getLabel())
733MachineOperand::printSymbol(OS, *Label);
734printCFIRegister(CFI.getRegister(),OS,TRI);
735break;
736caseMCCFIInstruction::OpEscape: {
737OS <<"escape ";
738if (MCSymbol *Label = CFI.getLabel())
739MachineOperand::printSymbol(OS, *Label);
740if (!CFI.getValues().empty()) {
741size_t e = CFI.getValues().size() - 1;
742for (size_t i = 0; i < e; ++i)
743OS <<format("0x%02x",uint8_t(CFI.getValues()[i])) <<", ";
744OS <<format("0x%02x",uint8_t(CFI.getValues()[e]));
745 }
746break;
747 }
748caseMCCFIInstruction::OpUndefined:
749OS <<"undefined ";
750if (MCSymbol *Label = CFI.getLabel())
751MachineOperand::printSymbol(OS, *Label);
752printCFIRegister(CFI.getRegister(),OS,TRI);
753break;
754caseMCCFIInstruction::OpRegister:
755OS <<"register ";
756if (MCSymbol *Label = CFI.getLabel())
757MachineOperand::printSymbol(OS, *Label);
758printCFIRegister(CFI.getRegister(),OS,TRI);
759OS <<", ";
760printCFIRegister(CFI.getRegister2(),OS,TRI);
761break;
762caseMCCFIInstruction::OpWindowSave:
763OS <<"window_save ";
764if (MCSymbol *Label = CFI.getLabel())
765MachineOperand::printSymbol(OS, *Label);
766break;
767caseMCCFIInstruction::OpNegateRAState:
768OS <<"negate_ra_sign_state ";
769if (MCSymbol *Label = CFI.getLabel())
770MachineOperand::printSymbol(OS, *Label);
771break;
772caseMCCFIInstruction::OpNegateRAStateWithPC:
773OS <<"negate_ra_sign_state_with_pc ";
774if (MCSymbol *Label = CFI.getLabel())
775MachineOperand::printSymbol(OS, *Label);
776break;
777default:
778// TODO: Print the other CFI Operations.
779OS <<"<unserializable cfi directive>";
780break;
781 }
782}
783
784voidMachineOperand::print(raw_ostream &OS,constTargetRegisterInfo *TRI,
785constTargetIntrinsicInfo *IntrinsicInfo) const{
786print(OS,LLT{},TRI, IntrinsicInfo);
787}
788
789voidMachineOperand::print(raw_ostream &OS,LLT TypeToPrint,
790constTargetRegisterInfo *TRI,
791constTargetIntrinsicInfo *IntrinsicInfo) const{
792tryToGetTargetInfo(*this,TRI, IntrinsicInfo);
793ModuleSlotTracker DummyMST(nullptr);
794print(OS, DummyMST, TypeToPrint, std::nullopt,/*PrintDef=*/false,
795/*IsStandalone=*/true,
796/*ShouldPrintRegisterTies=*/true,
797/*TiedOperandIdx=*/0,TRI, IntrinsicInfo);
798}
799
800voidMachineOperand::print(raw_ostream &OS,ModuleSlotTracker &MST,
801LLT TypeToPrint, std::optional<unsigned> OpIdx,
802bool PrintDef,bool IsStandalone,
803bool ShouldPrintRegisterTies,
804unsigned TiedOperandIdx,
805constTargetRegisterInfo *TRI,
806constTargetIntrinsicInfo *IntrinsicInfo) const{
807printTargetFlags(OS, *this);
808switch (getType()) {
809caseMachineOperand::MO_Register: {
810Register Reg =getReg();
811if (isImplicit())
812OS << (isDef() ?"implicit-def " :"implicit ");
813elseif (PrintDef &&isDef())
814// Print the 'def' flag only when the operand is defined after '='.
815OS <<"def ";
816if (isInternalRead())
817OS <<"internal ";
818if (isDead())
819OS <<"dead ";
820if (isKill())
821OS <<"killed ";
822if (isUndef())
823OS <<"undef ";
824if (isEarlyClobber())
825OS <<"early-clobber ";
826if (getReg().isPhysical() &&isRenamable())
827OS <<"renamable ";
828// isDebug() is exactly true for register operands of a DBG_VALUE. So we
829// simply infer it when parsing and do not need to print it.
830
831constMachineRegisterInfo *MRI =nullptr;
832if (Reg.isVirtual()) {
833if (constMachineFunction *MF =getMFIfAvailable(*this)) {
834MRI = &MF->getRegInfo();
835 }
836 }
837
838OS <<printReg(Reg,TRI, 0,MRI);
839// Print the sub register.
840if (unsignedSubReg =getSubReg()) {
841if (TRI)
842OS <<'.' <<TRI->getSubRegIndexName(SubReg);
843else
844OS <<".subreg" <<SubReg;
845 }
846// Print the register class / bank.
847if (Reg.isVirtual()) {
848if (constMachineFunction *MF =getMFIfAvailable(*this)) {
849constMachineRegisterInfo &MRI = MF->getRegInfo();
850if (IsStandalone || !PrintDef ||MRI.def_empty(Reg)) {
851OS <<':';
852OS <<printRegClassOrBank(Reg,MRI,TRI);
853 }
854 }
855 }
856// Print ties.
857if (ShouldPrintRegisterTies &&isTied() && !isDef())
858OS <<"(tied-def " << TiedOperandIdx <<")";
859// Print types.
860if (TypeToPrint.isValid())
861OS <<'(' << TypeToPrint <<')';
862break;
863 }
864caseMachineOperand::MO_Immediate: {
865constMIRFormatter *Formatter =nullptr;
866if (constMachineFunction *MF =getMFIfAvailable(*this)) {
867constauto *TII = MF->getSubtarget().getInstrInfo();
868assert(TII &&"expected instruction info");
869 Formatter =TII->getMIRFormatter();
870 }
871if (Formatter)
872 Formatter->printImm(OS, *getParent(), OpIdx,getImm());
873else
874OS <<getImm();
875break;
876 }
877caseMachineOperand::MO_CImmediate:
878getCImm()->printAsOperand(OS,/*PrintType=*/true, MST);
879break;
880caseMachineOperand::MO_FPImmediate:
881getFPImm()->printAsOperand(OS,/*PrintType=*/true, MST);
882break;
883caseMachineOperand::MO_MachineBasicBlock:
884OS <<printMBBReference(*getMBB());
885break;
886caseMachineOperand::MO_FrameIndex: {
887int FrameIndex =getIndex();
888bool IsFixed =false;
889constMachineFrameInfo *MFI =nullptr;
890if (constMachineFunction *MF =getMFIfAvailable(*this))
891 MFI = &MF->getFrameInfo();
892printFrameIndex(OS, FrameIndex, IsFixed, MFI);
893break;
894 }
895caseMachineOperand::MO_ConstantPoolIndex:
896OS <<"%const." <<getIndex();
897printOperandOffset(OS,getOffset());
898break;
899caseMachineOperand::MO_TargetIndex: {
900OS <<"target-index(";
901constchar *Name ="<unknown>";
902if (constMachineFunction *MF =getMFIfAvailable(*this))
903if (constauto *TargetIndexName =::getTargetIndexName(*MF,getIndex()))
904Name = TargetIndexName;
905OS <<Name <<')';
906printOperandOffset(OS,getOffset());
907break;
908 }
909caseMachineOperand::MO_JumpTableIndex:
910OS <<printJumpTableEntryReference(getIndex());
911break;
912caseMachineOperand::MO_GlobalAddress:
913if (auto *GV =getGlobal())
914 GV->printAsOperand(OS,/*PrintType=*/false, MST);
915else// Invalid, but may appear in debugging scenarios.
916OS <<"globaladdress(null)";
917
918printOperandOffset(OS,getOffset());
919break;
920caseMachineOperand::MO_ExternalSymbol: {
921StringRefName =getSymbolName();
922OS <<'&';
923if (Name.empty()) {
924OS <<"\"\"";
925 }else {
926printLLVMNameWithoutPrefix(OS,Name);
927 }
928printOperandOffset(OS,getOffset());
929break;
930 }
931caseMachineOperand::MO_BlockAddress: {
932OS <<"blockaddress(";
933getBlockAddress()->getFunction()->printAsOperand(OS,/*PrintType=*/false,
934 MST);
935OS <<", ";
936printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
937OS <<')';
938MachineOperand::printOperandOffset(OS,getOffset());
939break;
940 }
941caseMachineOperand::MO_RegisterMask: {
942OS <<"<regmask";
943if (TRI) {
944unsigned NumRegsInMask = 0;
945unsigned NumRegsEmitted = 0;
946for (unsigned i = 0; i <TRI->getNumRegs(); ++i) {
947unsigned MaskWord = i / 32;
948unsigned MaskBit = i % 32;
949if (getRegMask()[MaskWord] & (1 << MaskBit)) {
950if (PrintRegMaskNumRegs < 0 ||
951 NumRegsEmitted <=static_cast<unsigned>(PrintRegMaskNumRegs)) {
952OS <<" " <<printReg(i,TRI);
953 NumRegsEmitted++;
954 }
955 NumRegsInMask++;
956 }
957 }
958if (NumRegsEmitted != NumRegsInMask)
959OS <<" and " << (NumRegsInMask - NumRegsEmitted) <<" more...";
960 }else {
961OS <<" ...";
962 }
963OS <<">";
964break;
965 }
966caseMachineOperand::MO_RegisterLiveOut: {
967constuint32_t *RegMask =getRegLiveOut();
968OS <<"liveout(";
969if (!TRI) {
970OS <<"<unknown>";
971 }else {
972bool IsCommaNeeded =false;
973for (unsigned Reg = 0, E =TRI->getNumRegs(); Reg < E; ++Reg) {
974if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
975if (IsCommaNeeded)
976OS <<", ";
977OS <<printReg(Reg,TRI);
978 IsCommaNeeded =true;
979 }
980 }
981 }
982OS <<")";
983break;
984 }
985caseMachineOperand::MO_Metadata:
986getMetadata()->printAsOperand(OS, MST);
987break;
988caseMachineOperand::MO_MCSymbol:
989printSymbol(OS, *getMCSymbol());
990break;
991caseMachineOperand::MO_DbgInstrRef: {
992OS <<"dbg-instr-ref(" <<getInstrRefInstrIndex() <<", "
993 <<getInstrRefOpIndex() <<')';
994break;
995 }
996caseMachineOperand::MO_CFIIndex: {
997if (constMachineFunction *MF =getMFIfAvailable(*this))
998printCFI(OS, MF->getFrameInstructions()[getCFIIndex()],TRI);
999else
1000OS <<"<cfi directive>";
1001break;
1002 }
1003caseMachineOperand::MO_IntrinsicID: {
1004Intrinsic::IDID =getIntrinsicID();
1005if (ID < Intrinsic::num_intrinsics)
1006OS <<"intrinsic(@" <<Intrinsic::getBaseName(ID) <<')';
1007elseif (IntrinsicInfo)
1008OS <<"intrinsic(@" << IntrinsicInfo->getName(ID) <<')';
1009else
1010OS <<"intrinsic(" <<ID <<')';
1011break;
1012 }
1013caseMachineOperand::MO_Predicate: {
1014auto Pred =static_cast<CmpInst::Predicate>(getPredicate());
1015OS << (CmpInst::isIntPredicate(Pred) ?"int" :"float") <<"pred("
1016 << Pred <<')';
1017break;
1018 }
1019caseMachineOperand::MO_ShuffleMask:
1020OS <<"shufflemask(";
1021ArrayRef<int> Mask =getShuffleMask();
1022StringRef Separator;
1023for (int Elt : Mask) {
1024if (Elt == -1)
1025OS << Separator <<"undef";
1026else
1027OS << Separator << Elt;
1028 Separator =", ";
1029 }
1030
1031OS <<')';
1032break;
1033 }
1034}
1035
1036#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1037LLVM_DUMP_METHODvoidMachineOperand::dump() const{dbgs() << *this <<'\n'; }
1038#endif
1039
1040//===----------------------------------------------------------------------===//
1041// MachineMemOperand Implementation
1042//===----------------------------------------------------------------------===//
1043
1044/// getAddrSpace - Return the LLVM IR address space number that this pointer
1045/// points into.
1046unsignedMachinePointerInfo::getAddrSpace() const{returnAddrSpace; }
1047
1048/// isDereferenceable - Return true if V is always dereferenceable for
1049/// Offset + Size byte.
1050boolMachinePointerInfo::isDereferenceable(unsignedSize,LLVMContext &C,
1051constDataLayout &DL) const{
1052if (!isa<const Value *>(V))
1053returnfalse;
1054
1055constValue *BasePtr = cast<const Value *>(V);
1056if (BasePtr ==nullptr)
1057returnfalse;
1058
1059returnisDereferenceableAndAlignedPointer(
1060 BasePtr,Align(1),APInt(DL.getPointerSizeInBits(),Offset +Size),DL,
1061 dyn_cast<Instruction>(BasePtr));
1062}
1063
1064/// getConstantPool - Return a MachinePointerInfo record that refers to the
1065/// constant pool.
1066MachinePointerInfoMachinePointerInfo::getConstantPool(MachineFunction &MF) {
1067returnMachinePointerInfo(MF.getPSVManager().getConstantPool());
1068}
1069
1070/// getFixedStack - Return a MachinePointerInfo record that refers to the
1071/// the specified FrameIndex.
1072MachinePointerInfoMachinePointerInfo::getFixedStack(MachineFunction &MF,
1073int FI, int64_tOffset) {
1074returnMachinePointerInfo(MF.getPSVManager().getFixedStack(FI),Offset);
1075}
1076
1077MachinePointerInfoMachinePointerInfo::getJumpTable(MachineFunction &MF) {
1078returnMachinePointerInfo(MF.getPSVManager().getJumpTable());
1079}
1080
1081MachinePointerInfoMachinePointerInfo::getGOT(MachineFunction &MF) {
1082returnMachinePointerInfo(MF.getPSVManager().getGOT());
1083}
1084
1085MachinePointerInfoMachinePointerInfo::getStack(MachineFunction &MF,
1086 int64_tOffset,uint8_tID) {
1087returnMachinePointerInfo(MF.getPSVManager().getStack(),Offset,ID);
1088}
1089
1090MachinePointerInfoMachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1091returnMachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1092}
1093
1094MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo,Flags f,
1095LLT type,Align a,constAAMDNodes &AAInfo,
1096constMDNode *Ranges,SyncScope::ID SSID,
1097AtomicOrdering Ordering,
1098AtomicOrdering FailureOrdering)
1099 : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1100 AAInfo(AAInfo), Ranges(Ranges) {
1101assert((PtrInfo.V.isNull() || isa<const PseudoSourceValue *>(PtrInfo.V) ||
1102 isa<PointerType>(cast<const Value *>(PtrInfo.V)->getType())) &&
1103"invalid pointer value");
1104assert((isLoad() ||isStore()) &&"Not a load/store!");
1105
1106AtomicInfo.SSID =static_cast<unsigned>(SSID);
1107assert(getSyncScopeID() == SSID &&"Value truncated");
1108AtomicInfo.Ordering =static_cast<unsigned>(Ordering);
1109assert(getSuccessOrdering() == Ordering &&"Value truncated");
1110AtomicInfo.FailureOrdering =static_cast<unsigned>(FailureOrdering);
1111assert(getFailureOrdering() == FailureOrdering &&"Value truncated");
1112}
1113
1114MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo,FlagsF,
1115LocationSize TS,Align BaseAlignment,
1116constAAMDNodes &AAInfo,
1117constMDNode *Ranges,SyncScope::ID SSID,
1118AtomicOrdering Ordering,
1119AtomicOrdering FailureOrdering)
1120 :MachineMemOperand(
1121 ptrinfo,F,
1122 !TS.hasValue() ?LLT()
1123 : TS.isScalable()
1124 ?LLT::scalable_vector(1, 8 * TS.getValue().getKnownMinValue())
1125 :LLT::scalar(8 * TS.getValue().getKnownMinValue()),
1126 BaseAlignment, AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1127
1128voidMachineMemOperand::refineAlignment(constMachineMemOperand *MMO) {
1129// The Value and Offset may differ due to CSE. But the flags and size
1130// should be the same.
1131assert(MMO->getFlags() ==getFlags() &&"Flags mismatch!");
1132assert((!MMO->getSize().hasValue() || !getSize().hasValue() ||
1133 MMO->getSize() ==getSize()) &&
1134"Size mismatch!");
1135if (MMO->getBaseAlign() >=getBaseAlign()) {
1136// Update the alignment value.
1137 BaseAlign = MMO->getBaseAlign();
1138// Also update the base and offset, because the new alignment may
1139// not be applicable with the old ones.
1140 PtrInfo = MMO->PtrInfo;
1141 }
1142}
1143
1144/// getAlign - Return the minimum known alignment in bytes of the
1145/// actual memory reference.
1146AlignMachineMemOperand::getAlign() const{
1147returncommonAlignment(getBaseAlign(),getOffset());
1148}
1149
1150voidMachineMemOperand::print(raw_ostream &OS,ModuleSlotTracker &MST,
1151SmallVectorImpl<StringRef> &SSNs,
1152constLLVMContext &Context,
1153constMachineFrameInfo *MFI,
1154constTargetInstrInfo *TII) const{
1155OS <<'(';
1156if (isVolatile())
1157OS <<"volatile ";
1158if (isNonTemporal())
1159OS <<"non-temporal ";
1160if (isDereferenceable())
1161OS <<"dereferenceable ";
1162if (isInvariant())
1163OS <<"invariant ";
1164if (TII) {
1165if (getFlags() &MachineMemOperand::MOTargetFlag1)
1166OS <<'"' <<getTargetMMOFlagName(*TII,MachineMemOperand::MOTargetFlag1)
1167 <<"\" ";
1168if (getFlags() &MachineMemOperand::MOTargetFlag2)
1169OS <<'"' <<getTargetMMOFlagName(*TII,MachineMemOperand::MOTargetFlag2)
1170 <<"\" ";
1171if (getFlags() &MachineMemOperand::MOTargetFlag3)
1172OS <<'"' <<getTargetMMOFlagName(*TII,MachineMemOperand::MOTargetFlag3)
1173 <<"\" ";
1174if (getFlags() &MachineMemOperand::MOTargetFlag4)
1175OS <<'"' <<getTargetMMOFlagName(*TII,MachineMemOperand::MOTargetFlag4)
1176 <<"\" ";
1177 }else {
1178if (getFlags() &MachineMemOperand::MOTargetFlag1)
1179OS <<"\"MOTargetFlag1\" ";
1180if (getFlags() &MachineMemOperand::MOTargetFlag2)
1181OS <<"\"MOTargetFlag2\" ";
1182if (getFlags() &MachineMemOperand::MOTargetFlag3)
1183OS <<"\"MOTargetFlag3\" ";
1184if (getFlags() &MachineMemOperand::MOTargetFlag4)
1185OS <<"\"MOTargetFlag4\" ";
1186 }
1187
1188assert((isLoad() ||isStore()) &&
1189"machine memory operand must be a load or store (or both)");
1190if (isLoad())
1191OS <<"load ";
1192if (isStore())
1193OS <<"store ";
1194
1195printSyncScope(OS, Context,getSyncScopeID(), SSNs);
1196
1197if (getSuccessOrdering() !=AtomicOrdering::NotAtomic)
1198OS <<toIRString(getSuccessOrdering()) <<' ';
1199if (getFailureOrdering() !=AtomicOrdering::NotAtomic)
1200OS <<toIRString(getFailureOrdering()) <<' ';
1201
1202if (getMemoryType().isValid())
1203OS <<'(' <<getMemoryType() <<')';
1204else
1205OS <<"unknown-size";
1206
1207if (constValue *Val =getValue()) {
1208OS << ((isLoad() &&isStore()) ?" on " :isLoad() ?" from " :" into ");
1209MIRFormatter::printIRValue(OS, *Val, MST);
1210 }elseif (constPseudoSourceValue *PVal =getPseudoValue()) {
1211OS << ((isLoad() &&isStore()) ?" on " :isLoad() ?" from " :" into ");
1212assert(PVal &&"Expected a pseudo source value");
1213switch (PVal->kind()) {
1214casePseudoSourceValue::Stack:
1215OS <<"stack";
1216break;
1217casePseudoSourceValue::GOT:
1218OS <<"got";
1219break;
1220casePseudoSourceValue::JumpTable:
1221OS <<"jump-table";
1222break;
1223casePseudoSourceValue::ConstantPool:
1224OS <<"constant-pool";
1225break;
1226casePseudoSourceValue::FixedStack: {
1227int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1228bool IsFixed =true;
1229printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1230break;
1231 }
1232casePseudoSourceValue::GlobalValueCallEntry:
1233OS <<"call-entry ";
1234 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1235OS,/*PrintType=*/false, MST);
1236break;
1237casePseudoSourceValue::ExternalSymbolCallEntry:
1238OS <<"call-entry &";
1239printLLVMNameWithoutPrefix(
1240OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1241break;
1242default: {
1243constMIRFormatter *Formatter =TII->getMIRFormatter();
1244// FIXME: This is not necessarily the correct MIR serialization format for
1245// a custom pseudo source value, but at least it allows
1246// MIR printing to work on a target with custom pseudo source
1247// values.
1248OS <<"custom \"";
1249 Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1250OS <<'\"';
1251break;
1252 }
1253 }
1254 }elseif (getOpaqueValue() ==nullptr &&getOffset() != 0) {
1255OS << ((isLoad() &&isStore()) ?" on "
1256 :isLoad() ?" from "
1257 :" into ")
1258 <<"unknown-address";
1259 }
1260MachineOperand::printOperandOffset(OS,getOffset());
1261if (!getSize().hasValue() ||
1262 (!getSize().isZero() &&
1263getAlign() !=getSize().getValue().getKnownMinValue()))
1264OS <<", align " <<getAlign().value();
1265if (getAlign() !=getBaseAlign())
1266OS <<", basealign " <<getBaseAlign().value();
1267auto AAInfo =getAAInfo();
1268if (AAInfo.TBAA) {
1269OS <<", !tbaa ";
1270 AAInfo.TBAA->printAsOperand(OS, MST);
1271 }
1272if (AAInfo.Scope) {
1273OS <<", !alias.scope ";
1274 AAInfo.Scope->printAsOperand(OS, MST);
1275 }
1276if (AAInfo.NoAlias) {
1277OS <<", !noalias ";
1278 AAInfo.NoAlias->printAsOperand(OS, MST);
1279 }
1280if (getRanges()) {
1281OS <<", !range ";
1282getRanges()->printAsOperand(OS, MST);
1283 }
1284// FIXME: Implement addrspace printing/parsing in MIR.
1285// For now, print this even though parsing it is not available in MIR.
1286if (unsigned AS =getAddrSpace())
1287OS <<", addrspace " << AS;
1288
1289OS <<')';
1290}
SubReg
unsigned SubReg
Definition:AArch64AdvSIMDScalarPass.cpp:104
MRI
unsigned const MachineRegisterInfo * MRI
Definition:AArch64AdvSIMDScalarPass.cpp:105
MBB
MachineBasicBlock & MBB
Definition:ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition:ARMSLSHardening.cpp:73
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition:Compiler.h:622
Constants.h
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Idx
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Definition:DeadArgumentElimination.cpp:353
Name
std::string Name
Definition:ELFObjHandler.cpp:77
Size
uint64_t Size
Definition:ELFObjHandler.cpp:81
Sym
Symbol * Sym
Definition:ELF_riscv.cpp:479
TII
const HexagonInstrInfo * TII
Definition:HexagonCopyToCombine.cpp:125
isDebug
static bool isDebug()
Definition:HexagonGenInsert.cpp:83
MI
IRTranslator LLVM IR MI
Definition:IRTranslator.cpp:112
IRPrintingPasses.h
This file contains an interface for creating legacy passes to print out IR in various granularities.
Instructions.h
isZero
static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)
Definition:Lint.cpp:557
Loads.h
MCDwarf.h
F
#define F(x, y, z)
Definition:MD5.cpp:55
I
#define I(x, y, z)
Definition:MD5.cpp:58
MIRFormatter.h
MachineFrameInfo.h
tryToGetTargetInfo
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
Definition:MachineInstr.cpp:75
getMFIfAvailable
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
Definition:MachineInstr.cpp:66
MachineJumpTableInfo.h
printSyncScope
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
Definition:MachineOperand.cpp:527
getMFIfAvailable
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
Definition:MachineOperand.cpp:43
getTargetIndexName
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
Definition:MachineOperand.cpp:464
printFrameIndex
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
Definition:MachineOperand.cpp:555
PrintRegMaskNumRegs
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
printIRBlockReference
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
Definition:MachineOperand.cpp:504
getTargetFlagName
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
Definition:MachineOperand.cpp:481
printCFIRegister
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
Definition:MachineOperand.cpp:491
getTargetMMOFlagName
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
Definition:MachineOperand.cpp:544
printCFI
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
Definition:MachineOperand.cpp:664
MachineOperand.h
MachineRegisterInfo.h
isUndef
static bool isUndef(const MachineInstr &MI)
Definition:MachineSSAContext.cpp:57
TRI
unsigned const TargetRegisterInfo * TRI
Definition:MachineSink.cpp:2029
ModuleSlotTracker.h
PseudoSourceValueManager.h
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition:RustDemangle.cpp:181
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
isDead
bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition:SPIRVInstructionSelector.cpp:420
OS
raw_pwrite_stream & OS
Definition:SampleProfWriter.cpp:51
StableHashing.h
StringExtras.h
This file contains some functions that are useful when dealing with strings.
TargetInstrInfo.h
TargetIntrinsicInfo.h
TargetRegisterInfo.h
llvm::APInt
Class for arbitrary precision integers.
Definition:APInt.h:78
llvm::AllocaInst
an instruction to allocate memory on the stack
Definition:Instructions.h:63
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition:ArrayRef.h:41
llvm::AtomicInfo
Definition:Atomic.h:16
llvm::BasicBlock
LLVM Basic Block Representation.
Definition:BasicBlock.h:61
llvm::BasicBlock::getParent
const Function * getParent() const
Return the enclosing method, or null if none.
Definition:BasicBlock.h:220
llvm::BlockAddress
The address of a basic block.
Definition:Constants.h:893
llvm::BlockAddress::getFunction
Function * getFunction() const
Definition:Constants.h:923
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition:InstrTypes.h:673
llvm::CmpInst::isIntPredicate
bool isIntPredicate() const
Definition:InstrTypes.h:781
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition:Constants.h:271
llvm::DWARFExpression::Operation
This class represents an Operation in the Expression.
Definition:DWARFExpression.h:32
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition:DataLayout.h:63
llvm::DataLayout::getAllocaAddrSpace
unsigned getAllocaAddrSpace() const
Definition:DataLayout.h:229
llvm::Function
Definition:Function.h:63
llvm::GlobalValue
Definition:GlobalValue.h:48
llvm::HexagonInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition:HexagonInstrInfo.cpp:2070
llvm::HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
Definition:HexagonInstrInfo.cpp:2076
llvm::HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
Definition:HexagonInstrInfo.cpp:2095
llvm::LLT
Definition:LowLevelType.h:39
llvm::LLT::isValid
constexpr bool isValid() const
Definition:LowLevelType.h:145
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition:LLVMContext.h:67
llvm::LLVMContext::getSyncScopeNames
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
Definition:LLVMContext.cpp:310
llvm::LocationSize
Definition:MemoryLocation.h:68
llvm::LocationSize::hasValue
bool hasValue() const
Definition:MemoryLocation.h:165
llvm::MCCFIInstruction
Definition:MCDwarf.h:499
llvm::MCCFIInstruction::getLabel
MCSymbol * getLabel() const
Definition:MCDwarf.h:711
llvm::MCCFIInstruction::getAddressSpace
unsigned getAddressSpace() const
Definition:MCDwarf.h:730
llvm::MCCFIInstruction::getRegister2
unsigned getRegister2() const
Definition:MCDwarf.h:725
llvm::MCCFIInstruction::getRegister
unsigned getRegister() const
Definition:MCDwarf.h:713
llvm::MCCFIInstruction::getOperation
OpType getOperation() const
Definition:MCDwarf.h:710
llvm::MCCFIInstruction::OpDefCfaRegister
@ OpDefCfaRegister
Definition:MCDwarf.h:507
llvm::MCCFIInstruction::OpWindowSave
@ OpWindowSave
Definition:MCDwarf.h:516
llvm::MCCFIInstruction::OpUndefined
@ OpUndefined
Definition:MCDwarf.h:514
llvm::MCCFIInstruction::OpLLVMDefAspaceCfa
@ OpLLVMDefAspaceCfa
Definition:MCDwarf.h:506
llvm::MCCFIInstruction::OpRegister
@ OpRegister
Definition:MCDwarf.h:515
llvm::MCCFIInstruction::OpRestoreState
@ OpRestoreState
Definition:MCDwarf.h:504
llvm::MCCFIInstruction::OpDefCfaOffset
@ OpDefCfaOffset
Definition:MCDwarf.h:508
llvm::MCCFIInstruction::OpNegateRAStateWithPC
@ OpNegateRAStateWithPC
Definition:MCDwarf.h:518
llvm::MCCFIInstruction::OpOffset
@ OpOffset
Definition:MCDwarf.h:505
llvm::MCCFIInstruction::OpRelOffset
@ OpRelOffset
Definition:MCDwarf.h:510
llvm::MCCFIInstruction::OpRememberState
@ OpRememberState
Definition:MCDwarf.h:503
llvm::MCCFIInstruction::OpNegateRAState
@ OpNegateRAState
Definition:MCDwarf.h:517
llvm::MCCFIInstruction::OpRestore
@ OpRestore
Definition:MCDwarf.h:513
llvm::MCCFIInstruction::OpSameValue
@ OpSameValue
Definition:MCDwarf.h:502
llvm::MCCFIInstruction::OpDefCfa
@ OpDefCfa
Definition:MCDwarf.h:509
llvm::MCCFIInstruction::OpAdjustCfaOffset
@ OpAdjustCfaOffset
Definition:MCDwarf.h:511
llvm::MCCFIInstruction::OpEscape
@ OpEscape
Definition:MCDwarf.h:512
llvm::MCCFIInstruction::getValues
StringRef getValues() const
Definition:MCDwarf.h:750
llvm::MCCFIInstruction::getOffset
int64_t getOffset() const
Definition:MCDwarf.h:735
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition:MCRegister.h:33
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition:MCSymbol.h:41
llvm::MDNode
Metadata node.
Definition:Metadata.h:1073
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition:MIRFormatter.h:32
llvm::MIRFormatter::printImm
virtual void printImm(raw_ostream &OS, const MachineInstr &MI, std::optional< unsigned > OpIdx, int64_t Imm) const
Implement target specific printing for machine operand immediate value, so that we can have more mean...
Definition:MIRFormatter.h:43
llvm::MIRFormatter::printCustomPseudoSourceValue
virtual void printCustomPseudoSourceValue(raw_ostream &OS, ModuleSlotTracker &MST, const PseudoSourceValue &PSV) const
Implement target specific printing of target custom pseudo source value.
Definition:MIRFormatter.h:60
llvm::MIRFormatter::printIRValue
static void printIRValue(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Helper functions to print IR value as MIR serialization format which will be useful for target specif...
Definition:MIRPrinter.cpp:1030
llvm::MachineBasicBlock
Definition:MachineBasicBlock.h:125
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition:MachineBasicBlock.h:311
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition:MachineFrameInfo.h:106
llvm::MachineFrameInfo::getObjectAllocation
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
Definition:MachineFrameInfo.h:512
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition:MachineFrameInfo.h:700
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition:MachineFrameInfo.h:409
llvm::MachineFunction
Definition:MachineFunction.h:267
llvm::MachineFunction::getPSVManager
PseudoSourceValueManager & getPSVManager() const
Definition:MachineFunction.h:698
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition:MachineFunction.h:733
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition:MachineFunction.cpp:309
llvm::MachineInstr
Representation of each machine instruction.
Definition:MachineInstr.h:71
llvm::MachineInstr::IgnoreBundle
@ IgnoreBundle
Definition:MachineInstr.h:895
llvm::MachineInstr::getOperandNo
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition:MachineInstr.h:783
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition:MachineMemOperand.h:129
llvm::MachineMemOperand::getSize
LocationSize getSize() const
Return the size in bytes of the memory reference.
Definition:MachineMemOperand.h:240
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition:MachineMemOperand.h:298
llvm::MachineMemOperand::getFailureOrdering
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
Definition:MachineMemOperand.h:285
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition:MachineMemOperand.h:217
llvm::MachineMemOperand::getMemoryType
LLT getMemoryType() const
Return the memory type of the memory reference.
Definition:MachineMemOperand.h:237
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition:MachineMemOperand.h:233
llvm::MachineMemOperand::print
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
Definition:MachineOperand.cpp:1150
llvm::MachineMemOperand::isNonTemporal
bool isNonTemporal() const
Definition:MachineMemOperand.h:299
llvm::MachineMemOperand::getRanges
const MDNode * getRanges() const
Return the range tag for the memory reference.
Definition:MachineMemOperand.h:269
llvm::MachineMemOperand::refineAlignment
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
Definition:MachineOperand.cpp:1128
llvm::MachineMemOperand::getSyncScopeID
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
Definition:MachineMemOperand.h:272
llvm::MachineMemOperand::getOpaqueValue
const void * getOpaqueValue() const
Definition:MachineMemOperand.h:221
llvm::MachineMemOperand::isInvariant
bool isInvariant() const
Definition:MachineMemOperand.h:301
llvm::MachineMemOperand::MachineMemOperand
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, LocationSize TS, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
Definition:MachineOperand.cpp:1114
llvm::MachineMemOperand::isLoad
bool isLoad() const
Definition:MachineMemOperand.h:296
llvm::MachineMemOperand::isStore
bool isStore() const
Definition:MachineMemOperand.h:297
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition:MachineMemOperand.h:132
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition:MachineMemOperand.h:153
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition:MachineMemOperand.h:152
llvm::MachineMemOperand::MOTargetFlag3
@ MOTargetFlag3
Definition:MachineMemOperand.h:154
llvm::MachineMemOperand::MOTargetFlag4
@ MOTargetFlag4
Definition:MachineMemOperand.h:155
llvm::MachineMemOperand::getSuccessOrdering
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Definition:MachineMemOperand.h:279
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition:MachineMemOperand.h:224
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition:MachineOperand.cpp:1146
llvm::MachineMemOperand::isDereferenceable
bool isDereferenceable() const
Definition:MachineMemOperand.h:300
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition:MachineMemOperand.h:266
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition:MachineMemOperand.h:213
llvm::MachineMemOperand::getBaseAlign
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
Definition:MachineMemOperand.h:263
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition:MachineMemOperand.h:231
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition:MachineOperand.h:48
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition:MachineOperand.h:490
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition:MachineOperand.h:374
llvm::MachineOperand::getInstrRefOpIndex
unsigned getInstrRefOpIndex() const
Definition:MachineOperand.h:602
llvm::MachineOperand::setInstrRefInstrIndex
void setInstrRefInstrIndex(unsigned InstrIdx)
Definition:MachineOperand.h:719
llvm::MachineOperand::getOperandNo
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
Definition:MachineOperand.cpp:56
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition:MachineOperand.h:582
llvm::MachineOperand::isUndef
bool isUndef() const
Definition:MachineOperand.h:404
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition:MachineOperand.cpp:83
llvm::MachineOperand::ChangeToFrameIndex
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
Definition:MachineOperand.cpp:233
llvm::MachineOperand::getRegLiveOut
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
Definition:MachineOperand.h:671
llvm::MachineOperand::setInstrRefOpIndex
void setInstrRefOpIndex(unsigned OpIdx)
Definition:MachineOperand.h:723
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition:MachineOperand.h:561
llvm::MachineOperand::getTargetIndexName
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
Definition:MachineOperand.cpp:476
llvm::MachineOperand::printStackObjectReference
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Definition:MachineOperand.cpp:634
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition:MachineOperand.cpp:569
llvm::MachineOperand::getImm
int64_t getImm() const
Definition:MachineOperand.h:556
llvm::MachineOperand::getInstrRefInstrIndex
unsigned getInstrRefInstrIndex() const
Definition:MachineOperand.h:597
llvm::MachineOperand::printTargetFlags
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
Definition:MachineOperand.cpp:578
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition:MachineOperand.h:389
llvm::MachineOperand::isKill
bool isKill() const
Definition:MachineOperand.h:399
llvm::MachineOperand::ChangeToFPImmediate
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
Definition:MachineOperand.cpp:172
llvm::MachineOperand::setIsRenamable
void setIsRenamable(bool Val=true)
Definition:MachineOperand.cpp:142
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition:MachineOperand.h:329
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition:MachineOperand.h:676
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition:MachineOperand.h:571
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition:MachineOperand.h:622
llvm::MachineOperand::ChangeToMCSymbol
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
Definition:MachineOperand.cpp:222
llvm::MachineOperand::ChangeToTargetIndex
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
Definition:MachineOperand.cpp:244
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition:MachineOperand.cpp:61
llvm::MachineOperand::isUse
bool isUse() const
Definition:MachineOperand.h:379
llvm::MachineOperand::dump
void dump() const
Definition:MachineOperand.cpp:1037
llvm::MachineOperand::isDef
bool isDef() const
Definition:MachineOperand.h:384
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition:MachineOperand.cpp:162
llvm::MachineOperand::ChangeToES
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Definition:MachineOperand.cpp:183
llvm::MachineOperand::ChangeToGA
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
Definition:MachineOperand.cpp:196
llvm::MachineOperand::getCFIIndex
unsigned getCFIIndex() const
Definition:MachineOperand.h:607
llvm::MachineOperand::isTied
bool isTied() const
Definition:MachineOperand.h:450
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition:MachineOperand.cpp:124
llvm::MachineOperand::ChangeToBA
void ChangeToBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
ChangeToBA - Replace this operand with a new block address operand.
Definition:MachineOperand.cpp:209
llvm::MachineOperand::printOperandOffset
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
Definition:MachineOperand.cpp:647
llvm::MachineOperand::ChangeToDbgInstrRef
void ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx, unsigned TargetFlags=0)
Replace this operand with an Instruction Reference.
Definition:MachineOperand.cpp:257
llvm::MachineOperand::ChangeToRegister
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Definition:MachineOperand.cpp:273
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition:MachineOperand.h:587
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition:MachineOperand.h:243
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition:MachineOperand.cpp:93
llvm::MachineOperand::getRegMaskSize
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
Definition:MachineOperand.h:666
llvm::MachineOperand::setOffset
void setOffset(int64_t Offset)
Definition:MachineOperand.h:700
llvm::MachineOperand::isDebug
bool isDebug() const
Definition:MachineOperand.h:455
llvm::MachineOperand::getIndex
int getIndex() const
Definition:MachineOperand.h:576
llvm::MachineOperand::isDead
bool isDead() const
Definition:MachineOperand.h:394
llvm::MachineOperand::printIRSlotNumber
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
Definition:MachineOperand.cpp:657
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition:MachineOperand.h:226
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition:MachineOperand.h:224
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition:MachineOperand.h:637
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition:MachineOperand.h:530
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition:MachineOperand.h:445
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition:MachineOperand.h:369
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition:MachineOperand.h:612
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition:MachineOperand.h:440
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition:MachineOperand.h:229
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition:MachineOperand.cpp:319
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition:MachineOperand.h:660
llvm::MachineOperand::setIndex
void setIndex(int Idx)
Definition:MachineOperand.h:708
llvm::MachineOperand::setIsDef
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Definition:MachineOperand.cpp:107
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition:MachineOperand.cpp:784
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition:MachineOperand.h:566
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition:MachineOperand.cpp:630
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition:MachineOperand.h:617
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition:MachineOperand.h:592
llvm::MachineOperand::MO_CFIIndex
@ MO_CFIIndex
MCCFIInstruction index.
Definition:MachineOperand.h:67
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition:MachineOperand.h:52
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition:MachineOperand.h:57
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition:MachineOperand.h:66
llvm::MachineOperand::MO_Predicate
@ MO_Predicate
Generic predicate for ISel.
Definition:MachineOperand.h:69
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition:MachineOperand.h:61
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition:MachineOperand.h:63
llvm::MachineOperand::MO_ShuffleMask
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
Definition:MachineOperand.h:70
llvm::MachineOperand::MO_CImmediate
@ MO_CImmediate
Immediate >64bit operand.
Definition:MachineOperand.h:53
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition:MachineOperand.h:62
llvm::MachineOperand::MO_DbgInstrRef
@ MO_DbgInstrRef
Integer indices referring to an instruction+operand.
Definition:MachineOperand.h:71
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition:MachineOperand.h:55
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition:MachineOperand.h:56
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition:MachineOperand.h:51
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition:MachineOperand.h:60
llvm::MachineOperand::MO_IntrinsicID
@ MO_IntrinsicID
Intrinsic ID for ISel.
Definition:MachineOperand.h:68
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition:MachineOperand.h:59
llvm::MachineOperand::MO_TargetIndex
@ MO_TargetIndex
Target-dependent index+offset operand.
Definition:MachineOperand.h:58
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition:MachineOperand.h:65
llvm::MachineOperand::MO_FPImmediate
@ MO_FPImmediate
Floating-point immediate operand.
Definition:MachineOperand.h:54
llvm::MachineOperand::MO_RegisterLiveOut
@ MO_RegisterLiveOut
Mask of live-out registers.
Definition:MachineOperand.h:64
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition:MachineOperand.h:629
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition:MachineRegisterInfo.h:51
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition:MachineRegisterInfo.cpp:312
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition:MachineRegisterInfo.cpp:273
llvm::Metadata::printAsOperand
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition:AsmWriter.cpp:5250
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition:ModuleSlotTracker.h:44
llvm::ModuleSlotTracker::getLocalSlot
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition:AsmWriter.cpp:918
llvm::ModuleSlotTracker::getCurrentFunction
const Function * getCurrentFunction() const
Definition:ModuleSlotTracker.h:81
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition:AsmWriter.cpp:904
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition:Module.h:65
llvm::PointerUnion::isNull
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition:PointerUnion.h:142
llvm::PseudoSourceValueManager::getJumpTable
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
Definition:PseudoSourceValue.cpp:120
llvm::PseudoSourceValueManager::getFixedStack
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.
Definition:PseudoSourceValue.cpp:125
llvm::PseudoSourceValueManager::getGOT
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like).
Definition:PseudoSourceValue.cpp:114
llvm::PseudoSourceValueManager::getStack
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function,...
Definition:PseudoSourceValue.cpp:110
llvm::PseudoSourceValueManager::getConstantPool
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
Definition:PseudoSourceValue.cpp:116
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition:PseudoSourceValue.h:31
llvm::PseudoSourceValue::GOT
@ GOT
Definition:PseudoSourceValue.h:35
llvm::PseudoSourceValue::Stack
@ Stack
Definition:PseudoSourceValue.h:34
llvm::PseudoSourceValue::GlobalValueCallEntry
@ GlobalValueCallEntry
Definition:PseudoSourceValue.h:39
llvm::PseudoSourceValue::JumpTable
@ JumpTable
Definition:PseudoSourceValue.h:36
llvm::PseudoSourceValue::ExternalSymbolCallEntry
@ ExternalSymbolCallEntry
Definition:PseudoSourceValue.h:40
llvm::PseudoSourceValue::ConstantPool
@ ConstantPool
Definition:PseudoSourceValue.h:37
llvm::PseudoSourceValue::FixedStack
@ FixedStack
Definition:PseudoSourceValue.h:38
llvm::Register
Wrapper class representing virtual and physical registers.
Definition:Register.h:19
llvm::Register::id
constexpr unsigned id() const
Definition:Register.h:103
llvm::Register::isPhysical
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition:Register.h:95
llvm::SmallVectorBase::empty
bool empty() const
Definition:SmallVector.h:81
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition:SmallVector.h:573
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition:StringRef.h:51
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition:StringRef.h:147
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition:StringRef.h:150
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition:TargetInstrInfo.h:112
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition:TargetIntrinsicInfo.h:29
llvm::TargetIntrinsicInfo::getName
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition:TargetRegisterInfo.h:235
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition:TargetSubtargetInfo.h:97
llvm::Value
LLVM Value Representation.
Definition:Value.h:74
llvm::Value::printAsOperand
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition:AsmWriter.cpp:5144
llvm::Value::hasName
bool hasName() const
Definition:Value.h:261
llvm::Value::getName
StringRef getName() const
Return a constant reference to the value's name.
Definition:Value.cpp:309
llvm::cl::opt
Definition:CommandLine.h:1423
llvm::hash_code
An opaque object representing a hash code.
Definition:Hashing.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition:raw_ostream.h:52
uint32_t
uint64_t
uint8_t
unsigned
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition:ErrorHandling.h:143
TargetMachine.h
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition:CallingConv.h:34
llvm::Intrinsic::getBaseName
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
Definition:Intrinsics.cpp:42
llvm::SyncScope::System
@ System
Synchronized with respect to all concurrently executing threads.
Definition:LLVMContext.h:57
llvm::cl::Hidden
@ Hidden
Definition:CommandLine.h:137
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition:CommandLine.h:443
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:AddressRanges.h:18
llvm::Offset
@ Offset
Definition:DWP.cpp:480
llvm::hash_value
hash_code hash_value(const FixedPointSemantics &Val)
Definition:APFixedPoint.h:136
llvm::isDereferenceableAndAlignedPointer
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition:Loads.cpp:217
llvm::printJumpTableEntryReference
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
Definition:MachineFunction.cpp:1437
llvm::toIRString
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
Definition:AtomicOrdering.h:82
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition:Debug.cpp:163
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition:TargetRegisterInfo.cpp:171
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition:Format.h:125
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition:AtomicOrdering.h:56
llvm::AtomicOrdering::NotAtomic
@ NotAtomic
llvm::IRMemLocation::Other
@ Other
Any other memory.
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition:STLExtras.h:1766
llvm::commonAlignment
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition:Alignment.h:212
llvm::hash_combine
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition:Hashing.h:590
llvm::stable_hash_combine
stable_hash stable_hash_combine(ArrayRef< stable_hash > Buffer)
Definition:StableHashing.h:30
llvm::printLLVMNameWithoutPrefix
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition:AsmWriter.cpp:382
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition:TargetRegisterInfo.cpp:107
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition:MachineBasicBlock.cpp:122
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition:Metadata.h:764
llvm::AAMDNodes::Scope
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition:Metadata.h:787
llvm::AAMDNodes::TBAA
MDNode * TBAA
The tag for type-based alias analysis.
Definition:Metadata.h:781
llvm::AAMDNodes::NoAlias
MDNode * NoAlias
The tag specifying the noalias scope.
Definition:Metadata.h:790
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition:Alignment.h:39
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition:Alignment.h:85
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition:MachineMemOperand.h:41
llvm::MachinePointerInfo::getJumpTable
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Definition:MachineOperand.cpp:1077
llvm::MachinePointerInfo::isDereferenceable
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
Definition:MachineOperand.cpp:1050
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition:MachineOperand.cpp:1046
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition:MachineOperand.cpp:1085
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition:MachineMemOperand.h:46
llvm::MachinePointerInfo::AddrSpace
unsigned AddrSpace
Definition:MachineMemOperand.h:48
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition:MachineMemOperand.h:43
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
Definition:MachineOperand.cpp:1066
llvm::MachinePointerInfo::getUnknownStack
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
Definition:MachineOperand.cpp:1090
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition:MachineOperand.cpp:1081
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition:MachineOperand.cpp:1072
llvm::cl::desc
Definition:CommandLine.h:409
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