1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7//===----------------------------------------------------------------------===// 9// Methods common to all machine instructions. 11//===----------------------------------------------------------------------===// 73// Try to crawl up to the machine function and get TRI and IntrinsicInfo from 82TRI = MF->getSubtarget().getRegisterInfo();
83MRI = &MF->getRegInfo();
84 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
85TII = MF->getSubtarget().getInstrInfo();
96/// MachineInstr ctor - This constructor creates a MachineInstr and adds the 97/// implicit operands. It reserves space for the number of operands specified by 101 : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),
102 DbgLoc(
std::
move(
DL)), DebugInstrNum(0), Opcode(TID.Opcode) {
105// Reserve space for the expected number of operands. 108 CapOperands = OperandCapacity::get(NumOps);
116/// MachineInstr ctor - Copies MachineInstr arg exactly. 117/// Does not copy the number from debug instruction numbering, to preserve 120 : MCID(&
MI.
getDesc()), NumOperands(0),
Flags(0), AsmPrinterFlags(0),
125 CapOperands = OperandCapacity::get(
MI.getNumOperands());
132// Replicate ties between the operands, which addOperand was not 133// able to do reliably. 137 NewMO.TiedTo = OrigMO.TiedTo;
140// Copy all the sensible flags. 155/// getRegInfo - If this instruction is embedded into a MachineFunction, 156/// return the MachineRegisterInfo object for the current function, otherwise 173MRI.removeRegOperandFromUseList(&MO);
179MRI.addRegOperandToUseList(&MO);
184assert(
MBB &&
"Use MachineInstrBuilder to add operands to dangling instrs");
186assert(MF &&
"Use MachineInstrBuilder to add operands to dangling instrs");
190/// Move NumOps MachineOperands from Src to Dst, with support for overlapping 191/// ranges. If MRI is non-null also update use-def chains. 195returnMRI->moveOperands(Dst, Src, NumOps);
196// MachineOperand is a trivially copyable type so we can just use memmove. 197assert(Dst && Src &&
"Unknown operands");
201/// addOperand - Add the specified operand to the instruction. If it is an 202/// implicit operand, it is added to the end of the operand list. If it is 203/// an explicit operand it is added at the end of the explicit operand list 204/// (before the first implicit operand). 206assert(isUInt<LLVM_MI_NUMOPERANDS_BITS>(NumOperands + 1) &&
207"Cannot add more operands.");
208assert(MCID &&
"Cannot add operands before providing an instr descriptor");
210// Check if we're adding one of our existing operands. 211if (&
Op >= Operands && &
Op < Operands + NumOperands) {
212// This is unusual: MI->addOperand(MI->getOperand(i)). 213// If adding Op requires reallocating or moving existing operands around, 214// the Op reference could go stale. Support it by copying Op. 219// Find the insert location for the new operand. Implicit registers go at 220// the end, everything else goes before the implicit regs. 222// FIXME: Allow mixed explicit and implicit operands on inline asm. 223// InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as 224// implicit-defs, but they must not be moved around. See the FIXME in 227bool isImpReg =
Op.isReg() &&
Op.isImplicit();
229while (OpNo && Operands[OpNo-1].
isReg() && Operands[OpNo-1].isImplicit()) {
231assert(!Operands[OpNo].isTied() &&
"Cannot move tied operands");
235// OpNo now points as the desired insertion point. Unless this is a variadic 236// instruction, only implicit regs are allowed beyond MCID->getNumOperands(). 237// RegMask operands go between the explicit and implicit operands. 240// Determine if the Operands array needs to be reallocated. 241// Save the old capacity and operand array. 242 OperandCapacity OldCap = CapOperands;
245 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
247// Move the operands before the insertion point. 252// Move the operands following the insertion point. 253if (OpNo != NumOperands)
254moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
258// Deallocate the old operand array. 259if (OldOperands != Operands && OldOperands)
262// Copy Op into place. It still needs to be inserted into the MRI use lists. 264 NewMO->ParentMI =
this;
266// When adding a register operand, tell MRI about it. 268// Ensure isOnRegUseList() returns false, regardless of Op's status. 269 NewMO->Contents.Reg.Prev =
nullptr;
270// Ignore existing ties. This is not a property that can be copied. 272// Add the new operand to MRI, but only for instructions in an MBB. 274MRI->addRegOperandToUseList(NewMO);
275// The MCID operand information isn't accurate until we start adding 276// explicit operands. The implicit operands are added first, then the 277// explicits are inserted before them. 279// Tie uses to defs as indicated in MCInstrDesc. 285// If the register operand is flagged as early, mark the operand as such. 289// Ensure debug instructions set debug flag on register uses. 300// Moving tied operands would break the ties. 302if (Operands[i].
isReg())
303assert(!Operands[i].isTied() &&
"Cannot move tied operands");
308MRI->removeRegOperandFromUseList(Operands + OpNo);
310// Don't call the MachineOperand destructor. A lot of this code depends on 311// MachineOperand having a trivial destructor anyway, and adding a call here 312// wouldn't make it 'destructor-correct'. 314if (
unsignedN = NumOperands - 1 - OpNo)
325bool HasPreInstrSymbol = PreInstrSymbol !=
nullptr;
326bool HasPostInstrSymbol = PostInstrSymbol !=
nullptr;
327bool HasHeapAllocMarker = HeapAllocMarker !=
nullptr;
328bool HasPCSections = PCSections !=
nullptr;
329bool HasCFIType = CFIType != 0;
330bool HasMMRAs = MMRAs !=
nullptr;
331int NumPointers = MMOs.
size() + HasPreInstrSymbol + HasPostInstrSymbol +
332 HasHeapAllocMarker + HasPCSections + HasCFIType + HasMMRAs;
334// Drop all extra info if there is none. 335if (NumPointers <= 0) {
340// If more than one pointer, then store out of line. Store heap alloc markers 341// out of line because PointerSumType cannot hold more than 4 tag types with 343// FIXME: Maybe we should make the symbols in the extra info mutable? 344elseif (NumPointers > 1 || HasMMRAs || HasHeapAllocMarker || HasPCSections ||
346 Info.set<EIIK_OutOfLine>(
348 HeapAllocMarker, PCSections, CFIType, MMRAs));
352// Otherwise store the single pointer inline. 353if (HasPreInstrSymbol)
354 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
355elseif (HasPostInstrSymbol)
356 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
358 Info.set<EIIK_MMO>(MMOs[0]);
392// Nothing to do for a self-clone! 396"Invalid machine functions when cloning memory refrences!");
397// See if we can just steal the extra info already allocated for the 398// instruction. We can do this whenever the pre- and post-instruction symbols 399// are the same (including null). 404MI.getMMRAMetadata()) {
409// Otherwise, fall back on a copy-based clone. 413/// Check to see if the MMOs pointed to by the two MemRefs arrays are 417if (
LHS.size() !=
RHS.size())
422return std::equal(LHSPointees.begin(), LHSPointees.end(),
423 RHSPointees.begin());
428// Try handling easy numbers of MIs with simpler mechanisms. 433if (MIs.
size() == 1) {
437// Because an empty memoperands list provides *no* information and must be 438// handled conservatively (assuming the instruction can do anything), the only 439// way to merge with it is to drop all other memoperands. 445// Handle the general case. 447// Start with the first instruction. 449"Invalid machine functions when cloning memory references!");
451// Now walk all the other instructions and accumulate any different MMOs. 454"Invalid machine functions when cloning memory references!");
456// Skip MIs with identical operands to the first. This is a somewhat 457// arbitrary hack but will catch common cases without being quadratic. 458// TODO: We could fully implement merge semantics here if needed. 462// Because an empty memoperands list provides *no* information and must be 463// handled conservatively (assuming the instruction can do anything), the 464// only way to merge with it is to drop all other memoperands. 465if (
MI.memoperands_empty()) {
470// Otherwise accumulate these into our temporary buffer of the merged state. 471 MergedMMOs.
append(
MI.memoperands_begin(),
MI.memoperands_end());
478// Do nothing if old and new symbols are the same. 482// If there was only one symbol and we're removing it, just clear info. 483if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
494// Do nothing if old and new symbols are the same. 498// If there was only one symbol and we're removing it, just clear info. 499if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
510// Do nothing if old and new symbols are the same. 519// Do nothing if old and new symbols are the same. 529// Do nothing if old and new types are the same. 538// Do nothing if old and new symbols are the same. 549// Nothing to do for a self-clone! 553"Invalid machine functions when cloning instruction symbols!");
563// For now, the just return the union of the flags. If the flags get more 564// complicated over time, we might need more logic here. 570// Copy the wrapping flags. 572 dyn_cast<OverflowingBinaryOperator>(&
I)) {
573if (OB->hasNoSignedWrap())
575if (OB->hasNoUnsignedWrap())
577 }
elseif (
constTruncInst *TI = dyn_cast<TruncInst>(&
I)) {
578if (TI->hasNoSignedWrap())
580if (TI->hasNoUnsignedWrap())
583if (
GEP->hasNoUnsignedSignedWrap())
585if (
GEP->hasNoUnsignedWrap())
589// Copy the nonneg flag. 593// Copy the disjoint flag. 595 dyn_cast<PossiblyDisjointInst>(&
I)) {
600// Copy the samesign flag. 601if (
constICmpInst *ICmp = dyn_cast<ICmpInst>(&
I))
602if (ICmp->hasSameSign())
605// Copy the exact flag. 610// Copy the fast-math flags. 617if (Flags.noSignedZeros())
619if (Flags.allowReciprocal())
621if (Flags.allowContract())
623if (Flags.approxFunc())
625if (Flags.allowReassoc())
629if (
I.getMetadata(LLVMContext::MD_unpredictable))
639bool MachineInstr::hasPropertyInBundle(
uint64_t Mask, QueryType
Type)
const{
642if (MII->getDesc().getFlags() & Mask) {
649// This was the last instruction in the bundle. 650if (!MII->isBundledWithSucc())
657// If opcodes or number of operands are not the same then the two 658// instructions are obviously not identical. 664// We have passed the test above that both instructions have the same 665// opcode, so we know that both instructions are bundles here. Let's compare 666// MIs inside the bundle. 667assert(
Other.isBundle() &&
"Expected that both instructions are bundles.");
670// Loop until we analysed the last intruction inside at least one of the 672while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
675if (!I1->isIdenticalTo(*I2,
Check))
678// If we've reached the end of just one of the two bundles, but not both, 679// the instructions are not identical. 680if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
684// Check operands to make sure they match. 694// Clients may or may not want to ignore defs when testing for equality. 695// For example, machine CSE pass only cares about finding common 696// subexpressions, so it's safe to ignore virtual register defs. 717// If DebugLoc does not match then two debug instructions are not identical. 722// If pre- or post-instruction symbols do not match then the two instructions 727// Call instructions with different CFI types are not identical. 748Other.getDebugExpression(),
Other.isIndirectDebugValue()))
781case TargetOpcode::PATCHPOINT:
782case TargetOpcode::STACKMAP:
783case TargetOpcode::STATEPOINT:
784case TargetOpcode::FENTRY_CALL:
803// The operands must always be in the following order: 804// - explicit reg defs, 805// - other explicit operands (reg uses, immediates, etc.), 806// - implicit reg defs 807// - implicit reg uses 834assert(!Pred->isBundledWithSucc() &&
"Inconsistent bundle flags");
843assert(!Succ->isBundledWithPred() &&
"Inconsistent bundle flags");
852assert(Pred->isBundledWithSucc() &&
"Inconsistent bundle flags");
861assert(Succ->isBundledWithPred() &&
"Inconsistent bundle flags");
881unsigned *GroupNo)
const{
885// Ignore queries about the initial operands. 894// If we reach the implicit register operands, stop looking. 898 NumOps = 1 +
F.getNumOperandRegisters();
899if (i + NumOps > OpIdx) {
911return cast<DILabel>(
getOperand(0).getMetadata());
955assert(
getMF() &&
"Can't have an MF reference here!");
958// Most opcodes have fixed constraints in their MCInstrDesc. 965// For tied uses on inline asm, get the constraint from the def. 970// Inline asm stores register class constraints in the flag word. 977if ((
F.isRegUseKind() ||
F.isRegDefKind() ||
F.isRegDefEarlyClobberKind()) &&
978F.hasRegClassConstraint(RCID))
979returnTRI->getRegClass(RCID);
981// Assume that all registers in a memory operand are pointers. 983returnTRI->getPointerRegClass(MF);
991// Check every operands inside the bundle if we have 996 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
997 OpndIt.getOperandNo(), Reg, CurRC,
TII,
TRI);
999// Otherwise, just check the current operands. 1000for (
unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
1001 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC,
TII,
TRI);
1008assert(CurRC &&
"Invalid initial register class");
1009// Check if Reg is constrained by some of its use/def from MI. 1013// If yes, accumulate the constraints through the operand. 1023"Cannot get register constraints for non-register operand");
1024assert(CurRC &&
"Invalid initial register class");
1027 CurRC =
TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
1029 CurRC =
TRI->getSubClassWithSubReg(CurRC, SubIdx);
1031 CurRC =
TRI->getCommonSubClass(CurRC, OpRC);
1035/// Return the number of instructions inside the MI bundle, not counting the 1036/// header instruction. 1040while (
I->isBundledWithSucc()) {
1047/// Returns true if the MachineInstr has an implicit-use operand of exactly 1048/// the given register (not considering sub/super-registers). 1057/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 1058/// the specific register or -1 if it is not found. It further tightens 1059/// the search criteria to a use that kills the register if isKill is true. 1070if (MOReg == Reg || (
TRI && Reg && MOReg &&
TRI->regsOverlap(MOReg, Reg)))
1077/// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 1078/// indicating if this instruction reads or writes Reg. This also considers 1083bool PartDef =
false;
// Partial redefine. 1084bool FullDef =
false;
// Full define. 1096// A partial def undef doesn't count as reading the register. 1101// A partial redefine uses Reg unless there is also a full define. 1102return std::make_pair(
Use || (PartDef && !FullDef), PartDef || FullDef);
1105/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 1106/// the specified register or -1 if it is not found. If isDead is true, defs 1107/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 1108/// also checks if there is a def of a super-register. 1111boolisDead,
bool Overlap)
const{
1112bool isPhys = Reg.isPhysical();
1115// Accept regmask operands when Overlap is set. 1116// Ignore them when looking for a specific def operand (Overlap == false). 1122bool Found = (MOReg == Reg);
1125 Found =
TRI->regsOverlap(MOReg, Reg);
1127 Found =
TRI->isSubRegister(MOReg, Reg);
1135/// findFirstPredOperandIdx() - Find the index of the first operand in the 1136/// operand list that is used to represent the predicate. It returns -1 if 1139// Don't call MCID.findFirstPredOperandIdx() because this variant 1140// is sometimes called on an instruction that's not yet complete, and 1141// so the number of operands is less than the MCID indicates. In 1142// particular, the PTX target does this. 1146if (MCID.
operands()[i].isPredicate())
1153// MachineOperand::TiedTo is 4 bits wide. 1156/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. 1158/// Use and def operands can be tied together, indicated by a non-zero TiedTo 1159/// field. TiedTo can have these values: 1161/// 0: Operand is not tied to anything. 1162/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1). 1163/// TiedMax: Tied to an operand >= TiedMax-1. 1165/// The tied def must be one of the first TiedMax operands on a normal 1166/// instruction. INLINEASM instructions allow more tied defs. 1171assert(DefMO.
isDef() &&
"DefIdx must be a def operand");
1172assert(UseMO.
isUse() &&
"UseIdx must be a use operand");
1173assert(!DefMO.
isTied() &&
"Def is already tied to another use");
1174assert(!UseMO.
isTied() &&
"Use is already tied to another def");
1177 UseMO.TiedTo = DefIdx + 1;
1179// Inline asm can use the group descriptors to find tied operands, 1180// statepoint tied operands are trivial to match (1-1 reg def with reg use), 1181// but on normal instruction, the tied def must be within the first TiedMax 1184"DefIdx out of range");
1188// UseIdx can be out of range, we'll search for it in findTiedOperandIdx(). 1189 DefMO.TiedTo = std::min(UseIdx + 1,
TiedMax);
1192/// Given the index of a tied register operand, find the operand it is tied to. 1193/// Defs are tied to uses and vice versa. Returns the index of the tied operand 1194/// which must exist. 1199// Normally TiedTo is in range. 1201return MO.TiedTo - 1;
1203// Uses on normal instructions can be out of range. 1205// Normal tied defs must be in the 0..TiedMax-1 range. 1208// MO is a def. Search for the tied use. 1211if (UseMO.
isReg() && UseMO.
isUse() && UseMO.TiedTo == OpIdx + 1)
1217if (
getOpcode() == TargetOpcode::STATEPOINT) {
1218// In STATEPOINT defs correspond 1-1 to GC pointer operands passed 1222assert(CurUseIdx != -1U &&
"only gc pointer statepoint operands can be tied");
1224for (
unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1227if (OpIdx == CurDefIdx)
1229if (OpIdx == CurUseIdx)
1236// Now deal with inline asm by parsing the operand group descriptor flags. 1237// Find the beginning of each operand group. 1239unsigned OpIdxGroup = ~0u;
1244assert(FlagMO.
isImm() &&
"Invalid tied operand on inline asm");
1245unsigned CurGroup = GroupIdx.
size();
1248 NumOps = 1 +
F.getNumOperandRegisters();
1249// OpIdx belongs to this operand group. 1250if (OpIdx > i && OpIdx < i + NumOps)
1251 OpIdxGroup = CurGroup;
1253if (!
F.isUseOperandTiedToDef(TiedGroup))
1255// Operands in this group are tied to operands in TiedGroup which must be 1256// earlier. Find the number of operands between the two groups. 1257unsigned Delta = i - GroupIdx[TiedGroup];
1259// OpIdx is a use tied to TiedGroup. 1260if (OpIdxGroup == CurGroup)
1261return OpIdx - Delta;
1263// OpIdx is a def tied to this use group. 1264if (OpIdxGroup == TiedGroup)
1265return OpIdx + Delta;
1270/// clearKillInfo - Clears kill flags on all operands. 1284 ToReg = RegInfo.
getSubReg(ToReg, SubIdx);
1299/// isSafeToMove - Return true if it is safe to move this instruction. If 1300/// SawStore is set to true, it means that there is a store (or call) between 1301/// the instruction's location and its intended destination. 1303// Ignore stuff that we obviously can't move. 1305// Treat volatile loads as stores. This is not strictly necessary for 1306// volatiles, but it is required for atomic loads. It is not allowed to move 1307// a load across an atomic load with Ordering > Monotonic. 1319// See if this instruction does a load. If so, we have to guarantee that the 1320// loaded value doesn't change between the load and the its intended 1321// destination. The check for isInvariantLoad gives the target the chance to 1322// classify the load as always returning a constant, e.g. a constant pool 1325// Otherwise, this is a real load. If there is a store between the load and 1326// end of block, we can't move it. 1333// Don't delete frame allocation labels. 1334// FIXME: Why is LOCAL_ESCAPE not considered in MachineInstr::isLabel? 1335if (
getOpcode() == TargetOpcode::LOCAL_ESCAPE)
1338// Don't delete FAKE_USE. 1339// FIXME: Why is FAKE_USE not considered in MachineInstr::isPosition? 1343// LIFETIME markers should be preserved. 1344// FIXME: Why are LIFETIME markers not considered in MachineInstr::isPosition? 1348// If we can move an instruction, we can remove it. Otherwise, it has 1349// a side-effect of some sort. 1350bool SawStore =
false;
1356// Instructions without side-effects are dead iff they only define dead regs. 1357// This function is hot and this loop returns early in the common case, 1358// so only perform additional checks before this if absolutely necessary. 1361if (Reg.isPhysical()) {
1362// Don't delete live physreg defs, or any reserved register defs. 1370// This def has a non-debug use. Don't delete the instruction! 1376// Technically speaking inline asm without side effects and no defs can still 1377// be deleted. But there is so much bad inline asm code out there, we should 1382// FIXME: See issue #105950 for why LIFETIME markers are considered dead here. 1386// If there are no defs with uses, then we call the instruction dead so long 1387// as we do not suspect it may have sideeffects. 1395// The following interface to AA is fashioned after DAGCombiner::isAlias and 1396// operates with MachineMemOperand offset with some important assumptions: 1397// - LLVM fundamentally assumes flat address spaces. 1398// - MachineOperand offset can *only* result from legalization and cannot 1399// affect queries other than the trivial case of overlap checking. 1400// - These offsets never wrap and never step outside of allocated objects. 1401// - There should never be any negative offsets here. 1403// FIXME: Modify API to hide this math from "user" 1404// Even before we go to AA we can reason locally about some memory objects. It 1405// can save compile time, and possibly catch some corner cases not currently 1410 int64_t MinOffset = std::min(OffsetA, OffsetB);
1414bool KnownWidthA = WidthA.
hasValue();
1415bool KnownWidthB = WidthB.
hasValue();
1420bool SameVal = (ValA && ValB && (ValA == ValB));
1424if (PSVa && ValB && !PSVa->
mayAlias(&MFI))
1426if (PSVb && ValA && !PSVb->
mayAlias(&MFI))
1428if (PSVa && PSVb && (PSVa == PSVb))
1432if (SameVal && BothMMONonScalable) {
1433if (!KnownWidthA || !KnownWidthB)
1435 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1436 int64_t LowWidth = (MinOffset == OffsetA)
1439return (MinOffset + LowWidth > MaxOffset);
1448assert((OffsetA >= 0) &&
"Negative MachineMemOperand offset");
1449assert((OffsetB >= 0) &&
"Negative MachineMemOperand offset");
1451// If Scalable Location Size has non-zero offset, Width + Offset does not work 1482// Exclude call instruction which may alter the memory but can not be handled 1487// If neither instruction stores to memory, they can't alias in any 1488// meaningful way, even if they read from the same address. 1492// Both instructions must be memory operations to be able to alias. 1496// Let the target decide if memory accesses cannot possibly overlap. 1500// Memory operations without memory operands may access anything. Be 1501// conservative and assume `MayAlias`. 1505// Skip if there are too many memory operands. 1507if (NumChecks >
TII->getMemOperandAACheckLimit())
1510// Check each pair of memory operands from both instructions, which can't 1511// alias only if all pairs won't alias. 1513for (
auto *MMOb :
Other.memoperands())
1529/// hasOrderedMemoryRef - Return true if this instruction may have an ordered 1530/// or volatile memory reference, or if the information describing the memory 1531/// reference is not available. Return false if it is known to have no ordered 1532/// memory references. 1534// An instruction known never to access memory won't have a volatile access. 1541// Otherwise, if the instruction has no memory reference information, 1542// conservatively assume it wasn't preserved. 1546// Check if any of our memory operands are ordered. 1552/// isDereferenceableInvariantLoad - Return true if this instruction will never 1553/// trap and is loading from a location whose value is invariant across a run of 1556// If the instruction doesn't load at all, it isn't an invariant load. 1560// If the instruction has lost its memoperands, conservatively assume that 1561// it may not be an invariant load. 1568if (!MMO->isUnordered())
1569// If the memory operand has ordering side effects, we can't move the 1570// instruction. Such an instruction is technically an invariant load, 1571// but the caller code would need updated to expect that. 1573if (MMO->isStore())
returnfalse;
1574if (MMO->isInvariant() && MMO->isDereferenceable())
1577// A load from a constant PseudoSourceValue is invariant. 1579if (PSV->isConstant(&MFI))
1583// Otherwise assume conservatively. 1587// Everything checks out. 1595"It's illegal to have a PHI without source operands");
1621/// allDefsAreDead - Return true if all the defs of this instruction are dead. 1643/// copyImplicitOps - Copy implicit register operands from specified 1644/// instruction to this instruction. 1655if (MCID.
Opcode == TargetOpcode::STATEPOINT)
1659if (!Operand.isReg() || Operand.isDef())
1660// Ignore the defined registers as MCID marks only the uses as tied. 1664if (ExpectedTiedIdx != TiedIdx)
1677returnMRI.getType(
Op.getReg());
1680if (!OpInfo.isGenericType())
1681returnMRI.getType(
Op.getReg());
1683if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1686LLT TypeToPrint =
MRI.getType(
Op.getReg());
1687// Don't mark the type index printed if it wasn't actually printed: maybe 1688// another operand with the same type index has an actual type attached: 1690 PrintedTypes.
set(OpInfo.getGenericTypeIndex());
1694#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 1703if (
Depth >= MaxDepth)
1705if (!AlreadySeenInstrs.
insert(
this).second)
1707// PadToColumn always inserts at least one space. 1708// Don't mess up the alignment if we don't want any space. 1716if (Reg.isPhysical())
1721 NewMI->dumprImpl(
MRI,
Depth + 1, MaxDepth, AlreadySeenInstrs);
1726unsigned MaxDepth)
const{
1728 dumprImpl(
MRI, 0, MaxDepth, AlreadySeenInstrs);
1733bool SkipDebugLoc,
bool AddNewLine,
1747print(
OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine,
TII);
1751bool IsStandalone,
bool SkipOpers,
bool SkipDebugLoc,
1753// We can be a bit tidier if we know the MachineFunction. 1764auto getTiedOperandIdx = [&](
unsigned OpIdx) {
1765if (!ShouldPrintRegisterTies)
1772unsigned StartOp = 0;
1775// Print explicitly defined operands on the left of an assignment syntax. 1776while (StartOp < e) {
1785unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1786 MO.
print(
OS, MST, TypeToPrint, StartOp,
/*PrintDef=*/false, IsStandalone,
1787 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1797OS <<
"frame-destroy ";
1829// Print the opcode name. 1838// Print the rest of the operands. 1840unsigned AsmDescOp = ~0u;
1841unsigned AsmOpCount = 0;
1848unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1849getOperand(OpIdx).
print(
OS, MST, TypeToPrint, OpIdx,
/*PrintDef=*/true, IsStandalone,
1850 ShouldPrintRegisterTies, TiedOperandIdx,
TRI,
1853// Print HasSideEffects, MayLoad, MayStore, IsAlignStack 1856OS <<
" [sideeffect]";
1862OS <<
" [isconvergent]";
1864OS <<
" [alignstack]";
1866OS <<
" [attdialect]";
1868OS <<
" [inteldialect]";
1877if (FirstOp) FirstOp =
false;
elseOS <<
",";
1881// Pretty print DBG_VALUE* instructions. 1882auto *DIV = dyn_cast<DILocalVariable>(MO.
getMetadata());
1883if (DIV && !DIV->getName().empty())
1884OS <<
"!\"" << DIV->getName() <<
'\"';
1887unsigned TiedOperandIdx = getTiedOperandIdx(i);
1888 MO.
print(
OS, MST, TypeToPrint, i,
/*PrintDef=*/true, IsStandalone,
1889 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1892// Pretty print DBG_LABEL instructions. 1894if (DIL && !DIL->getName().empty())
1895OS <<
"\"" << DIL->getName() <<
'\"';
1898unsigned TiedOperandIdx = getTiedOperandIdx(i);
1899 MO.
print(
OS, MST, TypeToPrint, i,
/*PrintDef=*/true, IsStandalone,
1900 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1902 }
elseif (i == AsmDescOp && MO.
isImm()) {
1903// Pretty print the inline asm operand descriptor. 1904OS <<
'$' << AsmOpCount++;
1905unsigned Flag = MO.
getImm();
1908OS <<
F.getKindName();
1911if (!
F.isImmKind() && !
F.isMemKind() &&
F.hasRegClassConstraint(RCID)) {
1913OS <<
':' <<
TRI->getRegClassName(
TRI->getRegClass(RCID));
1924if (
F.isUseOperandTiedToDef(TiedTo))
1925OS <<
" tiedto:$" << TiedTo;
1927if ((
F.isRegDefKind() ||
F.isRegDefEarlyClobberKind() ||
1929F.getRegMayBeFolded()) {
1935// Compute the index of the next operand descriptor. 1936 AsmDescOp += 1 +
F.getNumOperandRegisters();
1939unsigned TiedOperandIdx = getTiedOperandIdx(i);
1943 MO.
print(
OS, MST, TypeToPrint, i,
/*PrintDef=*/true, IsStandalone,
1944 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1948// Print any optional symbols attached to this instruction as-if they were 1955OS <<
" pre-instr-symbol ";
1963OS <<
" post-instr-symbol ";
1971OS <<
" heap-alloc-marker ";
1988 MMRA->printAsOperand(
OS, MST);
1993OS <<
" cfi-type " << CFIType;
1999OS <<
" debug-instr-number " << DebugInstrNum;
2006OS <<
" debug-location ";
2014 std::unique_ptr<LLVMContext> CtxPtr;
2020 CtxPtr = std::make_unique<LLVMContext>();
2021 Context = CtxPtr.get();
2025bool NeedComma =
false;
2037bool HaveSemi =
false;
2039// Print debug location information. 2049// Print extra comments for DEBUG_VALUE and friends if they are well-formed. 2059OS <<
" line no:" << DV->getLine();
2072bool AddIfNotFound) {
2074bool hasAliases = isPhysReg &&
2083// DEBUG_VALUE nodes do not contribute to code generation and should 2084// always be ignored. Failure to do so may result in trying to modify 2085// KILL flags on DEBUG_VALUE nodes. 2093if (Reg == IncomingReg) {
2096// The register is already marked kill. 2099// Two-address uses of physregs must not be marked kill. 2104 }
elseif (hasAliases && MO.
isKill() && Reg.isPhysical()) {
2105// A super-register kill already exists. 2113// Trim unneeded kill operands. 2114while (!DeadOps.
empty()) {
2115unsigned OpIdx = DeadOps.
back();
2124// If not found, this means an alias of one of the operands is killed. Add a 2125// new implicit operand if required. 2126if (!Found && AddIfNotFound) {
2138if (!Reg.isPhysical())
2144if ((RegInfo && RegInfo->
regsOverlap(Reg, OpReg)) || Reg == OpReg)
2151bool AddIfNotFound) {
2152bool isPhysReg = Reg.isPhysical();
2153bool hasAliases = isPhysReg &&
2169// There exists a super-register that's marked dead. 2177// Trim unneeded dead operands. 2178while (!DeadOps.
empty()) {
2179unsigned OpIdx = DeadOps.
back();
2188// If not found, this means an alias of one of the operands is dead. Add a 2189// new implicit operand if required. 2190if (Found || !AddIfNotFound)
2215if (Reg.isPhysical()) {
2232bool HasRegMask =
false;
2240if (!Reg.isPhysical())
2242// If there are no uses, including partial uses, the def is dead. 2248// This is a call with a register mask operand. 2249// Mask clobbers are always dead, so add defs for the non-dead defines. 2251for (
constRegister &UsedReg : UsedRegs)
2257// Build up a buffer of hash code components. 2259 HashComponents.
reserve(
MI->getNumOperands() + 1);
2263continue;
// Skip virtual register defs. 2271// Find the source location cookie. 2272constMDNode *LocMD =
nullptr;
2277if (mdconst::hasa<ConstantInt>(LocMD->
getOperand(0)))
2290 ? mdconst::extract<ConstantInt>(LocMD->
getOperand(0))->getZExtValue()
2306assert(isa<DILocalVariable>(Variable) &&
"not a variable");
2307assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
2308assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
DL) &&
2309"Expected inlined-at fields to agree");
2322assert(isa<DILocalVariable>(Variable) &&
"not a variable");
2323assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
2324assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
DL) &&
2325"Expected inlined-at fields to agree");
2326if (MCID.
Opcode == TargetOpcode::DBG_VALUE) {
2328"DBG_VALUE must contain exactly one debug operand");
2343 MIB.addMetadata(Variable).addMetadata(Expr);
2346 MIB.addReg(DebugOp.getReg());
2371BuildMI(MF,
DL, MCID, IsIndirect, DebugOps, Variable, Expr);
2376/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot. 2377/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE. 2381assert(
MI.getDebugVariable()->isValidLocationForIntrinsic(
MI.getDebugLoc()) &&
2382"Expected inlined-at fields to agree");
2385if (
MI.isIndirectDebugValue()) {
2386assert(
MI.getDebugOffset().getImm() == 0 &&
2387"DBG_VALUE with nonzero offset");
2389 }
elseif (
MI.isDebugValueList()) {
2390// We will replace the spilled register with a frame index, so 2391// immediately deref all references to the spilled register. 2392 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2394unsigned OpIdx =
MI.getDebugOperandIndex(
Op);
2402assert(
MI.hasDebugOperandForReg(SpillReg) &&
"Spill Reg is not used in MI.");
2414"DBG_INSTR_REF should not reference a virtual register.");
2418// Non-Variadic Operands: Location, Offset, Variable, Expression 2419// Variadic Operands: Variable, Expression, Locations... 2425if (
Op.isReg() &&
Op.getReg() == SpillReg)
2439// Non-Variadic Operands: Location, Offset, Variable, Expression 2440// Variadic Operands: Variable, Expression, Locations... 2460Op.ChangeToFrameIndex(FrameIndex);
2467if (!
MI.getOperand(0).isReg())
2473if (!DI->isDebugValue())
2475if (DI->hasDebugOperandForReg(
MI.getOperand(0).getReg()))
2481// Collect matching debug values. 2488auto *
MRI = getRegInfo();
2489for (
auto &MO :
MRI->use_operands(DefReg)) {
2491if (!DI->isDebugValue())
2493if (DI->hasDebugOperandForReg(DefReg)) {
2498// Propagate Reg to debug value instructions. 2499for (
auto *DBI : DbgValues)
2509for (
constauto *
A : Accesses) {
2511 cast<FixedStackPseudoSourceValue>(
A->getPseudoValue())
2512 ->getFrameIndex())) {
2522std::optional<LocationSize>
2525if (
TII->isStoreToStackSlotPostFE(*
this, FI)) {
2533std::optional<LocationSize>
2541std::optional<LocationSize>
2544if (
TII->isLoadFromStackSlotPostFE(*
this, FI)) {
2552std::optional<LocationSize>
2561if (DebugInstrNum == 0)
2563return DebugInstrNum;
2567if (DebugInstrNum == 0)
2569return DebugInstrNum;
2598std::tuple<Register, LLT, Register, LLT>
2602return std::tuple(Reg0, getRegInfo()->
getType(Reg0), Reg1,
2606std::tuple<Register, LLT, Register, LLT, Register, LLT>
2611return std::tuple(Reg0, getRegInfo()->
getType(Reg0), Reg1,
2612 getRegInfo()->
getType(Reg1), Reg2,
2616std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2623 Reg0, getRegInfo()->
getType(Reg0), Reg1, getRegInfo()->
getType(Reg1),
2624 Reg2, getRegInfo()->
getType(Reg2), Reg3, getRegInfo()->
getType(Reg3));
2636 Reg0, getRegInfo()->
getType(Reg0), Reg1, getRegInfo()->
getType(Reg1),
2637 Reg2, getRegInfo()->
getType(Reg2), Reg3, getRegInfo()->
getType(Reg3),
2638 Reg4, getRegInfo()->
getType(Reg4));
2643assert(InsertBefore !=
nullptr &&
"invalid iterator");
2645"iterator points to operand of other inst");
2649// Do one pass to untie operands. 2655 TiedOpIndices[OpNo] = TiedTo;
2662unsigned OpsToMove = NumOperands - OpIdx;
2667for (
unsignedI = 0;
I < OpsToMove; ++
I) {
2677for (
auto [Tie1, Tie2] : TiedOpIndices) {
2687assert(OpId &&
"expected non-zero operand id");
2698if (
F.isRegUseKind() ||
F.isRegDefKind() ||
F.isRegDefEarlyClobberKind())
2699returnF.getRegMayBeFolded();
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
Implement a low-level type suitable for MachineInstr level instruction selection.
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.
static LocationSize getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)
static const DIExpression * computeExprForSpill(const MachineInstr &MI, const SmallVectorImpl< const MachineOperand * > &SpilledOperands)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, BatchAAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
This file contains the declarations for metadata subclasses.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
This file contains some templates that are useful if you are working with the STL at all.
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This file implements the SmallBitVector class.
This file defines the SmallVector class.
static SymbolRef::Type getType(const Symbol *Sym)
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
This class is a wrapper over an AAResults, and it is intended to be used only when there are no IR ch...
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
static bool isEqualExpression(const DIExpression *FirstExpr, bool FirstIndirect, const DIExpression *SecondExpr, bool SecondIndirect)
Determines whether two debug values should produce equivalent DWARF expressions, using their DIExpres...
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
This class represents an Operation in the Expression.
bool print(raw_ostream &OS, DIDumpOptions DumpOpts, const DWARFExpression *Expr, DWARFUnit *U) const
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Diagnostic information for inline asm reporting.
Utility class for floating point operations which can have information about relaxed accuracy require...
Convenience struct for specifying and reasoning about fast-math flags.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
an instruction for type-safe pointer arithmetic to access elements of arrays and structs
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
This instruction compares its operands according to the predicate given to the constructor.
static StringRef getMemConstraintName(ConstraintCode C)
constexpr bool isValid() const
This is an important class for using LLVM in a threaded context.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
A set of register units used to track register liveness.
static LocationSize precise(uint64_t Value)
static constexpr LocationSize beforeOrAfterPointer()
Any location before or after the base pointer (but still within the underlying object).
TypeSize getValue() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Wrapper class representing physical registers. Should be passed by value.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
const MDOperand & getOperand(unsigned I) const
unsigned getNumOperands() const
Return number of MDNode operands.
bool isValid() const
isValid - Returns true until all the operands have been visited.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
Instructions::iterator instr_iterator
Instructions::const_iterator const_instr_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr, MDNode *PCSections=nullptr, uint32_t CFIType=0, MDNode *MMRAs=nullptr)
Allocate and construct an extra info structure for a MachineInstr.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
unsigned getNewDebugInstrNum()
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void handleChangeDesc(MachineInstr &MI, const MCInstrDesc &TID)
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
bool isDebugValueList() const
void bundleWithPred()
Bundle this instruction with its predecessor.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
const MachineBasicBlock * getParent() const
MDNode * getMMRAMetadata() const
Helper to extract mmra.op metadata.
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
QueryType
API for querying MachineInstr properties.
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
bool isCall(QueryType Type=AnyInBundle) const
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Register isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool allImplicitDefsAreDead() const
Return true if all the implicit defs of this instruction are dead.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
bool isSafeToMove(bool &SawStore) const
Return true if it is safe to move this instruction.
bool mayAlias(BatchAAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
unsigned getNumOperands() const
Retuns the total number of operands.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
std::optional< LocationSize > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool wouldBeTriviallyDead() const
Return true if this instruction would be trivially dead if all of its defined registers were dead.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
std::tuple< LLT, LLT > getFirst2LLTs() const
std::optional< LocationSize > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
bool isStackAligningInlineAsm() const
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
bool isCandidateForAdditionalCallInfo(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an additional information associated with it.
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
std::optional< LocationSize > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
static uint32_t copyFlagsFromInstruction(const Instruction &I)
void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)
Inserts Ops BEFORE It. Can untie/retie tied operands.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool isJumpTableDebugInfo() const
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' from its basic block and delete it.
iterator_range< mop_iterator > operands()
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
bool isLifetimeMarker() const
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
void emitGenericError(const Twine &ErrMsg) const
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isNonListDebugValue() const
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
bool isDead(const MachineRegisterInfo &MRI, LiveRegUnits *LivePhysRegs=nullptr) const
Check whether an MI is dead.
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isDebugValue() const
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
MachineOperand & getDebugOperand(unsigned Index)
std::optional< LocationSize > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
iterator_range< mop_iterator > implicit_operands()
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
void emitInlineAsmError(const Twine &ErrMsg) const
Emit an error referring to the source location of this instruction.
uint32_t getFlags() const
Return the MI flags bitvector.
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool shouldUpdateAdditionalCallInfo() const
Return true if copying, moving, or erasing this instruction requires updating additional call info (s...
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
void unbundleFromSucc()
Break bundle below this instruction.
iterator_range< filtered_mop_iterator > all_defs()
Returns an iterator range over all operands that are (explicit or implicit) register defs.
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
void setPCSections(MachineFunction &MF, MDNode *MD)
const MDNode * getLocCookieMD() const
For inline asm, get the !srcloc metadata node if we have it, and decode the loc cookie from it.
int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs)
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool mayFoldInlineAsmRegOp(unsigned OpId) const
Returns true if the register operand can be folded with a load or store into a frame index.
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const PseudoSourceValue * getPseudoValue() const
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
const Value * getValue() const
Return the base address of the memory access.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MDNode * getMetadata() const
void setIsDead(bool Val=true)
void setMetadata(const MDNode *MD)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
void setIsEarlyClobber(bool Val=true)
void setIsUndef(bool Val=true)
void setIsDebug(bool Val=true)
Register getReg() const
getReg - Returns the register number.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Representation for a specific memory location.
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Manage lifetime of a slot tracker for printing IR.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
An or instruction, which can be marked as "disjoint", indicating that the inputs don't have a 1 in th...
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Instruction that can have a nneg flag (zext/uitofp).
Special value supplied for machine level alias analysis.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void reserve(size_type N)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
MI-level Statepoint operands.
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
virtual const TargetInstrInfo * getInstrInfo() const
This class represents a truncation of integer types.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
A Use represents the edge between a Value definition and its users.
LLVM Value Representation.
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
self_iterator getIterator()
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
hash_code hash_value(const FixedPointSemantics &Val)
formatted_raw_ostream & fdbgs()
fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Implement std::hash so that hash_code can be used in STL containers.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
static unsigned getHashValue(const MachineInstr *const &MI)
