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1//===-- M68kFrameLowering.cpp - M68k Frame Information ----------*- C++ -*-===//

2//

3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

4// See https://llvm.org/LICENSE.txt for license information.

5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

6//

7//===----------------------------------------------------------------------===//

8///

9/// \file

10/// This file contains the M68k implementation of TargetFrameLowering class.

11///

12//===----------------------------------------------------------------------===//

14#include "M68kFrameLowering.h"

16#include "M68kInstrBuilder.h"

17#include "M68kInstrInfo.h"

18#include "M68kMachineFunction.h"

19#include "M68kSubtarget.h"

21#include "llvm/ADT/SmallSet.h"

22#include "llvm/CodeGen/MachineFrameInfo.h"

23#include "llvm/CodeGen/MachineFunction.h"

24#include "llvm/CodeGen/MachineInstrBuilder.h"

25#include "llvm/CodeGen/MachineModuleInfo.h"

26#include "llvm/CodeGen/MachineRegisterInfo.h"

27#include "llvm/IR/DataLayout.h"

28#include "llvm/IR/Function.h"

29#include "llvm/Support/Alignment.h"

30#include "llvm/Support/CommandLine.h"

31#include "llvm/Target/TargetMachine.h"

32#include "llvm/Target/TargetOptions.h"

34using namespacellvm;

36#define DEBUG_TYPE "m68k-frame"

38M68kFrameLowering::M68kFrameLowering(constM68kSubtarget &STI,Align Alignment)

39 :TargetFrameLowering(StackGrowsDown, Alignment, -4), STI(STI),

40TII(*STI.getInstrInfo()),TRI(STI.getRegisterInfo()) {

41 SlotSize = STI.getSlotSize();

42 StackPtr = TRI->getStackRegister();

43}

45boolM68kFrameLowering::hasFPImpl(constMachineFunction &MF) const{

46constMachineFrameInfo &MFI = MF.getFrameInfo();

47constTargetRegisterInfo *TRI = STI.getRegisterInfo();

49return MF.getTarget().Options.DisableFramePointerElim(MF) ||

50 MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() ||

51TRI->hasStackRealignment(MF);

52}

54// FIXME Make sure no other factors prevent us from reserving call frame

55boolM68kFrameLowering::hasReservedCallFrame(constMachineFunction &MF) const{

56return !MF.getFrameInfo().hasVarSizedObjects() &&

57 !MF.getInfo<M68kMachineFunctionInfo>()->getHasPushSequences();

58}

60boolM68kFrameLowering::canSimplifyCallFramePseudos(

61constMachineFunction &MF) const{

62returnhasReservedCallFrame(MF) ||

63 (hasFP(MF) && !TRI->hasStackRealignment(MF)) ||

64 TRI->hasBasePointer(MF);

65}

67boolM68kFrameLowering::needsFrameIndexResolution(

68constMachineFunction &MF) const{

69return MF.getFrameInfo().hasStackObjects() ||

70 MF.getInfo<M68kMachineFunctionInfo>()->getHasPushSequences();

71}

73// NOTE: this only has a subset of the full frame index logic. In

74// particular, the FI < 0 and AfterFPPop logic is handled in

75// M68kRegisterInfo::eliminateFrameIndex, but not here. Possibly

76// (probably?) it should be moved into here.

77StackOffset

78M68kFrameLowering::getFrameIndexReference(constMachineFunction &MF,int FI,

79Register &FrameReg) const{

80constMachineFrameInfo &MFI = MF.getFrameInfo();

82// We can't calculate offset from frame pointer if the stack is realigned,

83// so enforce usage of stack/base pointer. The base pointer is used when we

84// have dynamic allocas in addition to dynamic realignment.

85if (TRI->hasBasePointer(MF))

86 FrameReg = TRI->getBaseRegister();

87elseif (TRI->hasStackRealignment(MF))

88 FrameReg = TRI->getStackRegister();

89else

90 FrameReg = TRI->getFrameRegister(MF);

92// Offset will hold the offset from the stack pointer at function entry to the

93// object.

94// We need to factor in additional offsets applied during the prologue to the

95// frame, base, and stack pointer depending on which is used.

96intOffset = MFI.getObjectOffset(FI) -getOffsetOfLocalArea();

97constM68kMachineFunctionInfo *MMFI = MF.getInfo<M68kMachineFunctionInfo>();

98uint64_t StackSize = MFI.getStackSize();

99bool HasFP =hasFP(MF);

100

101// TODO: Support tail calls

102if (TRI->hasBasePointer(MF)) {

103assert(HasFP &&"VLAs and dynamic stack realign, but no FP?!");

104if (FI < 0) {

105// Skip the saved FP.

106returnStackOffset::getFixed(Offset + SlotSize);

107 }

108

109assert((-(Offset + StackSize)) % MFI.getObjectAlign(FI).value() == 0);

110returnStackOffset::getFixed(Offset + StackSize);

111 }

112if (TRI->hasStackRealignment(MF)) {

113if (FI < 0) {

114// Skip the saved FP.

115returnStackOffset::getFixed(Offset + SlotSize);

116 }

117

118assert((-(Offset + StackSize)) % MFI.getObjectAlign(FI).value() == 0);

119returnStackOffset::getFixed(Offset + StackSize);

120 }

121

122if (!HasFP)

123returnStackOffset::getFixed(Offset + StackSize);

124

125// Skip the saved FP.

126Offset += SlotSize;

127

128// Skip the RETADDR move area

129int TailCallReturnAddrDelta = MMFI->getTCReturnAddrDelta();

130if (TailCallReturnAddrDelta < 0)

131Offset -= TailCallReturnAddrDelta;

132

133returnStackOffset::getFixed(Offset);

134}

135

136/// Return a caller-saved register that isn't live

137/// when it reaches the "return" instruction. We can then pop a stack object

138/// to this register without worry about clobbering it.

139staticunsignedfindDeadCallerSavedReg(MachineBasicBlock &MBB,

140MachineBasicBlock::iterator &MBBI,

141constM68kRegisterInfo *TRI) {

142constMachineFunction *MF =MBB.getParent();

143if (MF->callsEHReturn())

144return 0;

145

146constTargetRegisterClass &AvailableRegs = *TRI->getRegsForTailCall(*MF);

147

148if (MBBI ==MBB.end())

149return 0;

150

151switch (MBBI->getOpcode()) {

152default:

153return 0;

154case TargetOpcode::PATCHABLE_RET:

155case M68k::RET: {

156SmallSet<uint16_t, 8>Uses;

157

158for (unsigned i = 0, e =MBBI->getNumOperands(); i != e; ++i) {

159MachineOperand &MO =MBBI->getOperand(i);

160if (!MO.isReg() || MO.isDef())

161continue;

162Register Reg = MO.getReg();

163if (!Reg)

164continue;

165for (MCRegAliasIterator AI(Reg,TRI,true); AI.isValid(); ++AI)

166Uses.insert(*AI);

167 }

168

169for (auto CS : AvailableRegs)

170if (!Uses.count(CS))

171return CS;

172 }

173 }

174

175return 0;

176}

177

178staticboolisRegLiveIn(MachineBasicBlock &MBB,unsigned Reg) {

179returnllvm::any_of(MBB.liveins(),

180 [Reg](MachineBasicBlock::RegisterMaskPair RegMask) {

181 return RegMask.PhysReg == Reg;

182 });

183}

184

185uint64_t

186M68kFrameLowering::calculateMaxStackAlign(constMachineFunction &MF) const{

187constMachineFrameInfo &MFI = MF.getFrameInfo();

188uint64_t MaxAlign = MFI.getMaxAlign().value();// Desired stack alignment.

189unsigned StackAlign =getStackAlignment();// ABI alignment

190if (MF.getFunction().hasFnAttribute("stackrealign")) {

191if (MFI.hasCalls())

192 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;

193elseif (MaxAlign < SlotSize)

194 MaxAlign = SlotSize;

195 }

196return MaxAlign;

197}

198

199void M68kFrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,

200MachineBasicBlock::iterator MBBI,

201constDebugLoc &DL,unsigned Reg,

202uint64_t MaxAlign) const{

203uint64_t Val = -MaxAlign;

204unsigned AndOp = M68k::AND32di;

205unsigned MovOp = M68k::MOV32rr;

206

207// This function is normally used with SP which is Address Register, but AND,

208// or any other logical instructions in M68k do not support ARs so we need

209// to use a temp Data Register to perform the op.

210unsigned Tmp = M68k::D0;

211

212BuildMI(MBB,MBBI,DL, TII.get(MovOp), Tmp)

213 .addReg(Reg)

214 .setMIFlag(MachineInstr::FrameSetup);

215

216MachineInstr *MI =BuildMI(MBB,MBBI,DL, TII.get(AndOp), Tmp)

217 .addReg(Tmp)

218 .addImm(Val)

219 .setMIFlag(MachineInstr::FrameSetup);

220

221// The CCR implicit def is dead.

222MI->getOperand(3).setIsDead();

223

224BuildMI(MBB,MBBI,DL, TII.get(MovOp), Reg)

225 .addReg(Tmp)

226 .setMIFlag(MachineInstr::FrameSetup);

227}

228

229MachineBasicBlock::iterator M68kFrameLowering::eliminateCallFramePseudoInstr(

230MachineFunction &MF,MachineBasicBlock &MBB,

231MachineBasicBlock::iterator I) const{

232bool ReserveCallFrame =hasReservedCallFrame(MF);

233unsigned Opcode =I->getOpcode();

234bool IsDestroy = Opcode == TII.getCallFrameDestroyOpcode();

235DebugLoc DL =I->getDebugLoc();

236uint64_t Amount =I->getOperand(0).getImm();

237uint64_t InternalAmt = (IsDestroy || Amount) ?I->getOperand(1).getImm() : 0;

238I =MBB.erase(I);

239

240if (!ReserveCallFrame) {

241// If the stack pointer can be changed after prologue, turn the

242// adjcallstackup instruction into a 'sub %SP, <amt>' and the

243// adjcallstackdown instruction into 'add %SP, <amt>'

244

245// We need to keep the stack aligned properly. To do this, we round the

246// amount of space needed for the outgoing arguments up to the next

247// alignment boundary.

248unsigned StackAlign =getStackAlignment();

249 Amount =alignTo(Amount, StackAlign);

250

251boolDwarfCFI = MF.needsFrameMoves();

252

253// If we have any exception handlers in this function, and we adjust

254// the SP before calls, we may need to indicate this to the unwinder

255// using GNU_ARGS_SIZE. Note that this may be necessary even when

256// Amount == 0, because the preceding function may have set a non-0

257// GNU_ARGS_SIZE.

258// TODO: We don't need to reset this between subsequent functions,

259// if it didn't change.

260bool HasDwarfEHHandlers = !MF.getLandingPads().empty();

261

262if (HasDwarfEHHandlers && !IsDestroy &&

263 MF.getInfo<M68kMachineFunctionInfo>()->getHasPushSequences()) {

264 BuildCFI(MBB,I,DL,

265MCCFIInstruction::createGnuArgsSize(nullptr, Amount));

266 }

267

268if (Amount == 0)

269returnI;

270

271// Factor out the amount that gets handled inside the sequence

272// (Pushes of argument for frame setup, callee pops for frame destroy)

273 Amount -= InternalAmt;

274

275// TODO: This is needed only if we require precise CFA.

276// If this is a callee-pop calling convention, emit a CFA adjust for

277// the amount the callee popped.

278if (IsDestroy && InternalAmt &&DwarfCFI && !hasFP(MF))

279 BuildCFI(MBB,I,DL,

280MCCFIInstruction::createAdjustCfaOffset(nullptr, -InternalAmt));

281

282// Add Amount to SP to destroy a frame, or subtract to setup.

283 int64_t StackAdjustment = IsDestroy ? Amount : -Amount;

284 int64_t CfaAdjustment = -StackAdjustment;

285

286if (StackAdjustment) {

287// Merge with any previous or following adjustment instruction. Note: the

288// instructions merged with here do not have CFI, so their stack

289// adjustments do not feed into CfaAdjustment.

290 StackAdjustment +=mergeSPUpdates(MBB,I,true);

291 StackAdjustment +=mergeSPUpdates(MBB,I,false);

292

293if (StackAdjustment) {

294 BuildStackAdjustment(MBB,I,DL, StackAdjustment,false);

295 }

296 }

297

298if (DwarfCFI && !hasFP(MF)) {

299// If we don't have FP, but need to generate unwind information,

300// we need to set the correct CFA offset after the stack adjustment.

301// How much we adjust the CFA offset depends on whether we're emitting

302// CFI only for EH purposes or for debugging. EH only requires the CFA

303// offset to be correct at each call site, while for debugging we want

304// it to be more precise.

305

306// TODO: When not using precise CFA, we also need to adjust for the

307// InternalAmt here.

308if (CfaAdjustment) {

309 BuildCFI(

310MBB,I,DL,

311MCCFIInstruction::createAdjustCfaOffset(nullptr, CfaAdjustment));

312 }

313 }

314

315returnI;

316 }

317

318if (IsDestroy && InternalAmt) {

319// If we are performing frame pointer elimination and if the callee pops

320// something off the stack pointer, add it back. We do this until we have

321// more advanced stack pointer tracking ability.

322// We are not tracking the stack pointer adjustment by the callee, so make

323// sure we restore the stack pointer immediately after the call, there may

324// be spill code inserted between the CALL and ADJCALLSTACKUP instructions.

325MachineBasicBlock::iterator CI =I;

326MachineBasicBlock::iterator B =MBB.begin();

327while (CI !=B && !std::prev(CI)->isCall())

328 --CI;

329 BuildStackAdjustment(MBB, CI,DL, -InternalAmt,/*InEpilogue=*/false);

330 }

331

332returnI;

333}

334

335/// Emit a series of instructions to increment / decrement the stack pointer by

336/// a constant value.

337voidM68kFrameLowering::emitSPUpdate(MachineBasicBlock &MBB,

338MachineBasicBlock::iterator &MBBI,

339 int64_t NumBytes,bool InEpilogue) const{

340bool IsSub = NumBytes < 0;

341uint64_t Offset = IsSub ? -NumBytes : NumBytes;

342

343uint64_t Chunk = (1LL << 31) - 1;

344DebugLoc DL =MBB.findDebugLoc(MBBI);

345

346while (Offset) {

347if (Offset > Chunk) {

348// Rather than emit a long series of instructions for large offsets,

349// load the offset into a register and do one sub/add

350Register Reg;

351

352if (IsSub && !isRegLiveIn(MBB, M68k::D0))

353 Reg = M68k::D0;

354else

355 Reg =findDeadCallerSavedReg(MBB,MBBI, TRI);

356

357if (Reg) {

358unsigned Opc = M68k::MOV32ri;

359BuildMI(MBB,MBBI,DL, TII.get(Opc), Reg).addImm(Offset);

360 Opc = IsSub ? M68k::SUB32ar : M68k::ADD32ar;

361MachineInstr *MI =BuildMI(MBB,MBBI,DL, TII.get(Opc), StackPtr)

362 .addReg(StackPtr)

363 .addReg(Reg);

364// ??? still no CCR

365MI->getOperand(3).setIsDead();// The CCR implicit def is dead.

366Offset = 0;

367continue;

368 }

369 }

370

371uint64_t ThisVal = std::min(Offset, Chunk);

372

373MachineInstrBuilder MI = BuildStackAdjustment(

374MBB,MBBI,DL, IsSub ? -ThisVal : ThisVal, InEpilogue);

375if (IsSub)

376MI.setMIFlag(MachineInstr::FrameSetup);

377else

378MI.setMIFlag(MachineInstr::FrameDestroy);

379

380Offset -= ThisVal;

381 }

382}

383

384intM68kFrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,

385MachineBasicBlock::iterator &MBBI,

386bool MergeWithPrevious) const{

387if ((MergeWithPrevious &&MBBI ==MBB.begin()) ||

388 (!MergeWithPrevious &&MBBI ==MBB.end()))

389return 0;

390

391MachineBasicBlock::iterator PI = MergeWithPrevious ? std::prev(MBBI) :MBBI;

392MachineBasicBlock::iterator NI =

393 MergeWithPrevious ? nullptr : std::next(MBBI);

394unsigned Opc = PI->getOpcode();

395intOffset = 0;

396

397if (!MergeWithPrevious && NI !=MBB.end() &&

398 NI->getOpcode() == TargetOpcode::CFI_INSTRUCTION) {

399// Don't merge with the next instruction if it has CFI.

400returnOffset;

401 }

402

403if (Opc == M68k::ADD32ai && PI->getOperand(0).getReg() == StackPtr) {

404assert(PI->getOperand(1).getReg() == StackPtr);

405Offset += PI->getOperand(2).getImm();

406MBB.erase(PI);

407if (!MergeWithPrevious)

408MBBI = NI;

409 }elseif (Opc == M68k::SUB32ai && PI->getOperand(0).getReg() == StackPtr) {

410assert(PI->getOperand(1).getReg() == StackPtr);

411Offset -= PI->getOperand(2).getImm();

412MBB.erase(PI);

413if (!MergeWithPrevious)

414MBBI = NI;

415 }

416

417returnOffset;

418}

419

420MachineInstrBuilder M68kFrameLowering::BuildStackAdjustment(

421MachineBasicBlock &MBB,MachineBasicBlock::iterator MBBI,

422constDebugLoc &DL, int64_tOffset,bool InEpilogue) const{

423assert(Offset != 0 &&"zero offset stack adjustment requested");

424

425// TODO can `lea` be used to adjust stack?

426

427bool IsSub =Offset < 0;

428uint64_t AbsOffset = IsSub ? -Offset :Offset;

429unsigned Opc = IsSub ? M68k::SUB32ai : M68k::ADD32ai;

430

431MachineInstrBuilder MI =BuildMI(MBB,MBBI,DL, TII.get(Opc), StackPtr)

432 .addReg(StackPtr)

433 .addImm(AbsOffset);

434// FIXME Update CCR as well. For now we just

435// conservatively say CCR implicit def is dead

436MI->getOperand(3).setIsDead();

437returnMI;

438}

439

440void M68kFrameLowering::BuildCFI(MachineBasicBlock &MBB,

441MachineBasicBlock::iterator MBBI,

442constDebugLoc &DL,

443constMCCFIInstruction &CFIInst) const{

444MachineFunction &MF = *MBB.getParent();

445unsigned CFIIndex = MF.addFrameInst(CFIInst);

446BuildMI(MBB,MBBI,DL, TII.get(TargetOpcode::CFI_INSTRUCTION))

447 .addCFIIndex(CFIIndex);

448}

449

450void M68kFrameLowering::emitPrologueCalleeSavedFrameMoves(

451MachineBasicBlock &MBB,MachineBasicBlock::iterator MBBI,

452constDebugLoc &DL) const{

453MachineFunction &MF = *MBB.getParent();

454MachineFrameInfo &MFI = MF.getFrameInfo();

455constMCRegisterInfo *MRI = MF.getContext().getRegisterInfo();

456

457// Add callee saved registers to move list.

458constauto &CSI = MFI.getCalleeSavedInfo();

459if (CSI.empty())

460return;

461

462// Calculate offsets.

463for (constauto &I : CSI) {

464 int64_tOffset = MFI.getObjectOffset(I.getFrameIdx());

465Register Reg =I.getReg();

466

467unsigned DwarfReg =MRI->getDwarfRegNum(Reg,true);

468 BuildCFI(MBB,MBBI,DL,

469MCCFIInstruction::createOffset(nullptr, DwarfReg,Offset));

470 }

471}

472

473voidM68kFrameLowering::emitPrologue(MachineFunction &MF,

474MachineBasicBlock &MBB) const{

475assert(&STI == &MF.getSubtarget<M68kSubtarget>() &&

476"MF used frame lowering for wrong subtarget");

477

478MachineBasicBlock::iterator MBBI =MBB.begin();

479MachineFrameInfo &MFI = MF.getFrameInfo();

480M68kMachineFunctionInfo *MMFI = MF.getInfo<M68kMachineFunctionInfo>();

481uint64_t MaxAlign = calculateMaxStackAlign(MF);// Desired stack alignment.

482uint64_t StackSize = MFI.getStackSize();// Number of bytes to allocate.

483bool HasFP =hasFP(MF);

484bool NeedsDwarfCFI = MF.needsFrameMoves();

485Register FramePtr = TRI->getFrameRegister(MF);

486constunsigned MachineFramePtr =FramePtr;

487unsigned BasePtr = TRI->getBaseRegister();

488

489// Debug location must be unknown since the first debug location is used

490// to determine the end of the prologue.

491DebugLoc DL;

492

493// Add RETADDR move area to callee saved frame size.

494int TailCallReturnAddrDelta = MMFI->getTCReturnAddrDelta();

495

496if (TailCallReturnAddrDelta < 0) {

497 MMFI->setCalleeSavedFrameSize(MMFI->getCalleeSavedFrameSize() -

498 TailCallReturnAddrDelta);

499 }

500

501// Insert stack pointer adjustment for later moving of return addr. Only

502// applies to tail call optimized functions where the callee argument stack

503// size is bigger than the callers.

504if (TailCallReturnAddrDelta < 0) {

505 BuildStackAdjustment(MBB,MBBI,DL, TailCallReturnAddrDelta,

506/*InEpilogue=*/false)

507 .setMIFlag(MachineInstr::FrameSetup);

508 }

509

510// Mapping for machine moves:

511//

512// DST: VirtualFP AND

513// SRC: VirtualFP => DW_CFA_def_cfa_offset

514// ELSE => DW_CFA_def_cfa

515//

516// SRC: VirtualFP AND

517// DST: Register => DW_CFA_def_cfa_register

518//

519// ELSE

520// OFFSET < 0 => DW_CFA_offset_extended_sf

521// REG < 64 => DW_CFA_offset + Reg

522// ELSE => DW_CFA_offset_extended

523

524uint64_t NumBytes = 0;

525int stackGrowth = -SlotSize;

526

527if (HasFP) {

528// Calculate required stack adjustment.

529uint64_t FrameSize = StackSize - SlotSize;

530// If required, include space for extra hidden slot for stashing base

531// pointer.

532if (MMFI->getRestoreBasePointer())

533 FrameSize += SlotSize;

534

535 NumBytes = FrameSize - MMFI->getCalleeSavedFrameSize();

536

537// Callee-saved registers are pushed on stack before the stack is realigned.

538if (TRI->hasStackRealignment(MF))

539 NumBytes =alignTo(NumBytes, MaxAlign);

540

541// Get the offset of the stack slot for the FP register, which is

542// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.

543// Update the frame offset adjustment.

544 MFI.setOffsetAdjustment(-NumBytes);

545

546BuildMI(MBB,MBBI,DL, TII.get(M68k::LINK16))

547 .addReg(M68k::WA6,RegState::Kill)

548 .addImm(-NumBytes)

549 .setMIFlag(MachineInstr::FrameSetup);

550

551if (NeedsDwarfCFI) {

552// Mark the place where FP was saved.

553// Define the current CFA rule to use the provided offset.

554assert(StackSize);

555 BuildCFI(MBB,MBBI,DL,

556MCCFIInstruction::cfiDefCfaOffset(nullptr, 2 * stackGrowth));

557

558// Change the rule for the FramePtr to be an "offset" rule.

559int DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr,true);

560assert(DwarfFramePtr > 0);

561 BuildCFI(MBB,MBBI,DL,

562MCCFIInstruction::createOffset(nullptr, DwarfFramePtr,

563 2 * stackGrowth));

564 }

565

566if (NeedsDwarfCFI) {

567// Mark effective beginning of when frame pointer becomes valid.

568// Define the current CFA to use the FP register.

569unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr,true);

570 BuildCFI(MBB,MBBI,DL,

571MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));

572 }

573

574// Mark the FramePtr as live-in in every block. Don't do this again for

575// funclet prologues.

576for (MachineBasicBlock &EveryMBB : MF)

577 EveryMBB.addLiveIn(MachineFramePtr);

578 }else {

579 NumBytes = StackSize - MMFI->getCalleeSavedFrameSize();

580 }

581

582// Skip the callee-saved push instructions.

583bool PushedRegs =false;

584intStackOffset = 2 * stackGrowth;

585

586while (MBBI !=MBB.end() &&MBBI->getFlag(MachineInstr::FrameSetup) &&

587MBBI->getOpcode() == M68k::PUSH32r) {

588 PushedRegs =true;

589 ++MBBI;

590

591if (!HasFP && NeedsDwarfCFI) {

592// Mark callee-saved push instruction.

593// Define the current CFA rule to use the provided offset.

594assert(StackSize);

595 BuildCFI(MBB,MBBI,DL,

596MCCFIInstruction::cfiDefCfaOffset(nullptr,StackOffset));

597StackOffset += stackGrowth;

598 }

599 }

600

601// Realign stack after we pushed callee-saved registers (so that we'll be

602// able to calculate their offsets from the frame pointer).

603if (TRI->hasStackRealignment(MF)) {

604assert(HasFP &&"There should be a frame pointer if stack is realigned.");

605 BuildStackAlignAND(MBB,MBBI,DL, StackPtr, MaxAlign);

606 }

607

608// If there is an SUB32ri of SP immediately before this instruction, merge

609// the two. This can be the case when tail call elimination is enabled and

610// the callee has more arguments then the caller.

611 NumBytes -=mergeSPUpdates(MBB,MBBI,true);

612

613// Adjust stack pointer: ESP -= numbytes.

614if (!HasFP)

615emitSPUpdate(MBB,MBBI, -(int64_t)NumBytes,/*InEpilogue=*/false);

616

617unsigned SPOrEstablisher = StackPtr;

618

619// If we need a base pointer, set it up here. It's whatever the value

620// of the stack pointer is at this point. Any variable size objects

621// will be allocated after this, so we can still use the base pointer

622// to reference locals.

623if (TRI->hasBasePointer(MF)) {

624// Update the base pointer with the current stack pointer.

625BuildMI(MBB,MBBI,DL, TII.get(M68k::MOV32aa), BasePtr)

626 .addReg(SPOrEstablisher)

627 .setMIFlag(MachineInstr::FrameSetup);

628if (MMFI->getRestoreBasePointer()) {

629// Stash value of base pointer. Saving SP instead of FP shortens

630// dependence chain. Used by SjLj EH.

631unsigned Opm = M68k::MOV32ja;

632M68k::addRegIndirectWithDisp(BuildMI(MBB,MBBI,DL, TII.get(Opm)),

633FramePtr,true,

634 MMFI->getRestoreBasePointerOffset())

635 .addReg(SPOrEstablisher)

636 .setMIFlag(MachineInstr::FrameSetup);

637 }

638 }

639

640if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {

641// Mark end of stack pointer adjustment.

642if (!HasFP && NumBytes) {

643// Define the current CFA rule to use the provided offset.

644assert(StackSize);

645 BuildCFI(

646MBB,MBBI,DL,

647MCCFIInstruction::cfiDefCfaOffset(nullptr, -StackSize + stackGrowth));

648 }

649

650// Emit DWARF info specifying the offsets of the callee-saved registers.

651if (PushedRegs)

652 emitPrologueCalleeSavedFrameMoves(MBB,MBBI,DL);

653 }

654

655// TODO Interrupt handlers

656// M68k Interrupt handling function cannot assume anything about the

657// direction flag (DF in CCR register). Clear this flag by creating "cld"

658// instruction in each prologue of interrupt handler function. The "cld"

659// instruction should only in these cases:

660// 1. The interrupt handling function uses any of the "rep" instructions.

661// 2. Interrupt handling function calls another function.

662}

663

664staticboolisTailCallOpcode(unsigned Opc) {

665return Opc == M68k::TCRETURNj || Opc == M68k::TCRETURNq;

666}

667

668voidM68kFrameLowering::emitEpilogue(MachineFunction &MF,

669MachineBasicBlock &MBB) const{

670constMachineFrameInfo &MFI = MF.getFrameInfo();

671M68kMachineFunctionInfo *MMFI = MF.getInfo<M68kMachineFunctionInfo>();

672MachineBasicBlock::iterator MBBI =MBB.getFirstTerminator();

673 std::optional<unsigned> RetOpcode;

674if (MBBI !=MBB.end())

675 RetOpcode =MBBI->getOpcode();

676DebugLoc DL;

677if (MBBI !=MBB.end())

678DL =MBBI->getDebugLoc();

679Register FramePtr = TRI->getFrameRegister(MF);

680unsigned MachineFramePtr =FramePtr;

681

682// Get the number of bytes to allocate from the FrameInfo.

683uint64_t StackSize = MFI.getStackSize();

684uint64_t MaxAlign = calculateMaxStackAlign(MF);

685unsigned CSSize = MMFI->getCalleeSavedFrameSize();

686uint64_t NumBytes = 0;

687

688if (hasFP(MF)) {

689// Calculate required stack adjustment.

690uint64_t FrameSize = StackSize - SlotSize;

691 NumBytes = FrameSize - CSSize;

692

693// Callee-saved registers were pushed on stack before the stack was

694// realigned.

695if (TRI->hasStackRealignment(MF))

696 NumBytes =alignTo(FrameSize, MaxAlign);

697

698 }else {

699 NumBytes = StackSize - CSSize;

700 }

701

702// Skip the callee-saved pop instructions.

703while (MBBI !=MBB.begin()) {

704MachineBasicBlock::iterator PI = std::prev(MBBI);

705unsigned Opc = PI->getOpcode();

706

707if ((Opc != M68k::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&

708 Opc != M68k::DBG_VALUE && !PI->isTerminator())

709break;

710

711 --MBBI;

712 }

713MachineBasicBlock::iterator FirstCSPop =MBBI;

714

715if (MBBI !=MBB.end())

716DL =MBBI->getDebugLoc();

717

718// If there is an ADD32ri or SUB32ri of SP immediately before this

719// instruction, merge the two instructions.

720if (NumBytes || MFI.hasVarSizedObjects())

721 NumBytes +=mergeSPUpdates(MBB,MBBI,true);

722

723// If dynamic alloca is used, then reset SP to point to the last callee-saved

724// slot before popping them off! Same applies for the case, when stack was

725// realigned. Don't do this if this was a funclet epilogue, since the funclets

726// will not do realignment or dynamic stack allocation.

727if ((TRI->hasStackRealignment(MF) || MFI.hasVarSizedObjects())) {

728if (TRI->hasStackRealignment(MF))

729MBBI = FirstCSPop;

730uint64_t LEAAmount = -CSSize;

731

732// 'move %FramePtr, SP' will not be recognized as an epilogue sequence.

733// However, we may use this sequence if we have a frame pointer because the

734// effects of the prologue can safely be undone.

735if (LEAAmount != 0) {

736unsigned Opc = M68k::LEA32p;

737M68k::addRegIndirectWithDisp(

738BuildMI(MBB,MBBI,DL, TII.get(Opc), StackPtr),FramePtr,false,

739 LEAAmount);

740 --MBBI;

741 }else {

742BuildMI(MBB,MBBI,DL, TII.get(M68k::UNLK))

743 .addReg(MachineFramePtr,RegState::Kill)

744 .setMIFlag(MachineInstr::FrameDestroy);

745 --MBBI;

746 }

747 }elseif (hasFP(MF)) {

748BuildMI(MBB,MBBI,DL, TII.get(M68k::UNLK))

749 .addReg(MachineFramePtr,RegState::Kill)

750 .setMIFlag(MachineInstr::FrameDestroy);

751 }elseif (NumBytes) {

752// Adjust stack pointer back: SP += numbytes.

753emitSPUpdate(MBB,MBBI, NumBytes,/*InEpilogue=*/true);

754 --MBBI;

755 }

756

757if (!RetOpcode || !isTailCallOpcode(*RetOpcode)) {

758// Add the return addr area delta back since we are not tail calling.

759intOffset = -1 * MMFI->getTCReturnAddrDelta();

760assert(Offset >= 0 &&"TCDelta should never be positive");

761if (Offset) {

762MBBI =MBB.getFirstTerminator();

763

764// Check for possible merge with preceding ADD instruction.

765Offset +=mergeSPUpdates(MBB,MBBI,true);

766emitSPUpdate(MBB,MBBI,Offset,/*InEpilogue=*/true);

767 }

768 }

769}

770

771voidM68kFrameLowering::determineCalleeSaves(MachineFunction &MF,

772BitVector &SavedRegs,

773RegScavenger *RS) const{

774TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);

775

776MachineFrameInfo &MFI = MF.getFrameInfo();

777

778M68kMachineFunctionInfo *M68kFI = MF.getInfo<M68kMachineFunctionInfo>();

779 int64_t TailCallReturnAddrDelta = M68kFI->getTCReturnAddrDelta();

780

781if (TailCallReturnAddrDelta < 0) {

782// create RETURNADDR area

783// arg

784// arg

785// RETADDR

786// { ...

787// RETADDR area

788// ...

789// }

790// [FP]

791 MFI.CreateFixedObject(-TailCallReturnAddrDelta,

792 TailCallReturnAddrDelta - SlotSize,true);

793 }

794

795// Spill the BasePtr if it's used.

796if (TRI->hasBasePointer(MF)) {

797 SavedRegs.set(TRI->getBaseRegister());

798 }

799}

800

801boolM68kFrameLowering::assignCalleeSavedSpillSlots(

802MachineFunction &MF,constTargetRegisterInfo *TRI,

803 std::vector<CalleeSavedInfo> &CSI) const{

804MachineFrameInfo &MFI = MF.getFrameInfo();

805M68kMachineFunctionInfo *M68kFI = MF.getInfo<M68kMachineFunctionInfo>();

806

807int SpillSlotOffset =getOffsetOfLocalArea() + M68kFI->getTCReturnAddrDelta();

808

809if (hasFP(MF)) {

810// emitPrologue always spills frame register the first thing.

811 SpillSlotOffset -= SlotSize;

812 MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);

813

814// Since emitPrologue and emitEpilogue will handle spilling and restoring of

815// the frame register, we can delete it from CSI list and not have to worry

816// about avoiding it later.

817Register FPReg =TRI->getFrameRegister(MF);

818for (unsigned i = 0, e = CSI.size(); i < e; ++i) {

819if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {

820 CSI.erase(CSI.begin() + i);

821break;

822 }

823 }

824 }

825

826// The rest is fine

827returnfalse;

828}

829

830boolM68kFrameLowering::spillCalleeSavedRegisters(

831MachineBasicBlock &MBB,MachineBasicBlock::iterator MI,

832ArrayRef<CalleeSavedInfo> CSI,constTargetRegisterInfo *TRI) const{

833auto &MRI = *static_cast<constM68kRegisterInfo *>(TRI);

834autoDL =MBB.findDebugLoc(MI);

835

836int FI = 0;

837unsigned Mask = 0;

838for (constauto &Info : CSI) {

839 FI = std::max(FI,Info.getFrameIdx());

840Register Reg =Info.getReg();

841unsigned Shift =MRI.getSpillRegisterOrder(Reg);

842 Mask |= 1 << Shift;

843 }

844

845autoI =

846M68k::addFrameReference(BuildMI(MBB,MI,DL, TII.get(M68k::MOVM32pm)), FI)

847 .addImm(Mask)

848 .setMIFlag(MachineInstr::FrameSetup);

849

850// Append implicit registers and mem locations

851constMachineFunction &MF = *MBB.getParent();

852constMachineRegisterInfo &RI = MF.getRegInfo();

853for (constauto &Info : CSI) {

854Register Reg =Info.getReg();

855bool IsLiveIn = RI.isLiveIn(Reg);

856if (!IsLiveIn)

857MBB.addLiveIn(Reg);

858I.addReg(Reg, IsLiveIn ?RegState::Implicit :RegState::ImplicitKill);

859M68k::addMemOperand(I,Info.getFrameIdx(), 0);

860 }

861

862returntrue;

863}

864

865boolM68kFrameLowering::restoreCalleeSavedRegisters(

866MachineBasicBlock &MBB,MachineBasicBlock::iterator MI,

867MutableArrayRef<CalleeSavedInfo> CSI,constTargetRegisterInfo *TRI) const{

868auto &MRI = *static_cast<constM68kRegisterInfo *>(TRI);

869autoDL =MBB.findDebugLoc(MI);

870

871int FI = 0;

872unsigned Mask = 0;

873for (constauto &Info : CSI) {

874 FI = std::max(FI,Info.getFrameIdx());

875Register Reg =Info.getReg();

876unsigned Shift =MRI.getSpillRegisterOrder(Reg);

877 Mask |= 1 << Shift;

878 }

879

880autoI =M68k::addFrameReference(

881BuildMI(MBB,MI,DL, TII.get(M68k::MOVM32mp)).addImm(Mask), FI)

882 .setMIFlag(MachineInstr::FrameDestroy);

883

884// Append implicit registers and mem locations

885for (constauto &Info : CSI) {

886I.addReg(Info.getReg(),RegState::ImplicitDefine);

887M68k::addMemOperand(I,Info.getFrameIdx(), 0);

888 }

889

890returntrue;

891}

MRI

unsigned const MachineRegisterInfo * MRI

Definition:AArch64AdvSIMDScalarPass.cpp:105

MBB

MachineBasicBlock & MBB

Definition:ARMSLSHardening.cpp:71

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Definition:ARMSLSHardening.cpp:73

MBBI

MachineBasicBlock MachineBasicBlock::iterator MBBI

Definition:ARMSLSHardening.cpp:72

Alignment.h

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Info

Analysis containing CSE Info

Definition:CSEInfo.cpp:27

CommandLine.h

DataLayout.h

TII

const HexagonInstrInfo * TII

Definition:HexagonCopyToCombine.cpp:125

IRTranslator LLVM IR MI

Definition:IRTranslator.cpp:112

Function.h

isRegLiveIn

static bool isRegLiveIn(MachineBasicBlock &MBB, unsigned Reg)

Definition:M68kFrameLowering.cpp:178

isTailCallOpcode

static bool isTailCallOpcode(unsigned Opc)

Definition:M68kFrameLowering.cpp:664

findDeadCallerSavedReg

static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const M68kRegisterInfo *TRI)

Return a caller-saved register that isn't live when it reaches the "return" instruction.

Definition:M68kFrameLowering.cpp:139

M68kFrameLowering.h

This file contains the M68k declaration of TargetFrameLowering class.

M68kInstrBuilder.h

This file exposes functions that may be used with BuildMI from the MachineInstrBuilder....

M68kInstrInfo.h

This file contains the M68k implementation of the TargetInstrInfo class.

M68kMachineFunction.h

This file declares the M68k specific subclass of MachineFunctionInfo.

M68kSubtarget.h

This file declares the M68k specific subclass of TargetSubtargetInfo.

#define I(x, y, z)

Definition:MD5.cpp:58

MachineFrameInfo.h

MachineFunction.h

MachineInstrBuilder.h

MachineModuleInfo.h

MachineRegisterInfo.h

TRI

unsigned const TargetRegisterInfo * TRI

Definition:MachineSink.cpp:2029

FPReg

static constexpr Register FPReg

Definition:RISCVFrameLowering.cpp:105

Uses

Remove Loads Into Fake Uses

Definition:RemoveLoadsIntoFakeUses.cpp:75

assert

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

SmallSet.h

This file defines the SmallSet class.

TargetOptions.h

FramePtr

static const unsigned FramePtr

Definition:XCoreFrameLowering.cpp:32

llvm::ArrayRef

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Definition:ArrayRef.h:41

llvm::BitVector

Definition:BitVector.h:82

llvm::BitVector::set

BitVector & set()

Definition:BitVector.h:351

llvm::DebugLoc

A debug info location.

Definition:DebugLoc.h:33

llvm::Function::hasFnAttribute

bool hasFnAttribute(Attribute::AttrKind Kind) const

Return true if the function has the attribute.

Definition:Function.cpp:731

llvm::M68kFrameLowering::hasFPImpl

bool hasFPImpl(const MachineFunction &MF) const override

Return true if the specified function should have a dedicated frame pointer register.

Definition:M68kFrameLowering.cpp:45

llvm::M68kFrameLowering::determineCalleeSaves

void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override

This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...

Definition:M68kFrameLowering.cpp:771

llvm::M68kFrameLowering::emitEpilogue

void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override

Insert epilog code into the function.

Definition:M68kFrameLowering.cpp:668

llvm::M68kFrameLowering::emitSPUpdate

void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int64_t NumBytes, bool InEpilogue) const

Emit a series of instructions to increment / decrement the stack pointer by a constant value.

Definition:M68kFrameLowering.cpp:337

llvm::M68kFrameLowering::assignCalleeSavedSpillSlots

bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override

Allows target to override spill slot assignment logic.

Definition:M68kFrameLowering.cpp:801

llvm::M68kFrameLowering::spillCalleeSavedRegisters

bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override

Issues instruction(s) to spill all callee saved registers and returns true if it isn't possible / pro...

Definition:M68kFrameLowering.cpp:830

llvm::M68kFrameLowering::hasReservedCallFrame

bool hasReservedCallFrame(const MachineFunction &MF) const override

Under normal circumstances, when a frame pointer is not required, we reserve argument space for call ...

Definition:M68kFrameLowering.cpp:55

llvm::M68kFrameLowering::M68kFrameLowering

M68kFrameLowering(const M68kSubtarget &sti, Align Alignment)

Definition:M68kFrameLowering.cpp:38

llvm::M68kFrameLowering::mergeSPUpdates

int mergeSPUpdates(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, bool doMergeWithPrevious) const

Check the instruction before/after the passed instruction.

Definition:M68kFrameLowering.cpp:384

llvm::M68kFrameLowering::getFrameIndexReference

StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override

This method should return the base register and offset used to reference a frame index location.

Definition:M68kFrameLowering.cpp:78

llvm::M68kFrameLowering::eliminateCallFramePseudoInstr

MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...

Definition:M68kFrameLowering.cpp:229

llvm::M68kFrameLowering::emitPrologue

void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override

Insert prolog code into the function.

Definition:M68kFrameLowering.cpp:473

llvm::M68kFrameLowering::restoreCalleeSavedRegisters

bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override

Issues instruction(s) to restore all callee saved registers and returns true if it isn't possible / p...

Definition:M68kFrameLowering.cpp:865

llvm::M68kFrameLowering::canSimplifyCallFramePseudos

bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override

If there is a reserved call frame, the call frame pseudos can be simplified.

Definition:M68kFrameLowering.cpp:60

llvm::M68kFrameLowering::needsFrameIndexResolution

bool needsFrameIndexResolution(const MachineFunction &MF) const override

Definition:M68kFrameLowering.cpp:67

llvm::M68kMachineFunctionInfo

Definition:M68kMachineFunction.h:23

llvm::M68kMachineFunctionInfo::getRestoreBasePointerOffset

int getRestoreBasePointerOffset() const

Definition:M68kMachineFunction.h:79

llvm::M68kMachineFunctionInfo::getCalleeSavedFrameSize

unsigned getCalleeSavedFrameSize() const

Definition:M68kMachineFunction.h:81

llvm::M68kMachineFunctionInfo::getRestoreBasePointer

bool getRestoreBasePointer() const

Definition:M68kMachineFunction.h:77

llvm::M68kMachineFunctionInfo::setCalleeSavedFrameSize

void setCalleeSavedFrameSize(unsigned bytes)

Definition:M68kMachineFunction.h:82

llvm::M68kMachineFunctionInfo::getHasPushSequences

bool getHasPushSequences() const

Definition:M68kMachineFunction.h:99

llvm::M68kMachineFunctionInfo::getTCReturnAddrDelta

int getTCReturnAddrDelta() const

Definition:M68kMachineFunction.h:90

llvm::M68kRegisterInfo

Definition:M68kRegisterInfo.h:30

llvm::M68kRegisterInfo::getFrameRegister

Definition:M68kRegisterInfo.cpp:262

llvm::M68kRegisterInfo::getBaseRegister

unsigned getBaseRegister() const

Definition:M68kRegisterInfo.h:109

llvm::M68kRegisterInfo::hasBasePointer

bool hasBasePointer(const MachineFunction &MF) const

Definition:M68kRegisterInfo.cpp:228

llvm::M68kRegisterInfo::getStackRegister

unsigned getStackRegister() const

Definition:M68kRegisterInfo.h:108

llvm::M68kSubtarget

Definition:M68kSubtarget.h:44

llvm::M68kSubtarget::getSlotSize

unsigned getSlotSize() const

getSlotSize - Stack slot size in bytes.

Definition:M68kSubtarget.h:145

llvm::M68kSubtarget::getRegisterInfo

const M68kRegisterInfo * getRegisterInfo() const override

Definition:M68kSubtarget.h:161

llvm::MCCFIInstruction

Definition:MCDwarf.h:499

llvm::MCCFIInstruction::createDefCfaRegister

static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})

.cfi_def_cfa_register modifies a rule for computing CFA.

Definition:MCDwarf.h:582

llvm::MCCFIInstruction::createGnuArgsSize

static MCCFIInstruction createGnuArgsSize(MCSymbol *L, int64_t Size, SMLoc Loc={})

A special wrapper for .cfi_escape that indicates GNU_ARGS_SIZE.

Definition:MCDwarf.h:693

llvm::MCCFIInstruction::createOffset

static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})

.cfi_offset Previous value of Register is saved at offset Offset from CFA.

Definition:MCDwarf.h:617

llvm::MCCFIInstruction::cfiDefCfaOffset

static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int64_t Offset, SMLoc Loc={})

.cfi_def_cfa_offset modifies a rule for computing CFA.

Definition:MCDwarf.h:590

llvm::MCCFIInstruction::createAdjustCfaOffset

static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int64_t Adjustment, SMLoc Loc={})

.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...

Definition:MCDwarf.h:598

llvm::MCContext::getRegisterInfo

const MCRegisterInfo * getRegisterInfo() const

Definition:MCContext.h:414

llvm::MCInstrInfo::get

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Definition:MCInstrInfo.h:63

llvm::MCRegAliasIterator

MCRegAliasIterator enumerates all registers aliasing Reg.

Definition:MCRegisterInfo.h:747

llvm::MCRegAliasIterator::isValid

bool isValid() const

Definition:MCRegisterInfo.h:763

llvm::MCRegisterInfo

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Definition:MCRegisterInfo.h:149

llvm::MachineBasicBlock

Definition:MachineBasicBlock.h:125

llvm::MachineBasicBlock::liveins

iterator_range< livein_iterator > liveins() const

Definition:MachineBasicBlock.h:505

llvm::MachineBasicBlock::getFirstTerminator

iterator getFirstTerminator()

Returns an iterator to the first terminator instruction of this basic block.

Definition:MachineBasicBlock.cpp:244

llvm::MachineBasicBlock::begin

iterator begin()

Definition:MachineBasicBlock.h:355

llvm::MachineBasicBlock::findDebugLoc

DebugLoc findDebugLoc(instr_iterator MBBI)

Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.

Definition:MachineBasicBlock.cpp:1516

llvm::MachineBasicBlock::end

iterator end()

Definition:MachineBasicBlock.h:357

llvm::MachineBasicBlock::addLiveIn

void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())

Adds the specified register as a live in.

Definition:MachineBasicBlock.h:456

llvm::MachineBasicBlock::getParent

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

Definition:MachineBasicBlock.h:311

llvm::MachineBasicBlock::erase

instr_iterator erase(instr_iterator I)

Remove an instruction from the instruction list and delete it.

Definition:MachineBasicBlock.cpp:1443

llvm::MachineFrameInfo

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Definition:MachineFrameInfo.h:106

llvm::MachineFrameInfo::CreateFixedObject

int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)

Create a new object at a fixed location on the stack.

Definition:MachineFrameInfo.cpp:83

llvm::MachineFrameInfo::hasVarSizedObjects

bool hasVarSizedObjects() const

This method may be called any time after instruction selection is complete to determine if the stack ...

Definition:MachineFrameInfo.h:357

llvm::MachineFrameInfo::getStackSize

uint64_t getStackSize() const

Return the number of bytes that must be allocated to hold all of the fixed size frame objects.

Definition:MachineFrameInfo.h:587

llvm::MachineFrameInfo::hasCalls

bool hasCalls() const

Return true if the current function has any function calls.

Definition:MachineFrameInfo.h:621

llvm::MachineFrameInfo::isFrameAddressTaken

bool isFrameAddressTaken() const

This method may be called any time after instruction selection is complete to determine if there is a...

Definition:MachineFrameInfo.h:373

llvm::MachineFrameInfo::getMaxAlign

Align getMaxAlign() const

Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...

Definition:MachineFrameInfo.h:603

llvm::MachineFrameInfo::getObjectAlign

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

Definition:MachineFrameInfo.h:486

llvm::MachineFrameInfo::getCalleeSavedInfo

const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const

Returns a reference to call saved info vector for the current function.

Definition:MachineFrameInfo.h:806

llvm::MachineFrameInfo::hasStackObjects

bool hasStackObjects() const

Return true if there are any stack objects in this function.

Definition:MachineFrameInfo.h:352

llvm::MachineFrameInfo::CreateFixedSpillStackObject

int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)

Create a spill slot at a fixed location on the stack.

Definition:MachineFrameInfo.cpp:102

llvm::MachineFrameInfo::getObjectOffset

int64_t getObjectOffset(int ObjectIdx) const

Return the assigned stack offset of the specified object from the incoming stack pointer.

Definition:MachineFrameInfo.h:528

llvm::MachineFrameInfo::setOffsetAdjustment

void setOffsetAdjustment(int64_t Adj)

Set the correction for frame offsets.

Definition:MachineFrameInfo.h:599

llvm::MachineFunction

Definition:MachineFunction.h:267

llvm::MachineFunction::addFrameInst

unsigned addFrameInst(const MCCFIInstruction &Inst)

Definition:MachineFunction.cpp:334

llvm::MachineFunction::getSubtarget

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Definition:MachineFunction.h:733

llvm::MachineFunction::needsFrameMoves

bool needsFrameMoves() const

True if this function needs frame moves for debug or exceptions.

Definition:MachineFunction.cpp:691

llvm::MachineFunction::getFrameInfo

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

Definition:MachineFunction.h:749

llvm::MachineFunction::getContext

MCContext & getContext() const

Definition:MachineFunction.h:690

llvm::MachineFunction::callsEHReturn

bool callsEHReturn() const

Definition:MachineFunction.h:1225

llvm::MachineFunction::getRegInfo

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Definition:MachineFunction.h:743

llvm::MachineFunction::getFunction

Function & getFunction()

Return the LLVM function that this machine code represents.

Definition:MachineFunction.h:704

llvm::MachineFunction::getLandingPads

const std::vector< LandingPadInfo > & getLandingPads() const

Return a reference to the landing pad info for the current function.

Definition:MachineFunction.h:1250

llvm::MachineFunction::getInfo

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

Definition:MachineFunction.h:831

llvm::MachineFunction::getTarget

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

Definition:MachineFunction.h:729

llvm::MachineInstrBuilder

Definition:MachineInstrBuilder.h:71

llvm::MachineInstrBuilder::addCFIIndex

const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const

Definition:MachineInstrBuilder.h:249

llvm::MachineInstrBuilder::setMIFlag

const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const

Definition:MachineInstrBuilder.h:280

llvm::MachineInstrBuilder::addImm

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

Definition:MachineInstrBuilder.h:133

llvm::MachineInstrBuilder::addReg

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Definition:MachineInstrBuilder.h:99

llvm::MachineInstrBundleIterator< MachineInstr >

llvm::MachineInstr

Representation of each machine instruction.

Definition:MachineInstr.h:71

llvm::MachineInstr::FrameDestroy

@ FrameDestroy

Definition:MachineInstr.h:89

llvm::MachineInstr::FrameSetup

@ FrameSetup

Definition:MachineInstr.h:87

llvm::MachineOperand

MachineOperand class - Representation of each machine instruction operand.

Definition:MachineOperand.h:48

llvm::MachineOperand::isReg

bool isReg() const

isReg - Tests if this is a MO_Register operand.

Definition:MachineOperand.h:329

llvm::MachineOperand::isDef

bool isDef() const

Definition:MachineOperand.h:384

llvm::MachineOperand::getReg

getReg - Returns the register number.

Definition:MachineOperand.h:369

llvm::MachineRegisterInfo

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Definition:MachineRegisterInfo.h:51

llvm::MachineRegisterInfo::isLiveIn

bool isLiveIn(Register Reg) const

Definition:MachineRegisterInfo.cpp:450

llvm::MutableArrayRef

MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...

Definition:ArrayRef.h:310

llvm::RegScavenger

Definition:RegisterScavenging.h:34

llvm::Register

Wrapper class representing virtual and physical registers.

Definition:Register.h:19

llvm::SmallSet

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

Definition:SmallSet.h:132

llvm::StackOffset

StackOffset holds a fixed and a scalable offset in bytes.

Definition:TypeSize.h:33

llvm::StackOffset::getFixed

int64_t getFixed() const

Returns the fixed component of the stack.

Definition:TypeSize.h:49

llvm::TargetFrameLowering

Information about stack frame layout on the target.

Definition:TargetFrameLowering.h:45

llvm::TargetFrameLowering::getStackAlignment

unsigned getStackAlignment() const

getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...

Definition:TargetFrameLowering.h:100

llvm::TargetFrameLowering::hasFP

bool hasFP(const MachineFunction &MF) const

hasFP - Return true if the specified function should have a dedicated frame pointer register.

Definition:TargetFrameLowering.h:285

llvm::TargetFrameLowering::determineCalleeSaves

virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const

This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...

Definition:TargetFrameLoweringImpl.cpp:95

llvm::TargetFrameLowering::getOffsetOfLocalArea

int getOffsetOfLocalArea() const

getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...

Definition:TargetFrameLowering.h:144

llvm::TargetInstrInfo::getCallFrameDestroyOpcode

unsigned getCallFrameDestroyOpcode() const

Definition:TargetInstrInfo.h:222

llvm::TargetMachine::Options

TargetOptions Options

Definition:TargetMachine.h:118

llvm::TargetOptions::DisableFramePointerElim

bool DisableFramePointerElim(const MachineFunction &MF) const

DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...

Definition:TargetOptionsImpl.cpp:24

llvm::TargetRegisterClass

Definition:TargetRegisterInfo.h:44

llvm::TargetRegisterInfo

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Definition:TargetRegisterInfo.h:235

uint64_t

TargetMachine.h

llvm::M68k::addMemOperand

static const MachineInstrBuilder & addMemOperand(const MachineInstrBuilder &MIB, int FI, int Offset=0)

Definition:M68kInstrBuilder.h:76

llvm::M68k::addFrameReference

static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0)

addFrameReference - This function is used to add a reference to the base of an abstract object on the...

Definition:M68kInstrBuilder.h:59

llvm::M68k::addRegIndirectWithDisp

static const MachineInstrBuilder & addRegIndirectWithDisp(const MachineInstrBuilder &MIB, Register Reg, bool IsKill, int Offset)

addRegIndirectWithDisp - This function is used to add a memory reference of the form (Offset,...

Definition:M68kInstrBuilder.h:49

llvm::RegState::Implicit

@ Implicit

Not emitted register (e.g. carry, or temporary result).

Definition:MachineInstrBuilder.h:48

llvm::RegState::ImplicitDefine

@ ImplicitDefine

Definition:MachineInstrBuilder.h:65

llvm::RegState::Kill

@ Kill

The last use of a register.

Definition:MachineInstrBuilder.h:50

llvm::RegState::ImplicitKill

@ ImplicitKill

Definition:MachineInstrBuilder.h:66

llvm::X86Disassembler::Reg

Reg

All possible values of the reg field in the ModR/M byte.

Definition:X86DisassemblerDecoder.h:621

llvm

This is an optimization pass for GlobalISel generic memory operations.

Definition:AddressRanges.h:18

llvm::Offset

@ Offset

Definition:DWP.cpp:480

llvm::BuildMI

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

Definition:MachineInstrBuilder.h:373

llvm::ExceptionHandling::DwarfCFI

@ DwarfCFI

DWARF-like instruction based exceptions.

llvm::any_of

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

Definition:STLExtras.h:1746

llvm::alignTo

uint64_t alignTo(uint64_t Size, Align A)

Returns a multiple of A needed to store Size bytes.

Definition:Alignment.h:155

llvm::Align

This struct is a compact representation of a valid (non-zero power of two) alignment.

Definition:Alignment.h:39

llvm::Align::value

uint64_t value() const

This is a hole in the type system and should not be abused.

Definition:Alignment.h:85

llvm::MachineBasicBlock::RegisterMaskPair

Pair of physical register and lane mask.

Definition:MachineBasicBlock.h:130