1//===- LoadStoreOpt.cpp ----------- Generic memory optimizations -*- C++ -*-==// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7//===----------------------------------------------------------------------===// 9/// This file implements the LoadStoreOpt optimization pass. 10//===----------------------------------------------------------------------===// 41#define DEBUG_TYPE "loadstore-opt" 45using namespaceMIPatternMatch;
47STATISTIC(NumStoresMerged,
"Number of stores merged");
66 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
95Info.setOffset(RHSCst->Value.getSExtValue());
97// Just recognize a simple case for now. In future we'll need to match 98// indexing patterns for base + index + constant. 99Info.setIndex(PtrAddRHS);
107auto *LdSt1 = dyn_cast<GLoadStore>(&MI1);
108auto *LdSt2 = dyn_cast<GLoadStore>(&MI2);
125// If the size of memory access is unknown, do not use it to do analysis. 126// One example of unknown size memory access is to load/store scalable 127// vector objects on the stack. 128// BasePtr1 is PtrDiff away from BasePtr0. They alias if none of the 129// following situations arise: 133// ========PtrDiff========> 134 IsAlias = !((int64_t)Size1.
getValue() <= PtrDiff);
140// =====(-PtrDiff)====> 141 IsAlias = !((PtrDiff + (int64_t)Size2.
getValue()) <= 0);
147// If both BasePtr0 and BasePtr1 are FrameIndexes, we will not be 148// able to calculate their relative offset if at least one arises 149// from an alloca. However, these allocas cannot overlap and we 150// can infer there is no alias. 153if (!Base0Def || !Base1Def)
154returnfalse;
// Couldn't tell anything. 157if (Base0Def->getOpcode() != Base1Def->getOpcode())
160if (Base0Def->getOpcode() == TargetOpcode::G_FRAME_INDEX) {
162// If the bases have the same frame index but we couldn't find a 163// constant offset, (indices are different) be conservative. 164if (Base0Def != Base1Def &&
172// This implementation is a lot more primitive than the SDAG one for now. 173// FIXME: what about constant pools? 174if (Base0Def->getOpcode() == TargetOpcode::G_GLOBAL_VALUE) {
175auto GV0 = Base0Def->getOperand(1).getGlobal();
176auto GV1 = Base1Def->getOperand(1).getGlobal();
183// Can't tell anything about aliasing. 191structMemUseCharacteristics {
200auto getCharacteristics =
202if (
constauto *LS = dyn_cast<GLoadStore>(
MI)) {
205// No pre/post-inc addressing modes are considered here, unlike in SDAG. 208 BaseReg = LS->getPointerReg();
213return {LS->isVolatile(), LS->isAtomic(), BaseReg,
216// FIXME: support recognizing lifetime instructions. 218return {
false/*isvolatile*/,
221 (int64_t)0
/*offset*/,
225 MemUseCharacteristics MUC0 = getCharacteristics(&
MI),
226 MUC1 = getCharacteristics(&
Other);
228// If they are to the same address, then they must be aliases. 229if (MUC0.BasePtr.isValid() && MUC0.BasePtr == MUC1.BasePtr &&
230 MUC0.Offset == MUC1.Offset)
233// If they are both volatile then they cannot be reordered. 234if (MUC0.IsVolatile && MUC1.IsVolatile)
237// Be conservative about atomics for the moment 238// TODO: This is way overconservative for unordered atomics (see D66309) 239if (MUC0.IsAtomic && MUC1.IsAtomic)
242// If one operation reads from invariant memory, and the other may store, they 244if (MUC0.MMO && MUC1.MMO) {
245if ((MUC0.MMO->isInvariant() && MUC1.MMO->isStore()) ||
246 (MUC1.MMO->isInvariant() && MUC0.MMO->isStore()))
250// If NumBytes is scalable and offset is not 0, conservatively return may 252if ((MUC0.NumBytes.isScalable() && MUC0.Offset != 0) ||
253 (MUC1.NumBytes.isScalable() && MUC1.Offset != 0))
256constbool BothNotScalable =
257 !MUC0.NumBytes.isScalable() && !MUC1.NumBytes.isScalable();
259// Try to prove that there is aliasing, or that there is no aliasing. Either 260// way, we can return now. If nothing can be proved, proceed with more tests. 262if (BothNotScalable &&
266// The following all rely on MMO0 and MMO1 being valid. 267if (!MUC0.MMO || !MUC1.MMO)
270// FIXME: port the alignment based alias analysis from SDAG's isAlias(). 271 int64_t SrcValOffset0 = MUC0.MMO->getOffset();
272 int64_t SrcValOffset1 = MUC1.MMO->getOffset();
275if (AA && MUC0.MMO->getValue() && MUC1.MMO->getValue() && Size0.
hasValue() &&
277// Use alias analysis information. 278 int64_t MinOffset = std::min(SrcValOffset0, SrcValOffset1);
290MemoryLocation(MUC1.MMO->getValue(), Loc1, MUC1.MMO->getAAInfo())))
294// Otherwise we have to assume they alias. 298/// Returns true if the instruction creates an unavoidable hazard that 299/// forces a boundary between store merge candidates. 301returnMI.hasUnmodeledSideEffects() ||
MI.hasOrderedMemoryRef();
305// Try to merge all the stores in the vector, splitting into separate segments 307assert(StoresToMerge.
size() > 1 &&
"Expected multiple stores to merge");
308LLT OrigTy = MRI->
getType(StoresToMerge[0]->getValueReg());
309LLT PtrTy = MRI->
getType(StoresToMerge[0]->getPointerReg());
311// Ensure the legal store info is computed for this address space. 312 initializeStoreMergeTargetInfo(AS);
313constauto &LegalSizes = LegalStoreSizes[AS];
316for (
auto *StoreMI : StoresToMerge)
320bool AnyMerged =
false;
324// Compute the biggest store we can generate to handle the number of stores. 325unsigned MergeSizeBits;
326for (MergeSizeBits = MaxSizeBits; MergeSizeBits > 1; MergeSizeBits /= 2) {
330if (LegalSizes.size() > MergeSizeBits && LegalSizes[MergeSizeBits] &&
333break;
// We can generate a MergeSize bits store. 336return AnyMerged;
// No greater merge. 338unsigned NumStoresToMerge = MergeSizeBits / OrigTy.
getSizeInBits();
339// Perform the actual merging. 341 StoresToMerge.begin(), StoresToMerge.begin() + NumStoresToMerge);
342 AnyMerged |= doSingleStoreMerge(SingleMergeStores);
343 StoresToMerge.erase(StoresToMerge.begin(),
344 StoresToMerge.begin() + NumStoresToMerge);
345 }
while (StoresToMerge.size() > 1);
349bool LoadStoreOpt::isLegalOrBeforeLegalizer(
constLegalityQuery &Query,
352// If the instruction is unsupported, it can't be legalized at all. 355return IsPreLegalizer || Action == LegalizeAction::Legal;
360// We know that all the stores are consecutive and there are no aliasing 361// operations in the range. However, the values that are being stored may be 362// generated anywhere before each store. To ensure we have the values 363// available, we materialize the wide value and new store at the place of the 364// final store in the merge sequence. 365GStore *FirstStore = Stores[0];
366constunsigned NumStores = Stores.
size();
371// For each store, compute pairwise merged debug locs. 379// If all of the store values are constants, then create a wide constant 380// directly. Otherwise, we need to generate some instructions to merge the 381// existing values together into a wider type. 383for (
auto *Store : Stores) {
387 ConstantVals.
clear();
396if (ConstantVals.
empty()) {
397// Mimic the SDAG behaviour here and don't try to do anything for unknown 398// values. In future, we should also support the cases of loads and 399// extracted vector elements. 404// Check if our wide constant is legal. 405if (!isLegalOrBeforeLegalizer({TargetOpcode::G_CONSTANT, {WideValueTy}}, *MF))
409// Insert the smaller constant into the corresponding position in the 418 <<
" stores into merged store: " << *NewStore);
420 NumStoresMerged += Stores.size();
427R <<
"Merged " <<
NV(
"NumMerged", Stores.size()) <<
" stores of " 429 <<
" bytes into a single store of " 434for (
auto *
MI : Stores)
435 InstsToErase.insert(
MI);
439bool LoadStoreOpt::processMergeCandidate(StoreMergeCandidate &
C) {
440if (
C.Stores.size() < 2) {
445LLVM_DEBUG(
dbgs() <<
"Checking store merge candidate with " <<
C.Stores.size()
446 <<
" stores, starting with " << *
C.Stores[0]);
447// We know that the stores in the candidate are adjacent. 448// Now we need to check if any potential aliasing instructions recorded 449// during the search alias with load/stores added to the candidate after. 450// For example, if we have the candidate: 451// C.Stores = [ST1, ST2, ST3, ST4] 452// and after seeing ST2 we saw a load LD1, which did not alias with ST1 or 453// ST2, then we would have recorded it into the PotentialAliases structure 454// with the associated index value of "1". Then we see ST3 and ST4 and add 455// them to the candidate group. We know that LD1 does not alias with ST1 or 456// ST2, since we already did that check. However we don't yet know if it 457// may alias ST3 and ST4, so we perform those checks now. 460auto DoesStoreAliasWithPotential = [&](
unsignedIdx,
GStore &CheckStore) {
461for (
auto AliasInfo :
reverse(
C.PotentialAliases)) {
463unsigned PreCheckedIdx = AliasInfo.second;
464if (
static_cast<unsigned>(
Idx) < PreCheckedIdx) {
465// Once our store index is lower than the index associated with the 466// potential alias, we know that we've already checked for this alias 467// and all of the earlier potential aliases too. 470// Need to check this alias. 480// Start from the last store in the group, and check if it aliases with any 481// of the potential aliasing operations in the list. 482for (
int StoreIdx =
C.Stores.size() - 1; StoreIdx >= 0; --StoreIdx) {
483auto *CheckStore =
C.Stores[StoreIdx];
484if (DoesStoreAliasWithPotential(StoreIdx, *CheckStore))
490 <<
" stores remaining after alias checks. Merging...\n");
492// Now we've checked for aliasing hazards, merge any stores left. 494if (StoresToMerge.
size() < 2)
496return mergeStores(StoresToMerge);
500 StoreMergeCandidate &
C) {
504 return instMayAlias(MI, *OtherMI, *MRI, AA);
508void LoadStoreOpt::StoreMergeCandidate::addPotentialAlias(
MachineInstr &
MI) {
509 PotentialAliases.emplace_back(std::make_pair(&
MI, Stores.size() - 1));
512bool LoadStoreOpt::addStoreToCandidate(
GStore &StoreMI,
513 StoreMergeCandidate &
C) {
514// Check if the given store writes to an adjacent address, and other 519// Only handle scalars. 523// Don't allow truncating stores for now. 527// Avoid adding volatile or ordered stores to the candidate. We already have a 528// check for this in instMayAlias() but that only get's called later between 529// potential aliasing hazards. 536if (
C.Stores.empty()) {
537C.BasePtr = StoreBase;
538if (!BIO.hasValidOffset()) {
539C.CurrentLowestOffset = 0;
541C.CurrentLowestOffset = BIO.getOffset();
543// This is the first store of the candidate. 544// If the offset can't possibly allow for a lower addressed store with the 545// same base, don't bother adding it. 546if (BIO.hasValidOffset() &&
549C.Stores.emplace_back(&StoreMI);
555// Check the store is the same size as the existing ones in the candidate. 564// There are other stores in the candidate. Check that the store address 565// writes to the next lowest adjacent address. 566if (
C.BasePtr != StoreBase)
568// If we don't have a valid offset, we can't guarantee to be an adjacent 570if (!BIO.hasValidOffset())
572if ((
C.CurrentLowestOffset -
573static_cast<int64_t
>(ValueTy.
getSizeInBytes())) != BIO.getOffset())
576// This writes to an adjacent address. Allow it. 577C.Stores.emplace_back(&StoreMI);
585// Walk through the block bottom-up, looking for merging candidates. 586 StoreMergeCandidate Candidate;
588if (InstsToErase.contains(&
MI))
591if (
auto *StoreMI = dyn_cast<GStore>(&
MI)) {
592// We have a G_STORE. Add it to the candidate if it writes to an adjacent 594if (!addStoreToCandidate(*StoreMI, Candidate)) {
595// Store wasn't eligible to be added. May need to record it as a 597if (operationAliasesWithCandidate(*StoreMI, Candidate)) {
598 Changed |= processMergeCandidate(Candidate);
601 Candidate.addPotentialAlias(*StoreMI);
606// If we don't have any stores yet, this instruction can't pose a problem. 607if (Candidate.Stores.empty())
610// We're dealing with some other kind of instruction. 612 Changed |= processMergeCandidate(Candidate);
613 Candidate.Stores.clear();
617if (!
MI.mayLoadOrStore())
620if (operationAliasesWithCandidate(
MI, Candidate)) {
621// We have a potential alias, so process the current candidate if we can 622// and then continue looking for a new candidate. 623 Changed |= processMergeCandidate(Candidate);
627// Record this instruction as a potential alias for future stores that are 628// added to the candidate. 629 Candidate.addPotentialAlias(
MI);
632// Process any candidate left after finishing searching the entire block. 633 Changed |= processMergeCandidate(Candidate);
635// Erase instructions now that we're no longer iterating over the block. 636for (
auto *
MI : InstsToErase)
637MI->eraseFromParent();
638 InstsToErase.clear();
642/// Check if the store \p Store is a truncstore that can be merged. That is, 643/// it's a store of a shifted value of \p SrcVal. If \p SrcVal is an empty 644/// Register then it does not need to match and SrcVal is set to the source 646/// On match, returns the start byte offset of the \p SrcVal that is being 648static std::optional<int64_t>
655// The shift amount must be a constant multiple of the narrow type. 656// It is translated to the offset address in the wide source value "y". 658// x = G_LSHR y, ShiftAmtC 666if (!SrcVal.
isValid() || TruncVal == SrcVal) {
669return 0;
// If it's the lowest index store. 674unsigned NarrowBits = Store.getMMO().getMemoryType().getScalarSizeInBits();
675if (ShiftAmt % NarrowBits != 0)
677constunsignedOffset = ShiftAmt / NarrowBits;
679if (SrcVal.
isValid() && FoundSrcVal != SrcVal)
683 SrcVal = FoundSrcVal;
684elseif (
MRI.getType(SrcVal) !=
MRI.getType(FoundSrcVal))
689/// Match a pattern where a wide type scalar value is stored by several narrow 690/// stores. Fold it into a single store or a BSWAP and a store if the targets 693/// Assuming little endian target: 696/// p[0] = (val >> 0) & 0xFF; 697/// p[1] = (val >> 8) & 0xFF; 698/// p[2] = (val >> 16) & 0xFF; 699/// p[3] = (val >> 24) & 0xFF; 705/// p[0] = (val >> 24) & 0xFF; 706/// p[1] = (val >> 16) & 0xFF; 707/// p[2] = (val >> 8) & 0xFF; 708/// p[3] = (val >> 0) & 0xFF; 710/// *((i32)p) = BSWAP(val); 711bool LoadStoreOpt::mergeTruncStore(
GStore &StoreMI,
715// We only handle merging simple stores of 1-4 bytes. 729// We do a simple search for mergeable stores prior to this one. 730// Any potential alias hazard along the way terminates the search. 734// 1) a (store(trunc(...))) 735// 2) of an LSHR/ASHR of a single wide value, by the appropriate shift to get 736// the partial value stored. 737// 3) where the offsets form either a little or big-endian sequence. 739auto &LastStore = StoreMI;
741// The single base pointer that all stores must use. 744if (!
mi_match(LastStore.getPointerReg(), *MRI,
746 BaseReg = LastStore.getPointerReg();
750GStore *LowestIdxStore = &LastStore;
751 int64_t LowestIdxOffset = LastOffset;
756returnfalse;
// Didn't match a trunc. 760// The wide type might not be a multiple of the memory type, e.g. s48 and s32. 763constunsigned NumStoresRequired =
767 OffsetMap[*LowestShiftAmt] = LastOffset;
770constint MaxInstsToCheck = 10;
771int NumInstsChecked = 0;
772for (
autoII = ++LastStore.getReverseIterator();
773II != LastStore.getParent()->rend() && NumInstsChecked < MaxInstsToCheck;
777if ((NewStore = dyn_cast<GStore>(&*
II))) {
780 }
elseif (
II->isLoadFoldBarrier() ||
II->mayLoad()) {
783continue;
// This is a safe instruction we can look past. 788// Check we're storing to the same base + some offset. 794if (BaseReg != NewBaseReg)
800if (MemOffset < LowestIdxOffset) {
801 LowestIdxOffset = MemOffset;
802 LowestIdxStore = NewStore;
805// Map the offset in the store and the offset in the combined value, and 806// early return if it has been set before. 807if (*ShiftByteOffset < 0 || *ShiftByteOffset >= NumStoresRequired ||
810 OffsetMap[*ShiftByteOffset] = MemOffset;
813// Reset counter since we've found a matching inst. 815if (FoundStores.
size() == NumStoresRequired)
819if (FoundStores.
size() != NumStoresRequired) {
820if (FoundStores.
size() == 1)
822// We didn't find enough stores to merge into the size of the original 823// source value, but we may be able to generate a smaller store if we 824// truncate the source value. 828unsigned NumStoresFound = FoundStores.
size();
830constauto &
DL = LastStore.getMF()->getDataLayout();
831auto &
C = LastStore.getMF()->getFunction().getContext();
832// Check that a store of the wide type is both allowed and fast on the target 836if (!Allowed || !
Fast)
839// Check if the pieces of the value are going to the expected places in memory 840// to merge the stores. 842auto checkOffsets = [&](
bool MatchLittleEndian) {
843if (MatchLittleEndian) {
844for (
unsigned i = 0; i != NumStoresFound; ++i)
845if (OffsetMap[i] != i * (NarrowBits / 8) + LowestIdxOffset)
847 }
else {
// MatchBigEndian by reversing loop counter. 848for (
unsigned i = 0, j = NumStoresFound - 1; i != NumStoresFound;
850if (OffsetMap[j] != i * (NarrowBits / 8) + LowestIdxOffset)
856// Check if the offsets line up for the native data layout of this target. 857bool NeedBswap =
false;
858bool NeedRotate =
false;
859if (!checkOffsets(
DL.isLittleEndian())) {
860// Special-case: check if byte offsets line up for the opposite endian. 861if (NarrowBits == 8 && checkOffsets(
DL.isBigEndian()))
863elseif (NumStoresFound == 2 && checkOffsets(
DL.isBigEndian()))
870 !isLegalOrBeforeLegalizer({TargetOpcode::G_BSWAP, {WideStoreTy}}, *MF))
873 !isLegalOrBeforeLegalizer(
874 {TargetOpcode::G_ROTR, {WideStoreTy, WideStoreTy}}, *MF))
879if (WideStoreTy != MRI->
getType(WideSrcVal))
884 }
elseif (NeedRotate) {
886"Unexpected type for rotate");
897// Erase the old stores. 898for (
auto *ST : FoundStores) {
899ST->eraseFromParent();
909// Walk up the block so we can see the most eligible stores. 911if (
auto *StoreMI = dyn_cast<GStore>(&
MI))
914for (
auto *StoreMI : Stores) {
915if (DeletedStores.
count(StoreMI))
917if (mergeTruncStore(*StoreMI, DeletedStores))
926 Changed |= mergeBlockStores(BB);
927 Changed |= mergeTruncStoresBlock(BB);
930// Erase all dead instructions left over by the merging. 943void LoadStoreOpt::initializeStoreMergeTargetInfo(
unsigned AddrSpace) {
944// Query the legalizer info to record what store types are legal. 945// We record this because we don't want to bother trying to merge stores into 946// illegal ones, which would just result in being split again. 948if (LegalStoreSizes.count(AddrSpace)) {
950return;
// Already cached sizes for this address space. 953// Need to reserve at least MaxStoreSizeToForm + 1 bits. 955constauto &LI = *MF->getSubtarget().getLegalizerInfo();
956constauto &
DL = MF->getFunction().getDataLayout();
959// We assume that we're not going to be generating any stores wider than 960// MaxStoreSizeToForm bits for now. 969 LegalSizes.set(
Size);
971assert(LegalSizes.any() &&
"Expected some store sizes to be legal!");
972 LegalStoreSizes[AddrSpace] = LegalSizes;
976// If the ISel pipeline failed, do not bother running that pass. 986 Changed |= mergeFunctionStores(MF);
988 LegalStoreSizes.clear();
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Atomic ordering constants.
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Performs the initial survey of the specified function
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
Interface for Targets to specify which operations they can successfully select and how the others sho...
Generic memory optimizations
const unsigned MaxStoreSizeToForm
static std::optional< int64_t > getTruncStoreByteOffset(GStore &Store, Register &SrcVal, MachineRegisterInfo &MRI)
Check if the store Store is a truncstore that can be merged.
static bool isInstHardMergeHazard(MachineInstr &MI)
Returns true if the instruction creates an unavoidable hazard that forces a boundary between store me...
Implement a low-level type suitable for MachineInstr level instruction selection.
Contains matchers for matching SSA Machine Instructions.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
This file provides utility analysis objects describing memory locations.
uint64_t IntrinsicInst * II
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallPtrSet class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
This file describes how to lower LLVM code to machine code.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
A trivial helper function to check to see if the specified pointers are no-alias.
Class for arbitrary precision integers.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
void setPreservesAll()
Set by analyses that do not transform their input at all.
static DILocation * getMergedLocation(DILocation *LocA, DILocation *LocB)
When two instructions are combined into a single instruction we also need to combine the original loc...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Helper struct to store a base, index and offset that forms an address.
int64_t getOffset() const
bool hasValidOffset() const
Register getPointerReg() const
Get the source register of the pointer value.
MachineMemOperand & getMMO() const
Get the MachineMemOperand on this instruction.
LocationSize getMemSizeInBits() const
Returns the size in bits of the memory access.
bool isSimple() const
Returns true if the memory operation is neither atomic or volatile.
Register getValueReg() const
Get the stored value register.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr unsigned getAddressSpace() const
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
LegalizeActionStep getAction(const LegalityQuery &Query) const
Determine what action should be taken to legalize the described instruction.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
static LocationSize precise(uint64_t Value)
static constexpr LocationSize beforeOrAfterPointer()
Any location before or after the base pointer (but still within the underlying object).
TypeSize getValue() const
reverse_iterator rbegin()
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineFunctionProperties & getProperties() const
Get the function properties.
MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTR Src, Amt.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0)
Build and insert Dst = G_BSWAP Src0.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
void setInstrAndDebugLoc(MachineInstr &MI)
Set the insertion point to before MI, and set the debug loc to MI's loc.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_TRUNC Op.
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
void setMF(MachineFunction &MF)
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Register getReg(unsigned Idx) const
Get the register for the operand index.
Representation of each machine instruction.
const MachineBasicBlock * getParent() const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
A description of a memory reference used in the backend.
LLT getMemoryType() const
Return the memory type of the memory reference.
const MachinePointerInfo & getPointerInfo() const
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
The optimization diagnostic interface.
Diagnostic information for applied optimization remarks.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Representation for a specific memory location.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const
Returns if it's reasonable to merge stores to MemVT size.
virtual const LegalizerInfo * getLegalizerInfo() const
virtual const TargetLowering * getTargetLowering() const
The instances of the Type class are immutable: once they are created, they are never changed.
constexpr ScalarTy getFixedValue() const
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
constexpr bool any(E Val)
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
bool aliasIsKnownForLoadStore(const MachineInstr &MI1, const MachineInstr &MI2, bool &IsAlias, MachineRegisterInfo &MRI)
Compute whether or not a memory access at MI1 aliases with an access at MI2.
BaseIndexOffset getPointerInfo(Register Ptr, MachineRegisterInfo &MRI)
Returns a BaseIndexOffset which describes the pointer in Ptr.
bool instMayAlias(const MachineInstr &MI, const MachineInstr &Other, MachineRegisterInfo &MRI, AliasAnalysis *AA)
Returns true if the instruction MI may alias Other.
@ Legal
The operation is expected to be selectable directly by the target, and no transformation is necessary...
@ Unsupported
This operation is completely unsupported on the target.
operand_type_match m_Reg()
ConstantMatch< APInt > m_ICst(APInt &Cst)
BinaryOp_match< LHS, RHS, TargetOpcode::G_ASHR, false > m_GAShr(const LHS &L, const RHS &R)
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
BinaryOp_match< LHS, RHS, TargetOpcode::G_PTR_ADD, false > m_GPtrAdd(const LHS &L, const RHS &R)
Or< Preds... > m_any_of(Preds &&... preds)
BinaryOp_match< LHS, RHS, TargetOpcode::G_LSHR, false > m_GLShr(const LHS &L, const RHS &R)
UnaryOp_match< SrcTy, TargetOpcode::G_TRUNC > m_GTrunc(const SrcTy &Src)
DiagnosticInfoOptimizationBase::Argument NV
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
auto reverse(ContainerTy &&C)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
EVT getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx)
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Implement std::hash so that hash_code can be used in STL containers.
The LegalityQuery object bundles together all the information that's needed to decide whether a given...
LegalizeAction Action
The action to take or the final answer.
