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1//===-------------- GCNRewritePartialRegUses.cpp --------------------------===//

2//

3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

4// See https://llvm.org/LICENSE.txt for license information.

5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

6//

7//===----------------------------------------------------------------------===//

8/// \file

9/// RenameIndependentSubregs pass leaves large partially used super registers,

10/// for example:

11/// undef %0.sub4:VReg_1024 = ...

12/// %0.sub5:VReg_1024 = ...

13/// %0.sub6:VReg_1024 = ...

14/// %0.sub7:VReg_1024 = ...

15/// use %0.sub4_sub5_sub6_sub7

16/// use %0.sub6_sub7

17///

18/// GCNRewritePartialRegUses goes right after RenameIndependentSubregs and

19/// rewrites such partially used super registers with registers of minimal size:

20/// undef %0.sub0:VReg_128 = ...

21/// %0.sub1:VReg_128 = ...

22/// %0.sub2:VReg_128 = ...

23/// %0.sub3:VReg_128 = ...

24/// use %0.sub0_sub1_sub2_sub3

25/// use %0.sub2_sub3

26///

27/// This allows to avoid subreg lanemasks tracking during register pressure

28/// calculation and creates more possibilities for the code unaware of lanemasks

29//===----------------------------------------------------------------------===//

31#include "AMDGPU.h"

32#include "MCTargetDesc/AMDGPUMCTargetDesc.h"

33#include "SIRegisterInfo.h"

34#include "llvm/CodeGen/LiveInterval.h"

35#include "llvm/CodeGen/LiveIntervals.h"

36#include "llvm/CodeGen/MachineFunctionPass.h"

37#include "llvm/CodeGen/MachineRegisterInfo.h"

38#include "llvm/CodeGen/TargetInstrInfo.h"

39#include "llvm/Pass.h"

41using namespacellvm;

43#define DEBUG_TYPE "rewrite-partial-reg-uses"

45namespace{

47classGCNRewritePartialRegUses :publicMachineFunctionPass {

48public:

49staticcharID;

50 GCNRewritePartialRegUses() :MachineFunctionPass(ID) {}

52StringRef getPassName() const override{

53return"Rewrite Partial Register Uses";

54 }

56voidgetAnalysisUsage(AnalysisUsage &AU) const override{

57 AU.setPreservesCFG();

58 AU.addPreserved<LiveIntervalsWrapperPass>();

59 AU.addPreserved<SlotIndexesWrapperPass>();

60MachineFunctionPass::getAnalysisUsage(AU);

61 }

63boolrunOnMachineFunction(MachineFunction &MF)override;

65private:

66MachineRegisterInfo *MRI;

67constSIRegisterInfo *TRI;

68constTargetInstrInfo *TII;

69LiveIntervals *LIS;

71 /// Rewrite partially used register Reg by shifting all its subregisters to

72 /// the right and replacing the original register with a register of minimal

73 /// size. Return true if the change has been made.

74bool rewriteReg(Register Reg)const;

76 /// Value type for SubRegMap below.

77structSubRegInfo {

78 /// Register class required to hold the value stored in the SubReg.

79constTargetRegisterClass *RC;

81 /// Index for the right-shifted subregister. If 0 this is the "covering"

82 /// subreg i.e. subreg that covers all others. Covering subreg becomes the

83 /// whole register after the replacement.

84unsignedSubReg = AMDGPU::NoSubRegister;

85 SubRegInfo(constTargetRegisterClass *RC_ =nullptr) : RC(RC_) {}

86 };

88 /// Map OldSubReg -> { RC, NewSubReg }. Used as in/out container.

89usingSubRegMap =SmallDenseMap<unsigned, SubRegInfo>;

91 /// Given register class RC and the set of used subregs as keys in the SubRegs

92 /// map return new register class and indexes of right-shifted subregs as

93 /// values in SubRegs map such that the resulting regclass would contain

94 /// registers of minimal size.

95constTargetRegisterClass *getMinSizeReg(constTargetRegisterClass *RC,

96 SubRegMap &SubRegs)const;

98 /// Given regclass RC and pairs of [OldSubReg, SubRegRC] in SubRegs try to

99 /// find new regclass such that:

100 /// 1. It has subregs obtained by shifting each OldSubReg by RShift number

101 /// of bits to the right. Every "shifted" subreg should have the same

102 /// SubRegRC. If CoverSubregIdx is not zero it's a subreg that "covers"

103 /// all other subregs in pairs. Basically such subreg becomes a whole

104 /// register.

105 /// 2. Resulting register class contains registers of minimal size but not

106 /// less than RegNumBits.

107 ///

108 /// SubRegs is map of OldSubReg -> [SubRegRC, NewSubReg] and is used as in/out

109 /// parameter:

110 /// OldSubReg - input parameter,

111 /// SubRegRC - input parameter (cannot be null),

112 /// NewSubReg - output, contains shifted subregs on return.

113constTargetRegisterClass *

114 getRegClassWithShiftedSubregs(constTargetRegisterClass *RC,unsigned RShift,

115unsigned RegNumBits,unsigned CoverSubregIdx,

116 SubRegMap &SubRegs)const;

117

118 /// Update live intervals after rewriting OldReg to NewReg with SubRegs map

119 /// describing OldSubReg -> NewSubReg mapping.

120void updateLiveIntervals(Register OldReg,Register NewReg,

121 SubRegMap &SubRegs)const;

122

123 /// Helper methods.

124

125 /// Return reg class expected by a MO's parent instruction for a given MO.

126constTargetRegisterClass *getOperandRegClass(MachineOperand &MO)const;

127

128 /// Find right-shifted by RShift amount version of the SubReg if it exists,

129 /// return 0 otherwise.

130unsigned shiftSubReg(unsignedSubReg,unsigned RShift)const;

131

132 /// Find subreg index with a given Offset and Size, return 0 if there is no

133 /// such subregister index. The result is cached in SubRegs data-member.

134unsigned getSubReg(unsignedOffset,unsignedSize)const;

135

136 /// Cache for getSubReg method: {Offset, Size} -> SubReg index.

137mutableSmallDenseMap<std::pair<unsigned, unsigned>,unsigned> SubRegs;

138

139 /// Return bit mask that contains all register classes that are projected into

140 /// RC by SubRegIdx. The result is cached in SuperRegMasks data-member.

141constuint32_t *getSuperRegClassMask(constTargetRegisterClass *RC,

142unsigned SubRegIdx)const;

143

144 /// Cache for getSuperRegClassMask method: { RC, SubRegIdx } -> Class bitmask.

145mutableSmallDenseMap<std::pair<const TargetRegisterClass *, unsigned>,

146constuint32_t *>

147 SuperRegMasks;

148

149 /// Return bitmask containing all allocatable register classes with registers

150 /// aligned at AlignNumBits. The result is cached in

151 /// AllocatableAndAlignedRegClassMasks data-member.

152constBitVector &

153 getAllocatableAndAlignedRegClassMask(unsigned AlignNumBits)const;

154

155 /// Cache for getAllocatableAndAlignedRegClassMask method:

156 /// AlignNumBits -> Class bitmask.

157mutableSmallDenseMap<unsigned, BitVector> AllocatableAndAlignedRegClassMasks;

158};

159

160}// end anonymous namespace

161

162// TODO: move this to the tablegen and use binary search by Offset.

163unsigned GCNRewritePartialRegUses::getSubReg(unsignedOffset,

164unsignedSize) const{

165constauto [I,Inserted] = SubRegs.try_emplace({Offset,Size}, 0);

166if (Inserted) {

167for (unsignedIdx = 1, E =TRI->getNumSubRegIndices();Idx < E; ++Idx) {

168if (TRI->getSubRegIdxOffset(Idx) ==Offset &&

169TRI->getSubRegIdxSize(Idx) ==Size) {

170I->second =Idx;

171break;

172 }

173 }

174 }

175returnI->second;

176}

177

178unsigned GCNRewritePartialRegUses::shiftSubReg(unsignedSubReg,

179unsigned RShift) const{

180unsignedOffset =TRI->getSubRegIdxOffset(SubReg) - RShift;

181return getSubReg(Offset,TRI->getSubRegIdxSize(SubReg));

182}

183

184constuint32_t *

185GCNRewritePartialRegUses::getSuperRegClassMask(constTargetRegisterClass *RC,

186unsigned SubRegIdx) const{

187constauto [I,Inserted] =

188 SuperRegMasks.try_emplace({RC, SubRegIdx},nullptr);

189if (Inserted) {

190for (SuperRegClassIterator RCI(RC,TRI); RCI.isValid(); ++RCI) {

191if (RCI.getSubReg() == SubRegIdx) {

192I->second = RCI.getMask();

193break;

194 }

195 }

196 }

197returnI->second;

198}

199

200constBitVector &GCNRewritePartialRegUses::getAllocatableAndAlignedRegClassMask(

201unsigned AlignNumBits) const{

202constauto [I,Inserted] =

203 AllocatableAndAlignedRegClassMasks.try_emplace(AlignNumBits);

204if (Inserted) {

205BitVector &BV =I->second;

206 BV.resize(TRI->getNumRegClasses());

207for (unsigned ClassID = 0; ClassID <TRI->getNumRegClasses(); ++ClassID) {

208auto *RC =TRI->getRegClass(ClassID);

209if (RC->isAllocatable() &&TRI->isRegClassAligned(RC, AlignNumBits))

210 BV.set(ClassID);

211 }

212 }

213returnI->second;

214}

215

216constTargetRegisterClass *

217GCNRewritePartialRegUses::getRegClassWithShiftedSubregs(

218constTargetRegisterClass *RC,unsigned RShift,unsigned RegNumBits,

219unsigned CoverSubregIdx, SubRegMap &SubRegs) const{

220

221unsigned RCAlign =TRI->getRegClassAlignmentNumBits(RC);

222LLVM_DEBUG(dbgs() <<" Shift " << RShift <<", reg align " << RCAlign

223 <<'\n');

224

225BitVector ClassMask(getAllocatableAndAlignedRegClassMask(RCAlign));

226for (auto &[OldSubReg, SRI] : SubRegs) {

227auto &[SubRegRC, NewSubReg] = SRI;

228assert(SubRegRC);

229

230LLVM_DEBUG(dbgs() <<" " <<TRI->getSubRegIndexName(OldSubReg) <<':'

231 <<TRI->getRegClassName(SubRegRC)

232 << (SubRegRC->isAllocatable() ?"" :" not alloc")

233 <<" -> ");

234

235if (OldSubReg == CoverSubregIdx) {

236// Covering subreg will become a full register, RC should be allocatable.

237assert(SubRegRC->isAllocatable());

238 NewSubReg = AMDGPU::NoSubRegister;

239LLVM_DEBUG(dbgs() <<"whole reg");

240 }else {

241 NewSubReg = shiftSubReg(OldSubReg, RShift);

242if (!NewSubReg) {

243LLVM_DEBUG(dbgs() <<"none\n");

244returnnullptr;

245 }

246LLVM_DEBUG(dbgs() <<TRI->getSubRegIndexName(NewSubReg));

247 }

248

249constuint32_t *Mask = NewSubReg ? getSuperRegClassMask(SubRegRC, NewSubReg)

250 : SubRegRC->getSubClassMask();

251if (!Mask)

252llvm_unreachable("no register class mask?");

253

254 ClassMask.clearBitsNotInMask(Mask);

255// Don't try to early exit because checking if ClassMask has set bits isn't

256// that cheap and we expect it to pass in most cases.

257LLVM_DEBUG(dbgs() <<", num regclasses " << ClassMask.count() <<'\n');

258 }

259

260// ClassMask is the set of all register classes such that each class is

261// allocatable, aligned, has all shifted subregs and each subreg has required

262// register class (see SubRegRC above). Now select first (that is largest)

263// register class with registers of minimal but not less than RegNumBits size.

264// We have to check register size because we may encounter classes of smaller

265// registers like VReg_1 in some situations.

266constTargetRegisterClass *MinRC =nullptr;

267unsigned MinNumBits = std::numeric_limits<unsigned>::max();

268for (unsigned ClassID : ClassMask.set_bits()) {

269auto *RC =TRI->getRegClass(ClassID);

270unsigned NumBits =TRI->getRegSizeInBits(*RC);

271if (NumBits < MinNumBits && NumBits >= RegNumBits) {

272 MinNumBits = NumBits;

273 MinRC = RC;

274 }

275if (MinNumBits == RegNumBits)

276break;

277 }

278#ifndef NDEBUG

279if (MinRC) {

280assert(MinRC->isAllocatable() &&TRI->isRegClassAligned(MinRC, RCAlign));

281for (auto [SubReg, SRI] : SubRegs)

282// Check that all registers in MinRC support SRI.SubReg subregister.

283assert(MinRC ==TRI->getSubClassWithSubReg(MinRC, SRI.SubReg));

284 }

285#endif

286// There might be zero RShift - in this case we just trying to find smaller

287// register.

288return (MinRC != RC || RShift != 0) ? MinRC :nullptr;

289}

290

291constTargetRegisterClass *

292GCNRewritePartialRegUses::getMinSizeReg(constTargetRegisterClass *RC,

293 SubRegMap &SubRegs) const{

294unsigned CoverSubreg = AMDGPU::NoSubRegister;

295unsignedOffset = std::numeric_limits<unsigned>::max();

296unsignedEnd = 0;

297for (auto [SubReg, SRI] : SubRegs) {

298unsigned SubRegOffset =TRI->getSubRegIdxOffset(SubReg);

299unsigned SubRegEnd = SubRegOffset +TRI->getSubRegIdxSize(SubReg);

300if (SubRegOffset <Offset) {

301Offset = SubRegOffset;

302 CoverSubreg = AMDGPU::NoSubRegister;

303 }

304if (SubRegEnd >End) {

305End = SubRegEnd;

306 CoverSubreg = AMDGPU::NoSubRegister;

307 }

308if (SubRegOffset ==Offset && SubRegEnd ==End)

309 CoverSubreg =SubReg;

310 }

311// If covering subreg is found shift everything so the covering subreg would

312// be in the rightmost position.

313if (CoverSubreg != AMDGPU::NoSubRegister)

314return getRegClassWithShiftedSubregs(RC,Offset,End -Offset, CoverSubreg,

315 SubRegs);

316

317// Otherwise find subreg with maximum required alignment and shift it and all

318// other subregs to the rightmost possible position with respect to the

319// alignment.

320unsigned MaxAlign = 0;

321for (auto [SubReg, SRI] : SubRegs)

322 MaxAlign = std::max(MaxAlign,TRI->getSubRegAlignmentNumBits(RC,SubReg));

323

324unsigned FirstMaxAlignedSubRegOffset = std::numeric_limits<unsigned>::max();

325for (auto [SubReg, SRI] : SubRegs) {

326if (TRI->getSubRegAlignmentNumBits(RC,SubReg) != MaxAlign)

327continue;

328 FirstMaxAlignedSubRegOffset =

329 std::min(FirstMaxAlignedSubRegOffset,TRI->getSubRegIdxOffset(SubReg));

330if (FirstMaxAlignedSubRegOffset ==Offset)

331break;

332 }

333

334unsigned NewOffsetOfMaxAlignedSubReg =

335alignTo(FirstMaxAlignedSubRegOffset -Offset, MaxAlign);

336

337if (NewOffsetOfMaxAlignedSubReg > FirstMaxAlignedSubRegOffset)

338llvm_unreachable("misaligned subreg");

339

340unsigned RShift = FirstMaxAlignedSubRegOffset - NewOffsetOfMaxAlignedSubReg;

341return getRegClassWithShiftedSubregs(RC, RShift,End - RShift, 0, SubRegs);

342}

343

344// Only the subrange's lanemasks of the original interval need to be modified.

345// Subrange for a covering subreg becomes the main range.

346void GCNRewritePartialRegUses::updateLiveIntervals(Register OldReg,

347Register NewReg,

348 SubRegMap &SubRegs) const{

349if (!LIS->hasInterval(OldReg))

350return;

351

352auto &OldLI = LIS->getInterval(OldReg);

353auto &NewLI = LIS->createEmptyInterval(NewReg);

354

355auto &Allocator = LIS->getVNInfoAllocator();

356 NewLI.setWeight(OldLI.weight());

357

358for (auto &SR : OldLI.subranges()) {

359autoI =find_if(SubRegs, [&](auto &P) {

360return SR.LaneMask ==TRI->getSubRegIndexLaneMask(P.first);

361 });

362

363if (I == SubRegs.end()) {

364// There might be a situation when subranges don't exactly match used

365// subregs, for example:

366// %120 [160r,1392r:0) 0@160r

367// L000000000000C000 [160r,1392r:0) 0@160r

368// L0000000000003000 [160r,1392r:0) 0@160r

369// L0000000000000C00 [160r,1392r:0) 0@160r

370// L0000000000000300 [160r,1392r:0) 0@160r

371// L0000000000000003 [160r,1104r:0) 0@160r

372// L000000000000000C [160r,1104r:0) 0@160r

373// L0000000000000030 [160r,1104r:0) 0@160r

374// L00000000000000C0 [160r,1104r:0) 0@160r

375// but used subregs are:

376// sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, L000000000000FFFF

377// sub0_sub1_sub2_sub3, L00000000000000FF

378// sub4_sub5_sub6_sub7, L000000000000FF00

379// In this example subregs sub0_sub1_sub2_sub3 and sub4_sub5_sub6_sub7

380// have several subranges with the same lifetime. For such cases just

381// recreate the interval.

382 LIS->removeInterval(OldReg);

383 LIS->removeInterval(NewReg);

384 LIS->createAndComputeVirtRegInterval(NewReg);

385return;

386 }

387

388if (unsigned NewSubReg =I->second.SubReg)

389 NewLI.createSubRangeFrom(Allocator,

390TRI->getSubRegIndexLaneMask(NewSubReg), SR);

391else// This is the covering subreg (0 index) - set it as main range.

392 NewLI.assign(SR, Allocator);

393

394 SubRegs.erase(I);

395 }

396if (NewLI.empty())

397 NewLI.assign(OldLI, Allocator);

398assert(NewLI.verify(MRI));

399 LIS->removeInterval(OldReg);

400}

401

402constTargetRegisterClass *

403GCNRewritePartialRegUses::getOperandRegClass(MachineOperand &MO) const{

404MachineInstr *MI = MO.getParent();

405returnTII->getRegClass(TII->get(MI->getOpcode()),MI->getOperandNo(&MO),TRI,

406 *MI->getParent()->getParent());

407}

408

409bool GCNRewritePartialRegUses::rewriteReg(Register Reg) const{

410autoRange =MRI->reg_nodbg_operands(Reg);

411if (Range.empty() ||any_of(Range, [](MachineOperand &MO) {

412return MO.getSubReg() == AMDGPU::NoSubRegister;// Whole reg used. [1]

413 }))

414returnfalse;

415

416auto *RC =MRI->getRegClass(Reg);

417LLVM_DEBUG(dbgs() <<"Try to rewrite partial reg " <<printReg(Reg,TRI)

418 <<':' <<TRI->getRegClassName(RC) <<'\n');

419

420// Collect used subregs and their reg classes infered from instruction

421// operands.

422 SubRegMap SubRegs;

423for (MachineOperand &MO :Range) {

424constunsignedSubReg = MO.getSubReg();

425assert(SubReg != AMDGPU::NoSubRegister);// Due to [1].

426LLVM_DEBUG(dbgs() <<" " <<TRI->getSubRegIndexName(SubReg) <<':');

427

428constauto [I,Inserted] = SubRegs.try_emplace(SubReg);

429constTargetRegisterClass *&SubRegRC =I->second.RC;

430

431if (Inserted)

432 SubRegRC =TRI->getSubRegisterClass(RC,SubReg);

433

434if (SubRegRC) {

435if (constTargetRegisterClass *OpDescRC = getOperandRegClass(MO)) {

436LLVM_DEBUG(dbgs() <<TRI->getRegClassName(SubRegRC) <<" & "

437 <<TRI->getRegClassName(OpDescRC) <<" = ");

438 SubRegRC =TRI->getCommonSubClass(SubRegRC, OpDescRC);

439 }

440 }

441

442if (!SubRegRC) {

443LLVM_DEBUG(dbgs() <<"couldn't find target regclass\n");

444returnfalse;

445 }

446LLVM_DEBUG(dbgs() <<TRI->getRegClassName(SubRegRC) <<'\n');

447 }

448

449auto *NewRC = getMinSizeReg(RC, SubRegs);

450if (!NewRC) {

451LLVM_DEBUG(dbgs() <<" No improvement achieved\n");

452returnfalse;

453 }

454

455Register NewReg =MRI->createVirtualRegister(NewRC);

456LLVM_DEBUG(dbgs() <<" Success " <<printReg(Reg,TRI) <<':'

457 <<TRI->getRegClassName(RC) <<" -> "

458 <<printReg(NewReg,TRI) <<':'

459 <<TRI->getRegClassName(NewRC) <<'\n');

460

461for (auto &MO :make_early_inc_range(MRI->reg_operands(Reg))) {

462 MO.setReg(NewReg);

463// Debug info can refer to the whole reg, just leave it as it is for now.

464// TODO: create some DI shift expression?

465if (MO.isDebug() && MO.getSubReg() == 0)

466continue;

467unsignedSubReg = SubRegs[MO.getSubReg()].SubReg;

468 MO.setSubReg(SubReg);

469if (SubReg == AMDGPU::NoSubRegister && MO.isDef())

470 MO.setIsUndef(false);

471 }

472

473if (LIS)

474 updateLiveIntervals(Reg, NewReg, SubRegs);

475

476returntrue;

477}

478

479bool GCNRewritePartialRegUses::runOnMachineFunction(MachineFunction &MF) {

480MRI = &MF.getRegInfo();

481TRI =static_cast<constSIRegisterInfo *>(MRI->getTargetRegisterInfo());

482TII = MF.getSubtarget().getInstrInfo();

483auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>();

484 LIS = LISWrapper ? &LISWrapper->getLIS() :nullptr;

485bool Changed =false;

486for (size_tI = 0, E =MRI->getNumVirtRegs();I < E; ++I) {

487 Changed |= rewriteReg(Register::index2VirtReg(I));

488 }

489return Changed;

490}

491

492char GCNRewritePartialRegUses::ID;

493

494char &llvm::GCNRewritePartialRegUsesID = GCNRewritePartialRegUses::ID;

495

496INITIALIZE_PASS_BEGIN(GCNRewritePartialRegUses,DEBUG_TYPE,

497"Rewrite Partial Register Uses",false,false)

498INITIALIZE_PASS_END(GCNRewritePartialRegUses,DEBUG_TYPE,

499 "Rewrite PartialRegister Uses",false,false)

SubReg

unsigned SubReg

Definition:AArch64AdvSIMDScalarPass.cpp:104

MRI

unsigned const MachineRegisterInfo * MRI

Definition:AArch64AdvSIMDScalarPass.cpp:105

AMDGPUMCTargetDesc.h

Provides AMDGPU specific target descriptions.

AMDGPU.h

Idx

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

Definition:DeadArgumentElimination.cpp:353

LLVM_DEBUG

#define LLVM_DEBUG(...)

Definition:Debug.h:106

Size

uint64_t Size

Definition:ELFObjHandler.cpp:81

End

bool End

Definition:ELF_riscv.cpp:480

Uses

Rewrite Partial Register Uses

Definition:GCNRewritePartialRegUses.cpp:499

DEBUG_TYPE

#define DEBUG_TYPE

Definition:GCNRewritePartialRegUses.cpp:43

TII

const HexagonInstrInfo * TII

Definition:HexagonCopyToCombine.cpp:125

IRTranslator LLVM IR MI

Definition:IRTranslator.cpp:112

LiveInterval.h

LiveIntervals.h

#define I(x, y, z)

Definition:MD5.cpp:58

MachineFunctionPass.h

MachineRegisterInfo.h

TRI

unsigned const TargetRegisterInfo * TRI

Definition:MachineSink.cpp:2029

Range

ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))

#define P(N)

INITIALIZE_PASS_END

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

Definition:PassSupport.h:57

INITIALIZE_PASS_BEGIN

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

Definition:PassSupport.h:52

Pass.h

Allocator

Basic Register Allocator

Definition:RegAllocBasic.cpp:146

assert

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

SIRegisterInfo.h

Interface definition for SIRegisterInfo.

TargetInstrInfo.h

llvm::AnalysisUsage

Represent the analysis usage information of a pass.

Definition:PassAnalysisSupport.h:47

llvm::AnalysisUsage::addPreserved

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

Definition:PassAnalysisSupport.h:98

llvm::AnalysisUsage::setPreservesCFG

void setPreservesCFG()

This function should be called by the pass, iff they do not:

Definition:Pass.cpp:256

llvm::BitVector

Definition:BitVector.h:82

llvm::BitVector::resize

void resize(unsigned N, bool t=false)

resize - Grow or shrink the bitvector.

Definition:BitVector.h:341

llvm::BitVector::set

BitVector & set()

Definition:BitVector.h:351

llvm::DenseMapBase::try_emplace

std::pair< iterator, bool > try_emplace(KeyT &&Key, Ts &&...Args)

Definition:DenseMap.h:226

llvm::LiveIntervalsWrapperPass

Definition:LiveIntervals.h:527

llvm::LiveIntervals

Definition:LiveIntervals.h:55

llvm::MachineFunctionPass

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

Definition:MachineFunctionPass.h:30

llvm::MachineFunctionPass::getAnalysisUsage

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Definition:MachineFunctionPass.cpp:169

llvm::MachineFunctionPass::runOnMachineFunction

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

llvm::MachineFunction

Definition:MachineFunction.h:267

llvm::MachineFunction::getSubtarget

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Definition:MachineFunction.h:733

llvm::MachineFunction::getRegInfo

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Definition:MachineFunction.h:743

llvm::MachineInstr

Representation of each machine instruction.

Definition:MachineInstr.h:71

llvm::MachineOperand

MachineOperand class - Representation of each machine instruction operand.

Definition:MachineOperand.h:48

llvm::MachineOperand::setSubReg

void setSubReg(unsigned subReg)

Definition:MachineOperand.h:490

llvm::MachineOperand::getSubReg

unsigned getSubReg() const

Definition:MachineOperand.h:374

llvm::MachineOperand::setReg

void setReg(Register Reg)

Change the register this operand corresponds to.

Definition:MachineOperand.cpp:61

llvm::MachineOperand::isDef

bool isDef() const

Definition:MachineOperand.h:384

llvm::MachineOperand::getParent

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

Definition:MachineOperand.h:243

llvm::MachineOperand::isDebug

bool isDebug() const

Definition:MachineOperand.h:455

llvm::MachineOperand::setIsUndef

void setIsUndef(bool Val=true)

Definition:MachineOperand.h:530

llvm::MachineRegisterInfo

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Definition:MachineRegisterInfo.h:51

llvm::Pass::getPassName

virtual StringRef getPassName() const

getPassName - Return a nice clean name for a pass.

Definition:Pass.cpp:81

llvm::Register

Wrapper class representing virtual and physical registers.

Definition:Register.h:19

llvm::Register::index2VirtReg

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

Definition:Register.h:84

llvm::SIRegisterInfo

Definition:SIRegisterInfo.h:32

llvm::SlotIndexesWrapperPass

Definition:SlotIndexes.h:663

llvm::SmallDenseMap

Definition:DenseMap.h:883

llvm::StringRef

StringRef - Represent a constant reference to a string, i.e.

Definition:StringRef.h:51

llvm::SuperRegClassIterator

Definition:TargetRegisterInfo.h:1254

llvm::SuperRegClassIterator::isValid

bool isValid() const

Returns true if this iterator is still pointing at a valid entry.

Definition:TargetRegisterInfo.h:1273

llvm::TargetInstrInfo

TargetInstrInfo - Interface to description of machine instruction set.

Definition:TargetInstrInfo.h:112

llvm::TargetRegisterClass

Definition:TargetRegisterInfo.h:44

llvm::TargetRegisterClass::isAllocatable

bool isAllocatable() const

Return true if this register class may be used to create virtual registers.

Definition:TargetRegisterInfo.h:118

llvm::TargetSubtargetInfo::getInstrInfo

virtual const TargetInstrInfo * getInstrInfo() const

Definition:TargetSubtargetInfo.h:97

uint32_t

unsigned

llvm_unreachable

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

Definition:ErrorHandling.h:143

false

Definition:StackSlotColoring.cpp:193

llvm::BitmaskEnumDetail::Mask

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

Definition:BitmaskEnum.h:125

llvm::CallingConv::ID

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

Definition:CallingConv.h:24

llvm::logicalview::LVAttributeKind::Inserted

@ Inserted

llvm

This is an optimization pass for GlobalISel generic memory operations.

Definition:AddressRanges.h:18

llvm::Offset

@ Offset

Definition:DWP.cpp:480

llvm::GCNRewritePartialRegUsesID

char & GCNRewritePartialRegUsesID

Definition:GCNRewritePartialRegUses.cpp:494

llvm::make_early_inc_range

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

Definition:STLExtras.h:657

llvm::any_of

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

Definition:STLExtras.h:1746

llvm::dbgs

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Definition:Debug.cpp:163

llvm::alignTo

uint64_t alignTo(uint64_t Size, Align A)

Returns a multiple of A needed to store Size bytes.

Definition:Alignment.h:155

llvm::find_if

auto find_if(R &&Range, UnaryPredicate P)

Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.

Definition:STLExtras.h:1766

llvm::printReg

Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

Definition:TargetRegisterInfo.cpp:107