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1//===- CombinerHelperVectorOps.cpp-----------------------------------------===//

2//

3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

4// See https://llvm.org/LICENSE.txt for license information.

5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

6//

7//===----------------------------------------------------------------------===//

8//

9// This file implements CombinerHelper for G_EXTRACT_VECTOR_ELT,

10// G_INSERT_VECTOR_ELT, and G_VSCALE

11//

12//===----------------------------------------------------------------------===//

13#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"

14#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"

15#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"

16#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"

17#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"

18#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"

19#include "llvm/CodeGen/GlobalISel/Utils.h"

20#include "llvm/CodeGen/LowLevelTypeUtils.h"

21#include "llvm/CodeGen/MachineOperand.h"

22#include "llvm/CodeGen/MachineRegisterInfo.h"

23#include "llvm/CodeGen/TargetLowering.h"

24#include "llvm/CodeGen/TargetOpcodes.h"

25#include "llvm/Support/Casting.h"

26#include <optional>

28#define DEBUG_TYPE "gi-combiner"

30using namespacellvm;

31using namespaceMIPatternMatch;

33boolCombinerHelper::matchExtractVectorElement(MachineInstr &MI,

34BuildFnTy &MatchInfo) const{

35GExtractVectorElement *Extract = cast<GExtractVectorElement>(&MI);

37Register Dst = Extract->getReg(0);

38Register Vector = Extract->getVectorReg();

39Register Index = Extract->getIndexReg();

40LLT DstTy =MRI.getType(Dst);

41LLT VectorTy =MRI.getType(Vector);

43// The vector register can be def'd by various ops that have vector as its

44// type. They can all be used for constant folding, scalarizing,

45// canonicalization, or combining based on symmetry.

46//

47// vector like ops

48// * build vector

49// * build vector trunc

50// * shuffle vector

51// * splat vector

52// * concat vectors

53// * insert/extract vector element

54// * insert/extract subvector

55// * vector loads

56// * scalable vector loads

57//

58// compute like ops

59// * binary ops

60// * unary ops

61// * exts and truncs

62// * casts

63// * fneg

64// * select

65// * phis

66// * cmps

67// * freeze

68// * bitcast

69// * undef

71// We try to get the value of the Index register.

72 std::optional<ValueAndVReg> MaybeIndex =

73getIConstantVRegValWithLookThrough(Index,MRI);

74 std::optional<APInt> IndexC = std::nullopt;

76if (MaybeIndex)

77 IndexC = MaybeIndex->Value;

79// Fold extractVectorElement(Vector, TOOLARGE) -> undef

80if (IndexC && VectorTy.isFixedVector() &&

81 IndexC->uge(VectorTy.getNumElements()) &&

82isLegalOrBeforeLegalizer({TargetOpcode::G_IMPLICIT_DEF, {DstTy}})) {

83// For fixed-length vectors, it's invalid to extract out-of-range elements.

84 MatchInfo = [=](MachineIRBuilder &B) {B.buildUndef(Dst); };

85returntrue;

86 }

88returnfalse;

89}

91boolCombinerHelper::matchExtractVectorElementWithDifferentIndices(

92constMachineOperand &MO,BuildFnTy &MatchInfo) const{

93MachineInstr *Root =getDefIgnoringCopies(MO.getReg(),MRI);

94GExtractVectorElement *Extract = cast<GExtractVectorElement>(Root);

96//

97// %idx1:_(s64) = G_CONSTANT i64 1

98// %idx2:_(s64) = G_CONSTANT i64 2

99// %insert:_(<2 x s32>) = G_INSERT_VECTOR_ELT_ELT %bv(<2 x s32>),

100// %value(s32), %idx2(s64) %extract:_(s32) = G_EXTRACT_VECTOR_ELT %insert(<2

101// x s32>), %idx1(s64)

102//

103// -->

104//

105// %insert:_(<2 x s32>) = G_INSERT_VECTOR_ELT_ELT %bv(<2 x s32>),

106// %value(s32), %idx2(s64) %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x

107// s32>), %idx1(s64)

108//

109//

110

111Register Index = Extract->getIndexReg();

112

113// We try to get the value of the Index register.

114 std::optional<ValueAndVReg> MaybeIndex =

115getIConstantVRegValWithLookThrough(Index,MRI);

116 std::optional<APInt> IndexC = std::nullopt;

117

118if (!MaybeIndex)

119returnfalse;

120else

121 IndexC = MaybeIndex->Value;

122

123Register Vector = Extract->getVectorReg();

124

125GInsertVectorElement *Insert =

126 getOpcodeDef<GInsertVectorElement>(Vector,MRI);

127if (!Insert)

128returnfalse;

129

130Register Dst = Extract->getReg(0);

131

132 std::optional<ValueAndVReg> MaybeInsertIndex =

133getIConstantVRegValWithLookThrough(Insert->getIndexReg(),MRI);

134

135if (MaybeInsertIndex && MaybeInsertIndex->Value != *IndexC) {

136// There is no one-use check. We have to keep the insert. When both Index

137// registers are constants and not equal, we can look into the Vector

138// register of the insert.

139 MatchInfo = [=](MachineIRBuilder &B) {

140B.buildExtractVectorElement(Dst, Insert->getVectorReg(), Index);

141 };

142returntrue;

143 }

144

145returnfalse;

146}

147

148boolCombinerHelper::matchExtractVectorElementWithBuildVector(

149constMachineInstr &MI,constMachineInstr &MI2,

150BuildFnTy &MatchInfo) const{

151constGExtractVectorElement *Extract = cast<GExtractVectorElement>(&MI);

152constGBuildVector *Build = cast<GBuildVector>(&MI2);

153

154//

155// %zero:_(s64) = G_CONSTANT i64 0

156// %bv:_(<2 x s32>) = G_BUILD_VECTOR %arg1(s32), %arg2(s32)

157// %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %zero(s64)

158//

159// -->

160//

161// %extract:_(32) = COPY %arg1(s32)

162//

163//

164

165Register Vector = Extract->getVectorReg();

166LLT VectorTy =MRI.getType(Vector);

167

168// There is a one-use check. There are more combines on build vectors.

169EVT Ty(getMVTForLLT(VectorTy));

170if (!MRI.hasOneNonDBGUse(Build->getReg(0)) ||

171 !getTargetLowering().aggressivelyPreferBuildVectorSources(Ty))

172returnfalse;

173

174APInt Index =getIConstantFromReg(Extract->getIndexReg(),MRI);

175

176// We now know that there is a buildVector def'd on the Vector register and

177// the index is const. The combine will succeed.

178

179Register Dst = Extract->getReg(0);

180

181 MatchInfo = [=](MachineIRBuilder &B) {

182B.buildCopy(Dst, Build->getSourceReg(Index.getZExtValue()));

183 };

184

185returntrue;

186}

187

188boolCombinerHelper::matchExtractVectorElementWithBuildVectorTrunc(

189constMachineOperand &MO,BuildFnTy &MatchInfo) const{

190MachineInstr *Root =getDefIgnoringCopies(MO.getReg(),MRI);

191GExtractVectorElement *Extract = cast<GExtractVectorElement>(Root);

192

193//

194// %zero:_(s64) = G_CONSTANT i64 0

195// %bv:_(<2 x s32>) = G_BUILD_VECTOR_TRUNC %arg1(s64), %arg2(s64)

196// %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %zero(s64)

197//

198// -->

199//

200// %extract:_(32) = G_TRUNC %arg1(s64)

201//

202//

203//

204// %bv:_(<2 x s32>) = G_BUILD_VECTOR_TRUNC %arg1(s64), %arg2(s64)

205// %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %opaque(s64)

206//

207// -->

208//

209// %bv:_(<2 x s32>) = G_BUILD_VECTOR_TRUNC %arg1(s64), %arg2(s64)

210// %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %opaque(s64)

211//

212

213Register Vector = Extract->getVectorReg();

214

215// We expect a buildVectorTrunc on the Vector register.

216GBuildVectorTrunc *Build = getOpcodeDef<GBuildVectorTrunc>(Vector,MRI);

217if (!Build)

218returnfalse;

219

220LLT VectorTy =MRI.getType(Vector);

221

222// There is a one-use check. There are more combines on build vectors.

223EVT Ty(getMVTForLLT(VectorTy));

224if (!MRI.hasOneNonDBGUse(Build->getReg(0)) ||

225 !getTargetLowering().aggressivelyPreferBuildVectorSources(Ty))

226returnfalse;

227

228Register Index = Extract->getIndexReg();

229

230// If the Index is constant, then we can extract the element from the given

231// offset.

232 std::optional<ValueAndVReg> MaybeIndex =

233getIConstantVRegValWithLookThrough(Index,MRI);

234if (!MaybeIndex)

235returnfalse;

236

237// We now know that there is a buildVectorTrunc def'd on the Vector register

238// and the index is const. The combine will succeed.

239

240Register Dst = Extract->getReg(0);

241LLT DstTy =MRI.getType(Dst);

242LLT SrcTy =MRI.getType(Build->getSourceReg(0));

243

244// For buildVectorTrunc, the inputs are truncated.

245if (!isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}}))

246returnfalse;

247

248 MatchInfo = [=](MachineIRBuilder &B) {

249B.buildTrunc(Dst, Build->getSourceReg(MaybeIndex->Value.getZExtValue()));

250 };

251

252returntrue;

253}

254

255boolCombinerHelper::matchExtractVectorElementWithShuffleVector(

256constMachineInstr &MI,constMachineInstr &MI2,

257BuildFnTy &MatchInfo) const{

258constGExtractVectorElement *Extract = cast<GExtractVectorElement>(&MI);

259constGShuffleVector *Shuffle = cast<GShuffleVector>(&MI2);

260

261//

262// %zero:_(s64) = G_CONSTANT i64 0

263// %sv:_(<4 x s32>) = G_SHUFFLE_SHUFFLE %arg1(<4 x s32>), %arg2(<4 x s32>),

264// shufflemask(0, 0, 0, 0)

265// %extract:_(s32) = G_EXTRACT_VECTOR_ELT %sv(<4 x s32>), %zero(s64)

266//

267// -->

268//

269// %zero1:_(s64) = G_CONSTANT i64 0

270// %extract:_(s32) = G_EXTRACT_VECTOR_ELT %arg1(<4 x s32>), %zero1(s64)

271//

272//

273//

274//

275// %three:_(s64) = G_CONSTANT i64 3

276// %sv:_(<4 x s32>) = G_SHUFFLE_SHUFFLE %arg1(<4 x s32>), %arg2(<4 x s32>),

277// shufflemask(0, 0, 0, -1)

278// %extract:_(s32) = G_EXTRACT_VECTOR_ELT %sv(<4 x s32>), %three(s64)

279//

280// -->

281//

282// %extract:_(s32) = G_IMPLICIT_DEF

283//

284//

285

286APInt Index =getIConstantFromReg(Extract->getIndexReg(),MRI);

287

288ArrayRef<int> Mask = Shuffle->getMask();

289

290unsignedOffset = Index.getZExtValue();

291int SrcIdx = Mask[Offset];

292

293LLT Src1Type =MRI.getType(Shuffle->getSrc1Reg());

294// At the IR level a <1 x ty> shuffle vector is valid, but we want to extract

295// from a vector.

296assert(Src1Type.isVector() &&"expected to extract from a vector");

297unsigned LHSWidth = Src1Type.isVector() ? Src1Type.getNumElements() : 1;

298

299// Note that there is no one use check.

300Register Dst = Extract->getReg(0);

301LLT DstTy =MRI.getType(Dst);

302

303if (SrcIdx < 0 &&

304isLegalOrBeforeLegalizer({TargetOpcode::G_IMPLICIT_DEF, {DstTy}})) {

305 MatchInfo = [=](MachineIRBuilder &B) {B.buildUndef(Dst); };

306returntrue;

307 }

308

309// If the legality check failed, then we still have to abort.

310if (SrcIdx < 0)

311returnfalse;

312

313Register NewVector;

314

315// We check in which vector and at what offset to look through.

316if (SrcIdx < (int)LHSWidth) {

317 NewVector = Shuffle->getSrc1Reg();

318// SrcIdx unchanged

319 }else {// SrcIdx >= LHSWidth

320 NewVector = Shuffle->getSrc2Reg();

321 SrcIdx -= LHSWidth;

322 }

323

324LLT IdxTy =MRI.getType(Extract->getIndexReg());

325LLT NewVectorTy =MRI.getType(NewVector);

326

327// We check the legality of the look through.

328if (!isLegalOrBeforeLegalizer(

329 {TargetOpcode::G_EXTRACT_VECTOR_ELT, {DstTy, NewVectorTy, IdxTy}}) ||

330 !isConstantLegalOrBeforeLegalizer({IdxTy}))

331returnfalse;

332

333// We look through the shuffle vector.

334 MatchInfo = [=](MachineIRBuilder &B) {

335autoIdx =B.buildConstant(IdxTy, SrcIdx);

336B.buildExtractVectorElement(Dst, NewVector,Idx);

337 };

338

339returntrue;

340}

341

342boolCombinerHelper::matchInsertVectorElementOOB(MachineInstr &MI,

343BuildFnTy &MatchInfo) const{

344GInsertVectorElement *Insert = cast<GInsertVectorElement>(&MI);

345

346Register Dst = Insert->getReg(0);

347LLT DstTy =MRI.getType(Dst);

348Register Index = Insert->getIndexReg();

349

350if (!DstTy.isFixedVector())

351returnfalse;

352

353 std::optional<ValueAndVReg> MaybeIndex =

354getIConstantVRegValWithLookThrough(Index,MRI);

355

356if (MaybeIndex && MaybeIndex->Value.uge(DstTy.getNumElements()) &&

357isLegalOrBeforeLegalizer({TargetOpcode::G_IMPLICIT_DEF, {DstTy}})) {

358 MatchInfo = [=](MachineIRBuilder &B) {B.buildUndef(Dst); };

359returntrue;

360 }

361

362returnfalse;

363}

364

365boolCombinerHelper::matchAddOfVScale(constMachineOperand &MO,

366BuildFnTy &MatchInfo) const{

367GAdd *Add = cast<GAdd>(MRI.getVRegDef(MO.getReg()));

368GVScale *LHSVScale = cast<GVScale>(MRI.getVRegDef(Add->getLHSReg()));

369GVScale *RHSVScale = cast<GVScale>(MRI.getVRegDef(Add->getRHSReg()));

370

371Register Dst =Add->getReg(0);

372

373if (!MRI.hasOneNonDBGUse(LHSVScale->getReg(0)) ||

374 !MRI.hasOneNonDBGUse(RHSVScale->getReg(0)))

375returnfalse;

376

377 MatchInfo = [=](MachineIRBuilder &B) {

378B.buildVScale(Dst, LHSVScale->getSrc() + RHSVScale->getSrc());

379 };

380

381returntrue;

382}

383

384boolCombinerHelper::matchMulOfVScale(constMachineOperand &MO,

385BuildFnTy &MatchInfo) const{

386GMul *Mul = cast<GMul>(MRI.getVRegDef(MO.getReg()));

387GVScale *LHSVScale = cast<GVScale>(MRI.getVRegDef(Mul->getLHSReg()));

388

389 std::optional<APInt> MaybeRHS =getIConstantVRegVal(Mul->getRHSReg(),MRI);

390if (!MaybeRHS)

391returnfalse;

392

393Register Dst = MO.getReg();

394

395if (!MRI.hasOneNonDBGUse(LHSVScale->getReg(0)))

396returnfalse;

397

398 MatchInfo = [=](MachineIRBuilder &B) {

399B.buildVScale(Dst, LHSVScale->getSrc() * *MaybeRHS);

400 };

401

402returntrue;

403}

404

405boolCombinerHelper::matchSubOfVScale(constMachineOperand &MO,

406BuildFnTy &MatchInfo) const{

407GSub *Sub = cast<GSub>(MRI.getVRegDef(MO.getReg()));

408GVScale *RHSVScale = cast<GVScale>(MRI.getVRegDef(Sub->getRHSReg()));

409

410Register Dst = MO.getReg();

411LLT DstTy =MRI.getType(Dst);

412

413if (!MRI.hasOneNonDBGUse(RHSVScale->getReg(0)) ||

414 !isLegalOrBeforeLegalizer({TargetOpcode::G_ADD, DstTy}))

415returnfalse;

416

417 MatchInfo = [=](MachineIRBuilder &B) {

418auto VScale =B.buildVScale(DstTy, -RHSVScale->getSrc());

419B.buildAdd(Dst, Sub->getLHSReg(), VScale, Sub->getFlags());

420 };

421

422returntrue;

423}

424

425boolCombinerHelper::matchShlOfVScale(constMachineOperand &MO,

426BuildFnTy &MatchInfo) const{

427GShl *Shl = cast<GShl>(MRI.getVRegDef(MO.getReg()));

428GVScale *LHSVScale = cast<GVScale>(MRI.getVRegDef(Shl->getSrcReg()));

429

430 std::optional<APInt> MaybeRHS =getIConstantVRegVal(Shl->getShiftReg(),MRI);

431if (!MaybeRHS)

432returnfalse;

433

434Register Dst = MO.getReg();

435LLT DstTy =MRI.getType(Dst);

436

437if (!MRI.hasOneNonDBGUse(LHSVScale->getReg(0)) ||

438 !isLegalOrBeforeLegalizer({TargetOpcode::G_VSCALE, DstTy}))

439returnfalse;

440

441 MatchInfo = [=](MachineIRBuilder &B) {

442B.buildVScale(Dst, LHSVScale->getSrc().shl(*MaybeRHS));

443 };

444

445returntrue;

446}

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Casting.h

Utils.h

CombinerHelper.h

This contains common combine transformations that may be used in a combine pass,or by the target else...

Idx

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

Definition:DeadArgumentElimination.cpp:353

GenericMachineInstrs.h

Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...

IRTranslator LLVM IR MI

Definition:IRTranslator.cpp:112

LegalizerHelper.h

LegalizerInfo.h

Interface for Targets to specify which operations they can successfully select and how the others sho...

LowLevelTypeUtils.h

Implement a low-level type suitable for MachineInstr level instruction selection.

MIPatternMatch.h

Contains matchers for matching SSA Machine Instructions.

MachineIRBuilder.h

This file declares the MachineIRBuilder class.

MachineOperand.h

MachineRegisterInfo.h

assert

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

TargetLowering.h

This file describes how to lower LLVM code to machine code.

TargetOpcodes.h

llvm::APInt

Class for arbitrary precision integers.

Definition:APInt.h:78

llvm::APInt::shl

APInt shl(unsigned shiftAmt) const

Left-shift function.

Definition:APInt.h:873

llvm::ArrayRef

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Definition:ArrayRef.h:41

llvm::CombinerHelper::matchExtractVectorElementWithBuildVectorTrunc

bool matchExtractVectorElementWithBuildVectorTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Combine extract vector element with a build vector trunc on the vector register.

Definition:CombinerHelperVectorOps.cpp:188

llvm::CombinerHelper::getTargetLowering

const TargetLowering & getTargetLowering() const

Definition:CombinerHelper.cpp:67

llvm::CombinerHelper::matchExtractVectorElementWithDifferentIndices

bool matchExtractVectorElementWithDifferentIndices(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Combine extract vector element with a insert vector element on the vector register and different indi...

Definition:CombinerHelperVectorOps.cpp:91

llvm::CombinerHelper::matchInsertVectorElementOOB

bool matchInsertVectorElementOOB(MachineInstr &MI, BuildFnTy &MatchInfo) const

Combine insert vector element OOB.

Definition:CombinerHelperVectorOps.cpp:342

llvm::CombinerHelper::matchExtractVectorElement

bool matchExtractVectorElement(MachineInstr &MI, BuildFnTy &MatchInfo) const

Combine extract vector element.

Definition:CombinerHelperVectorOps.cpp:33

llvm::CombinerHelper::matchMulOfVScale

bool matchMulOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Definition:CombinerHelperVectorOps.cpp:384

llvm::CombinerHelper::matchAddOfVScale

bool matchAddOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Definition:CombinerHelperVectorOps.cpp:365

llvm::CombinerHelper::matchShlOfVScale

bool matchShlOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Definition:CombinerHelperVectorOps.cpp:425

llvm::CombinerHelper::matchExtractVectorElementWithShuffleVector

bool matchExtractVectorElementWithShuffleVector(const MachineInstr &MI, const MachineInstr &MI2, BuildFnTy &MatchInfo) const

Combine extract vector element with a shuffle vector on the vector register.

Definition:CombinerHelperVectorOps.cpp:255

llvm::CombinerHelper::isConstantLegalOrBeforeLegalizer

bool isConstantLegalOrBeforeLegalizer(const LLT Ty) const

Definition:CombinerHelper.cpp:163

llvm::CombinerHelper::MRI

MachineRegisterInfo & MRI

Definition:CombinerHelper.h:107

llvm::CombinerHelper::isLegalOrBeforeLegalizer

bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const

Definition:CombinerHelper.cpp:158

llvm::CombinerHelper::matchSubOfVScale

bool matchSubOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Definition:CombinerHelperVectorOps.cpp:405

llvm::CombinerHelper::matchExtractVectorElementWithBuildVector

bool matchExtractVectorElementWithBuildVector(const MachineInstr &MI, const MachineInstr &MI2, BuildFnTy &MatchInfo) const

Combine extract vector element with a build vector on the vector register.

Definition:CombinerHelperVectorOps.cpp:148

llvm::GAdd

Represents an integer addition.

Definition:GenericMachineInstrs.h:774

llvm::GBinOp::getLHSReg

Definition:GenericMachineInstrs.h:672

llvm::GBinOp::getRHSReg

Definition:GenericMachineInstrs.h:673

llvm::GBuildVectorTrunc

Represents a G_BUILD_VECTOR_TRUNC.

Definition:GenericMachineInstrs.h:308

llvm::GBuildVector

Represents a G_BUILD_VECTOR.

Definition:GenericMachineInstrs.h:300

llvm::GExtractVectorElement

Represents an extract vector element.

Definition:GenericMachineInstrs.h:798

llvm::GExtractVectorElement::getVectorReg

Definition:GenericMachineInstrs.h:800

llvm::GExtractVectorElement::getIndexReg

Definition:GenericMachineInstrs.h:801

llvm::GInsertVectorElement

Represents an insert vector element.

Definition:GenericMachineInstrs.h:809

llvm::GMergeLikeInstr::getSourceReg

Returns the I'th source register.

Definition:GenericMachineInstrs.h:269

llvm::GMul

Represents an integer multiplication.

Definition:GenericMachineInstrs.h:947

llvm::GShl

Represents a shift left.

Definition:GenericMachineInstrs.h:955

llvm::GShl::getShiftReg

Definition:GenericMachineInstrs.h:958

llvm::GShl::getSrcReg

Definition:GenericMachineInstrs.h:957

llvm::GShuffleVector

Represents a G_SHUFFLE_VECTOR.

Definition:GenericMachineInstrs.h:316

llvm::GShuffleVector::getSrc2Reg

Definition:GenericMachineInstrs.h:319

llvm::GShuffleVector::getSrc1Reg

Definition:GenericMachineInstrs.h:318

llvm::GShuffleVector::getMask

ArrayRef< int > getMask() const

Definition:GenericMachineInstrs.h:320

llvm::GSub

Represents an integer subtraction.

Definition:GenericMachineInstrs.h:939

llvm::GVScale

Represents a vscale.

Definition:GenericMachineInstrs.h:917

llvm::GVScale::getSrc

APInt getSrc() const

Definition:GenericMachineInstrs.h:919

llvm::GenericMachineInstr::getReg

Access the Idx'th operand as a register and return it.

Definition:GenericMachineInstrs.h:38

llvm::LLT

Definition:LowLevelType.h:39

llvm::LLT::getNumElements

constexpr uint16_t getNumElements() const

Returns the number of elements in a vector LLT.

Definition:LowLevelType.h:159

llvm::LLT::isVector

constexpr bool isVector() const

Definition:LowLevelType.h:148

llvm::LLT::isFixedVector

constexpr bool isFixedVector() const

Returns true if the LLT is a fixed vector.

Definition:LowLevelType.h:177

llvm::MachineIRBuilder

Helper class to build MachineInstr.

Definition:MachineIRBuilder.h:235

llvm::MachineInstr

Representation of each machine instruction.

Definition:MachineInstr.h:71

llvm::MachineInstr::getFlags

uint32_t getFlags() const

Return the MI flags bitvector.

Definition:MachineInstr.h:394

llvm::MachineOperand

MachineOperand class - Representation of each machine instruction operand.

Definition:MachineOperand.h:48

llvm::MachineOperand::getReg

getReg - Returns the register number.

Definition:MachineOperand.h:369

llvm::MachineRegisterInfo::hasOneNonDBGUse

bool hasOneNonDBGUse(Register RegNo) const

hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.

Definition:MachineRegisterInfo.cpp:427

llvm::MachineRegisterInfo::getVRegDef

MachineInstr * getVRegDef(Register Reg) const

getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...

Definition:MachineRegisterInfo.cpp:406

llvm::MachineRegisterInfo::getType

LLT getType(Register Reg) const

Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.

Definition:MachineRegisterInfo.h:777

llvm::Register

Wrapper class representing virtual and physical registers.

Definition:Register.h:19

llvm

This is an optimization pass for GlobalISel generic memory operations.

Definition:AddressRanges.h:18

llvm::Offset

@ Offset

Definition:DWP.cpp:480

llvm::getIConstantVRegVal

std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)

If VReg is defined by a G_CONSTANT, return the corresponding value.

Definition:Utils.cpp:294

llvm::getMVTForLLT

MVT getMVTForLLT(LLT Ty)

Get a rough equivalent of an MVT for a given LLT.

Definition:LowLevelTypeUtils.cpp:48

llvm::getDefIgnoringCopies

MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)

Find the def instruction for Reg, folding away any trivial copies.

Definition:Utils.cpp:486

llvm::BuildFnTy

std::function< void(MachineIRBuilder &)> BuildFnTy

Definition:CombinerHelper.h:83

llvm::getIConstantFromReg

const APInt & getIConstantFromReg(Register VReg, const MachineRegisterInfo &MRI)

VReg is defined by a G_CONSTANT, return the corresponding value.

Definition:Utils.cpp:305

llvm::RecurKind::Mul

@ Mul

Product of integers.

llvm::RecurKind::Add

@ Add

Sum of integers.

llvm::getIConstantVRegValWithLookThrough

std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)

If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...

Definition:Utils.cpp:433

llvm::VFParamKind::Vector

@ Vector

llvm::EVT

Extended Value Type.

Definition:ValueTypes.h:35