1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7//===----------------------------------------------------------------------===// 35#define DEBUG_TYPE "arm-disassembler" 41// Handles the condition code status of instructions in IT blocks 45// Returns the condition code for instruction in IT block 53// Advances the IT block state to the next T or E 54void advanceITState() {
58// Returns true if the current instruction is in an IT block 59bool instrInITBlock() {
60return !ITStates.empty();
63// Returns true if current instruction is the last instruction in an IT block 64bool instrLastInITBlock() {
65return ITStates.size() == 1;
68// Called when decoding an IT instruction. Sets the IT state for 69// the following instructions that for the IT block. Firstcond 70// corresponds to the field in the IT instruction encoding; Mask 71// is in the MCOperand format in which 1 means 'else' and 0 'then'. 72void setITState(
char Firstcond,
char Mask) {
73// (3 - the number of trailing zeros) is the number of then / else. 74unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask);
75unsignedchar CCBits =
static_cast<unsignedchar>(Firstcond & 0xf);
76assert(NumTZ <= 3 &&
"Invalid IT mask!");
77// push condition codes onto the stack the correct order for the pops 78for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
79unsigned Else = (Mask >> Pos) & 1;
80 ITStates.push_back(CCBits ^ Else);
82 ITStates.push_back(CCBits);
86 std::vector<unsigned char> ITStates;
92unsigned getVPTPred() {
95 Pred = VPTStates.back();
99void advanceVPTState() {
100 VPTStates.pop_back();
103bool instrInVPTBlock() {
104return !VPTStates.empty();
107bool instrLastInVPTBlock() {
108return VPTStates.size() == 1;
111void setVPTState(
char Mask) {
112// (3 - the number of trailing zeros) is the number of then / else. 113unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask);
114assert(NumTZ <= 3 &&
"Invalid VPT mask!");
115// push predicates onto the stack the correct order for the pops 116for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
117boolT = ((Mask >> Pos) & 1) == 0;
130/// ARM disassembler for all ARM platforms. 133 std::unique_ptr<const MCInstrInfo> MCII;
138 InstructionEndianness = STI.
hasFeature(ARM::ModeBigEndianInstructions)
143 ~ARMDisassembler()
override =
default;
161mutable ITStatus ITBlock;
162mutable VPTStatus VPTBlock;
164void AddThumb1SBit(
MCInst &
MI,
bool InITBlock)
const;
172}
// end anonymous namespace 174// Forward declare these because the autogenerated code will reference them. 175// Definitions are further down. 553template <
int shift,
int WriteBack>
615template <
bool isSigned,
bool isNeg,
bool zeroPermitted,
int size>
653template <
bool Writeback>
669template <
unsigned MinLog,
unsigned MaxLog>
673template <
unsigned start>
689template <
bool scalar, OperandDecoder predicate_decoder>
707#include "ARMGenDisassemblerTables.inc" 712returnnew ARMDisassembler(STI, Ctx,
T.createMCInstrInfo());
715// Post-decoding checks 720switch (
MI.getOpcode()) {
722// HVC is undefined if condition = 0xf otherwise upredictable 723// if condition != 0xe 739if (
MI.getOperand(0).getReg() == ARM::SP &&
740MI.getOperand(1).getReg() != ARM::SP)
743default:
return Result;
749// In Arm state, instructions are always 4 bytes wide, so there's no 750// point in skipping any smaller number of bytes if an instruction 752if (!STI.hasFeature(ARM::ModeThumb))
755// In a Thumb instruction stream, a halfword is a standalone 2-byte 756// instruction if and only if its value is less than 0xE800. 757// Otherwise, it's the first halfword of a 4-byte instruction. 759// So, if we can see the upcoming halfword, we can judge on that 760// basis, and maybe skip a whole 4-byte instruction that we don't 761// know how to decode, without accidentally trying to interpret its 762// second half as something else. 764// If we don't have the instruction data available, we just have to 765// recommend skipping the minimum sensible distance, which is 2 770uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
771 Bytes.
data(), InstructionEndianness);
772return Insn16 < 0xE800 ? 2 : 4;
779if (STI.hasFeature(ARM::ModeThumb))
780return getThumbInstruction(
MI,
Size, Bytes, Address, CS);
781return getARMInstruction(
MI,
Size, Bytes, Address, CS);
790assert(!STI.hasFeature(ARM::ModeThumb) &&
791"Asked to disassemble an ARM instruction but Subtarget is in Thumb " 794// We want to read exactly 4 bytes of data. 795if (Bytes.
size() < 4) {
800// Encoded as a 32-bit word in the stream. 802 InstructionEndianness);
804// Calling the auto-generated decoder function. 806 decodeInstruction(DecoderTableARM32,
MI,
Insn, Address,
this, STI);
817const DecodeTable Tables[] = {
818 {DecoderTableVFP32,
false}, {DecoderTableVFPV832,
false},
819 {DecoderTableNEONData32,
true}, {DecoderTableNEONLoadStore32,
true},
820 {DecoderTableNEONDup32,
true}, {DecoderTablev8NEON32,
false},
821 {DecoderTablev8Crypto32,
false},
824for (
auto Table : Tables) {
825Result = decodeInstruction(Table.P,
MI,
Insn, Address,
this, STI);
828// Add a fake predicate operand, because we share these instruction 829// definitions with Thumb2 where these instructions are predicable. 837 decodeInstruction(DecoderTableCoProc32,
MI,
Insn, Address,
this, STI);
847/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 848/// immediate Value in the MCInst. The immediate Value has had any PC 849/// adjustment made by the caller. If the instruction is a branch instruction 850/// then isBranch is true, else false. If the getOpInfo() function was set as 851/// part of the setupForSymbolicDisassembly() call then that function is called 852/// to get any symbolic information at the Address for this instruction. If 853/// that returns non-zero then the symbolic information it returns is used to 854/// create an MCExpr and that is added as an operand to the MCInst. If 855/// getOpInfo() returns zero and isBranch is true then a symbol look up for 856/// Value is done and if a symbol is found an MCExpr is created with that, else 857/// an MCExpr with Value is created. This function returns true if it adds an 858/// operand to the MCInst and false otherwise. 863// FIXME: Does it make sense for value to be negative? 869/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 870/// referenced by a load instruction with the base register that is the Pc. 871/// These can often be values in a literal pool near the Address of the 872/// instruction. The Address of the instruction and its immediate Value are 873/// used as a possible literal pool entry. The SymbolLookUp call back will 874/// return the name of a symbol referenced by the literal pool's entry if 875/// the referenced address is that of a symbol. Or it will return a pointer to 876/// a literal 'C' string if the referenced address of the literal pool's entry 877/// is an address into a section with 'C' string literals. 884// Thumb1 instructions don't have explicit S bits. Rather, they 885// implicitly set CPSR. Since it's not represented in the encoding, the 886// auto-generated decoder won't inject the CPSR operand. We need to fix 887// that as a post-pass. 888void ARMDisassembler::AddThumb1SBit(
MCInst &
MI,
bool InITBlock)
const{
892if (
I ==
MI.end())
break;
893if (MCID.
operands()[i].isOptionalDef() &&
894 MCID.
operands()[i].RegClass == ARM::CCRRegClassID) {
895if (i > 0 && MCID.
operands()[i - 1].isPredicate())
906bool ARMDisassembler::isVectorPredicable(
constMCInst &
MI)
const{
915// Most Thumb instructions don't have explicit predicates in the 916// encoding, but rather get their predicates from IT context. We need 917// to fix up the predicate operands using this context information as a 920ARMDisassembler::AddThumbPredicate(
MCInst &
MI)
const{
923constFeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
925// A few instructions actually have predicates encoded in them. Don't 926// try to overwrite it if we're seeing one of those. 927switch (
MI.getOpcode()) {
942// Some instructions (mostly conditional branches) are not 943// allowed in IT blocks. 944if (ITBlock.instrInITBlock())
950if (
MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
957// Some instructions (mostly unconditional branches) can 958// only appears at the end of, or outside of, an IT. 959if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
966// Warn on non-VPT predicable instruction in a VPT block and a VPT 967// predicable instruction in an IT block 972// If we're in an IT/VPT block, base the predicate on that. Otherwise, 973// assume a predicate of AL. 976if (ITBlock.instrInITBlock()) {
977CC = ITBlock.getITCC();
978 ITBlock.advanceITState();
979 }
elseif (VPTBlock.instrInVPTBlock()) {
980 VCC = VPTBlock.getVPTPred();
981 VPTBlock.advanceVPTState();
987for (
unsigned i = 0; i < MCID.
NumOperands; ++i, ++CCI) {
988if (MCID.
operands()[i].isPredicate() || CCI ==
MI.end())
1005for (VCCPos = 0; VCCPos < MCID.
NumOperands; ++VCCPos, ++VCCI) {
1023"Inactive register in vpred_r is not tied to an output!");
1024// Copy the operand to ensure it's not invalidated when MI grows. 1034// Thumb VFP instructions are a special case. Because we share their 1035// encodings between ARM and Thumb modes, and they are predicable in ARM 1036// mode, the auto-generated decoder will give them an (incorrect) 1037// predicate operand. We need to rewrite these operands based on the IT 1038// context as a post-pass. 1039void ARMDisassembler::UpdateThumbVFPPredicate(
1042CC = ITBlock.getITCC();
1045if (ITBlock.instrInITBlock())
1046 ITBlock.advanceITState();
1047elseif (VPTBlock.instrInVPTBlock()) {
1048CC = VPTBlock.getVPTPred();
1049 VPTBlock.advanceVPTState();
1056for (
unsigned i = 0; i < NumOps; ++i, ++
I) {
1057if (OpInfo[i].isPredicate() ) {
1063I->setReg(ARM::NoRegister);
1065I->setReg(ARM::CPSR);
1075 CommentStream = &CS;
1077assert(STI.hasFeature(ARM::ModeThumb) &&
1078"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
1080// We want to read exactly 2 bytes of data. 1081if (Bytes.
size() < 2) {
1086uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
1087 Bytes.
data(), InstructionEndianness);
1089 decodeInstruction(DecoderTableThumb16,
MI, Insn16, Address,
this, STI);
1092Check(Result, AddThumbPredicate(
MI));
1096Result = decodeInstruction(DecoderTableThumbSBit16,
MI, Insn16, Address,
this,
1100bool InITBlock = ITBlock.instrInITBlock();
1101Check(Result, AddThumbPredicate(
MI));
1102 AddThumb1SBit(
MI, InITBlock);
1107 decodeInstruction(DecoderTableThumb216,
MI, Insn16, Address,
this, STI);
1111// Nested IT blocks are UNPREDICTABLE. Must be checked before we add 1112// the Thumb predicate. 1113if (
MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
1116Check(Result, AddThumbPredicate(
MI));
1118// If we find an IT instruction, we need to parse its condition 1119// code and mask operands so that we can apply them correctly 1120// to the subsequent instructions. 1121if (
MI.getOpcode() == ARM::t2IT) {
1122unsigned Firstcond =
MI.getOperand(0).getImm();
1123unsignedMask =
MI.getOperand(1).getImm();
1124 ITBlock.setITState(Firstcond, Mask);
1126// An IT instruction that would give a 'NV' predicate is unpredictable. 1128 CS <<
"unpredictable IT predicate sequence";
1134// We want to read exactly 4 bytes of data. 1135if (Bytes.
size() < 4) {
1141 (
uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>(
1142 Bytes.
data() + 2, InstructionEndianness);
1145 decodeInstruction(DecoderTableMVE32,
MI, Insn32, Address,
this, STI);
1149// Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 1150// the VPT predicate. 1151if (
isVPTOpcode(
MI.getOpcode()) && VPTBlock.instrInVPTBlock())
1154Check(Result, AddThumbPredicate(
MI));
1157unsignedMask =
MI.getOperand(0).getImm();
1158 VPTBlock.setVPTState(Mask);
1165 decodeInstruction(DecoderTableThumb32,
MI, Insn32, Address,
this, STI);
1168bool InITBlock = ITBlock.instrInITBlock();
1169Check(Result, AddThumbPredicate(
MI));
1170 AddThumb1SBit(
MI, InITBlock);
1175 decodeInstruction(DecoderTableThumb232,
MI, Insn32, Address,
this, STI);
1178Check(Result, AddThumbPredicate(
MI));
1182if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1184 decodeInstruction(DecoderTableVFP32,
MI, Insn32, Address,
this, STI);
1187 UpdateThumbVFPPredicate(Result,
MI);
1193 decodeInstruction(DecoderTableVFPV832,
MI, Insn32, Address,
this, STI);
1199if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1200Result = decodeInstruction(DecoderTableNEONDup32,
MI, Insn32, Address,
this,
1204Check(Result, AddThumbPredicate(
MI));
1209if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1211 NEONLdStInsn &= 0xF0FFFFFF;
1212 NEONLdStInsn |= 0x04000000;
1213Result = decodeInstruction(DecoderTableNEONLoadStore32,
MI, NEONLdStInsn,
1217Check(Result, AddThumbPredicate(
MI));
1222if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1224 NEONDataInsn &= 0xF0FFFFFF;
// Clear bits 27-24 1225 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4;
// Move bit 28 to bit 24 1226 NEONDataInsn |= 0x12000000;
// Set bits 28 and 25 1227Result = decodeInstruction(DecoderTableNEONData32,
MI, NEONDataInsn,
1231Check(Result, AddThumbPredicate(
MI));
1236 NEONCryptoInsn &= 0xF0FFFFFF;
// Clear bits 27-24 1237 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4;
// Move bit 28 to bit 24 1238 NEONCryptoInsn |= 0x12000000;
// Set bits 28 and 25 1239Result = decodeInstruction(DecoderTablev8Crypto32,
MI, NEONCryptoInsn,
1247 NEONv8Insn &= 0xF3FFFFFF;
// Clear bits 27-26 1248Result = decodeInstruction(DecoderTablev8NEON32,
MI, NEONv8Insn, Address,
1256uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
1258 ? DecoderTableThumb2CDE32
1259 : DecoderTableThumb2CoProc32;
1261 decodeInstruction(DecoderTable,
MI, Insn32, Address,
this, STI);
1264Check(Result, AddThumbPredicate(
MI));
1284 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1285 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1286 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1287 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1291 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1292 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1293 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1294 ARM::R12, 0, ARM::LR, ARM::APSR
1400 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1401 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1409// According to the Arm ARM RegNo = 14 is undefined, but we return fail 1410// rather than SoftFail as there is no GPRPair table entry for index 7. 1431if ((RegNo & 1) || RegNo > 10)
1484 ((
constMCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1486if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1494 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1495 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1496 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1497 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1498 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1499 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1500 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1501 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1522 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1523 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1524 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1525 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1526ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1527 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1528 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1529 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1532// Does this instruction/subtarget permit use of registers d16-d31? 1537 ((
constMCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1538return featureBits[ARM::FeatureD32];
1544if (RegNo > (
PermitsD32(Inst, Decoder) ? 31u : 15u))
1577 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1578 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1579 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1580 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1586if (RegNo > 31 || (RegNo & 1) != 0)
1596 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1597 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1598 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1599 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1600 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1616 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1617 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1618 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1619 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1620 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1621 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1622 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1623 ARM::D28_D30, ARM::D29_D31
1642// AL predicate is not allowed on Thumb1 branches. 1643if (Inst.
getOpcode() == ARM::tBcc && Val == 0xE)
1646static_cast<constARMDisassembler *
>(Decoder)->MCII.
get();
1672unsigned Rm = fieldFromInstruction(Val, 0, 4);
1673unsigned type = fieldFromInstruction(Val, 5, 2);
1674unsigned imm = fieldFromInstruction(Val, 7, 5);
1676// Register-immediate 1699unsignedOp = Shift | (imm << 3);
1710unsigned Rm = fieldFromInstruction(Val, 0, 4);
1711unsigned type = fieldFromInstruction(Val, 5, 2);
1712unsigned Rs = fieldFromInstruction(Val, 8, 4);
1746bool NeedDisjointWriteback =
false;
1756case ARM::t2LDMIA_UPD:
1757case ARM::t2LDMDB_UPD:
1758case ARM::t2STMIA_UPD:
1759case ARM::t2STMDB_UPD:
1760 NeedDisjointWriteback =
true;
1768// Empty register lists are not allowed. 1770for (
unsigned i = 0; i < 16; ++i) {
1771if (Val & (1 << i)) {
1779// Writeback not allowed if Rn is in the target list. 1780if (NeedDisjointWriteback && WritebackReg == Inst.
end()[-1].getReg())
1794unsigned Vd = fieldFromInstruction(Val, 8, 5);
1795unsigned regs = fieldFromInstruction(Val, 0, 8);
1797// In case of unpredictable encoding, tweak the operands. 1798if (regs == 0 || (Vd + regs) > 32) {
1799 regs = Vd + regs > 32 ? 32 - Vd : regs;
1800 regs = std::max( 1u, regs);
1806for (
unsigned i = 0; i < (regs - 1); ++i) {
1819unsigned Vd = fieldFromInstruction(Val, 8, 5);
1820unsigned regs = fieldFromInstruction(Val, 1, 7);
1822// In case of unpredictable encoding, tweak the operands. 1823unsigned MaxReg =
PermitsD32(Inst, Decoder) ? 32 : 16;
1824if (regs == 0 || (Vd + regs) > MaxReg) {
1825 regs = Vd + regs > MaxReg ? MaxReg - Vd : regs;
1826 regs = std::max( 1u, regs);
1827 regs = std::min(MaxReg, regs);
1833for (
unsigned i = 0; i < (regs - 1); ++i) {
1844// This operand encodes a mask of contiguous zeros between a specified MSB 1845// and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1846// the mask of all bits LSB-and-lower, and then xor them to create 1847// the mask of that's all ones on [msb, lsb]. Finally we not it to 1848// create the final mask. 1849unsigned msb = fieldFromInstruction(Val, 5, 5);
1850unsigned lsb = fieldFromInstruction(Val, 0, 5);
1855// The check above will cause the warning for the "potentially undefined 1856// instruction encoding" but we can't build a bad MCOperand value here 1857// with a lsb > msb or else printing the MCInst will cause a crash. 1862if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1863uint32_t lsb_mask = (1U << lsb) - 1;
1874unsignedpred = fieldFromInstruction(
Insn, 28, 4);
1875unsigned CRd = fieldFromInstruction(
Insn, 12, 4);
1876unsigned coproc = fieldFromInstruction(
Insn, 8, 4);
1877unsigned imm = fieldFromInstruction(
Insn, 0, 8);
1878unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
1879unsigned U = fieldFromInstruction(
Insn, 23, 1);
1881 ((
constMCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1884case ARM::LDC_OFFSET:
1887case ARM::LDC_OPTION:
1888case ARM::LDCL_OFFSET:
1891case ARM::LDCL_OPTION:
1892case ARM::STC_OFFSET:
1895case ARM::STC_OPTION:
1896case ARM::STCL_OFFSET:
1899case ARM::STCL_OPTION:
1900case ARM::t2LDC_OFFSET:
1902case ARM::t2LDC_POST:
1903case ARM::t2LDC_OPTION:
1904case ARM::t2LDCL_OFFSET:
1905case ARM::t2LDCL_PRE:
1906case ARM::t2LDCL_POST:
1907case ARM::t2LDCL_OPTION:
1908case ARM::t2STC_OFFSET:
1910case ARM::t2STC_POST:
1911case ARM::t2STC_OPTION:
1912case ARM::t2STCL_OFFSET:
1913case ARM::t2STCL_PRE:
1914case ARM::t2STCL_POST:
1915case ARM::t2STCL_OPTION:
1916case ARM::t2LDC2_OFFSET:
1917case ARM::t2LDC2L_OFFSET:
1918case ARM::t2LDC2_PRE:
1919case ARM::t2LDC2L_PRE:
1920case ARM::t2STC2_OFFSET:
1921case ARM::t2STC2L_OFFSET:
1922case ARM::t2STC2_PRE:
1923case ARM::t2STC2L_PRE:
1924case ARM::LDC2_OFFSET:
1925case ARM::LDC2L_OFFSET:
1928case ARM::STC2_OFFSET:
1929case ARM::STC2L_OFFSET:
1932case ARM::t2LDC2_OPTION:
1933case ARM::t2STC2_OPTION:
1934case ARM::t2LDC2_POST:
1935case ARM::t2LDC2L_POST:
1936case ARM::t2STC2_POST:
1937case ARM::t2STC2L_POST:
1939case ARM::LDC2L_POST:
1941case ARM::STC2L_POST:
1942if (coproc == 0xA || coproc == 0xB ||
1943 (featureBits[ARM::HasV8_1MMainlineOps] &&
1944 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1945 coproc == 0xE || coproc == 0xF)))
1952if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1961case ARM::t2LDC2_OFFSET:
1962case ARM::t2LDC2L_OFFSET:
1963case ARM::t2LDC2_PRE:
1964case ARM::t2LDC2L_PRE:
1965case ARM::t2STC2_OFFSET:
1966case ARM::t2STC2L_OFFSET:
1967case ARM::t2STC2_PRE:
1968case ARM::t2STC2L_PRE:
1969case ARM::LDC2_OFFSET:
1970case ARM::LDC2L_OFFSET:
1973case ARM::STC2_OFFSET:
1974case ARM::STC2L_OFFSET:
1977case ARM::t2LDC_OFFSET:
1978case ARM::t2LDCL_OFFSET:
1980case ARM::t2LDCL_PRE:
1981case ARM::t2STC_OFFSET:
1982case ARM::t2STCL_OFFSET:
1984case ARM::t2STCL_PRE:
1985case ARM::LDC_OFFSET:
1986case ARM::LDCL_OFFSET:
1989case ARM::STC_OFFSET:
1990case ARM::STCL_OFFSET:
1996case ARM::t2LDC2_POST:
1997case ARM::t2LDC2L_POST:
1998case ARM::t2STC2_POST:
1999case ARM::t2STC2L_POST:
2001case ARM::LDC2L_POST:
2003case ARM::STC2L_POST:
2004case ARM::t2LDC_POST:
2005case ARM::t2LDCL_POST:
2006case ARM::t2STC_POST:
2007case ARM::t2STCL_POST:
2015// The 'option' variant doesn't encode 'U' in the immediate since 2016// the immediate is unsigned [0,255]. 2022case ARM::LDC_OFFSET:
2025case ARM::LDC_OPTION:
2026case ARM::LDCL_OFFSET:
2029case ARM::LDCL_OPTION:
2030case ARM::STC_OFFSET:
2033case ARM::STC_OPTION:
2034case ARM::STCL_OFFSET:
2037case ARM::STCL_OPTION:
2053unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2054unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
2055unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2056unsigned imm = fieldFromInstruction(
Insn, 0, 12);
2057unsignedpred = fieldFromInstruction(
Insn, 28, 4);
2058unsigned reg = fieldFromInstruction(
Insn, 25, 1);
2059unsignedP = fieldFromInstruction(
Insn, 24, 1);
2060unsigned W = fieldFromInstruction(
Insn, 21, 1);
2062// On stores, the writeback operand precedes Rt. 2064case ARM::STR_POST_IMM:
2065case ARM::STR_POST_REG:
2066case ARM::STRB_POST_IMM:
2067case ARM::STRB_POST_REG:
2068case ARM::STRT_POST_REG:
2069case ARM::STRT_POST_IMM:
2070case ARM::STRBT_POST_REG:
2071case ARM::STRBT_POST_IMM:
2082// On loads, the writeback operand comes after Rt. 2084case ARM::LDR_POST_IMM:
2085case ARM::LDR_POST_REG:
2086case ARM::LDRB_POST_IMM:
2087case ARM::LDRB_POST_REG:
2088case ARM::LDRBT_POST_REG:
2089case ARM::LDRBT_POST_IMM:
2090case ARM::LDRT_POST_REG:
2091case ARM::LDRT_POST_IMM:
2103if (!fieldFromInstruction(
Insn, 23, 1))
2106bool writeback = (
P == 0) || (W == 1);
2107unsigned idx_mode = 0;
2110elseif (!
P && writeback)
2113if (writeback && (Rn == 15 || Rn == Rt))
2120switch( fieldFromInstruction(
Insn, 5, 2)) {
2136unsigned amt = fieldFromInstruction(
Insn, 7, 5);
2159unsigned Rn = fieldFromInstruction(Val, 13, 4);
2160unsigned Rm = fieldFromInstruction(Val, 0, 4);
2161unsigned type = fieldFromInstruction(Val, 5, 2);
2162unsigned imm = fieldFromInstruction(Val, 7, 5);
2163unsigned U = fieldFromInstruction(Val, 12, 1);
2204// The "csync" operand is not encoded into the "tsb" instruction (as this is 2205// the only available operand), but LLVM expects the instruction to have one 2206// operand, so we need to add the csync when decoding. 2216unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
2217unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2218unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2219unsigned type = fieldFromInstruction(
Insn, 22, 1);
2220unsigned imm = fieldFromInstruction(
Insn, 8, 4);
2221unsigned U = ((~fieldFromInstruction(
Insn, 23, 1)) & 1) << 8;
2222unsignedpred = fieldFromInstruction(
Insn, 28, 4);
2223unsigned W = fieldFromInstruction(
Insn, 21, 1);
2224unsignedP = fieldFromInstruction(
Insn, 24, 1);
2225unsigned Rt2 = Rt + 1;
2227bool writeback = (W == 1) | (
P == 0);
2229// For {LD,ST}RD, Rt must be even, else undefined. 2246if (
P == 0 && W == 1)
2249if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2251if (type && Rm == 15)
2255if (!type && fieldFromInstruction(
Insn, 8, 4))
2263if (writeback && (Rn == 15 || Rn == Rt))
2265if (!type && Rm == 15)
2271if (type && Rn == 15) {
2276if (
P == 0 && W == 1)
2278if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2280if (!type && writeback && Rn == 15)
2282if (writeback && (Rn == Rt || Rn == Rt2))
2288if (type && Rn == 15) {
2295if (!type && Rm == 15)
2297if (!type && writeback && (Rn == 15 || Rn == Rt))
2302case ARM::LDRSH_POST:
2305case ARM::LDRSB_POST:
2306if (type && Rn == 15) {
2311if (type && (Rt == 15 || (writeback && Rn == Rt)))
2313if (!type && (Rt == 15 || Rm == 15))
2315if (!type && writeback && (Rn == 15 || Rn == Rt))
2322if (writeback) {
// Writeback 2328// On stores, the writeback operand precedes Rt. 2361// On loads, the writeback operand comes after Rt. 2371case ARM::LDRSH_POST:
2374case ARM::LDRSB_POST:
2408unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2409unsignedmode = fieldFromInstruction(
Insn, 23, 2);
2438unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
2439unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2440unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2441unsignedpred = fieldFromInstruction(
Insn, 28, 4);
2463unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2464unsignedpred = fieldFromInstruction(
Insn, 28, 4);
2465unsigned reglist = fieldFromInstruction(
Insn, 0, 16);
2468// Ambiguous with RFE and SRS 2522// For stores (which become SRS's, the only operand is the mode. 2523if (fieldFromInstruction(
Insn, 20, 1) == 0) {
2524// Check SRS encoding constraints 2525if (!(fieldFromInstruction(
Insn, 22, 1) == 1 &&
2526 fieldFromInstruction(
Insn, 20, 1) == 0))
2549// Check for UNPREDICTABLE predicated ESB instruction 2553unsignedpred = fieldFromInstruction(
Insn, 28, 4);
2554unsigned imm8 = fieldFromInstruction(
Insn, 0, 8);
2565// ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2566// so all predicates should be allowed. 2567if (imm8 == 0x10 &&
pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2576unsigned imod = fieldFromInstruction(
Insn, 18, 2);
2577unsigned M = fieldFromInstruction(
Insn, 17, 1);
2578unsigned iflags = fieldFromInstruction(
Insn, 6, 3);
2579unsignedmode = fieldFromInstruction(
Insn, 0, 5);
2583// This decoder is called from multiple location that do not check 2584// the full encoding is valid before they do. 2585if (fieldFromInstruction(
Insn, 5, 1) != 0 ||
2586 fieldFromInstruction(
Insn, 16, 1) != 0 ||
2587 fieldFromInstruction(
Insn, 20, 8) != 0x10)
2590// imod == '01' --> UNPREDICTABLE 2591// NOTE: Even though this is technically UNPREDICTABLE, we choose to 2592// return failure here. The '01' imod value is unprintable, so there's 2593// nothing useful we could do even if we returned UNPREDICTABLE. 2602 }
elseif (imod && !M) {
2607 }
elseif (!imod && M) {
2612// imod == '00' && M == '0' --> UNPREDICTABLE 2624unsigned imod = fieldFromInstruction(
Insn, 9, 2);
2625unsigned M = fieldFromInstruction(
Insn, 8, 1);
2626unsigned iflags = fieldFromInstruction(
Insn, 5, 3);
2627unsignedmode = fieldFromInstruction(
Insn, 0, 5);
2631// imod == '01' --> UNPREDICTABLE 2632// NOTE: Even though this is technically UNPREDICTABLE, we choose to 2633// return failure here. The '01' imod value is unprintable, so there's 2634// nothing useful we could do even if we returned UNPREDICTABLE. 2643 }
elseif (imod && !M) {
2648 }
elseif (!imod && M) {
2653// imod == '00' && M == '0' --> this is a HINT instruction 2654int imm = fieldFromInstruction(
Insn, 0, 8);
2655// HINT are defined only for immediate in [0..4] 2667unsigned imm = fieldFromInstruction(
Insn, 0, 8);
2669unsigned Opcode = ARM::t2HINT;
2672 Opcode = ARM::t2PACBTI;
2673 }
elseif (imm == 0x1D) {
2674 Opcode = ARM::t2PAC;
2675 }
elseif (imm == 0x2D) {
2676 Opcode = ARM::t2AUT;
2677 }
elseif (imm == 0x0F) {
2678 Opcode = ARM::t2BTI;
2682if (Opcode == ARM::t2HINT) {
2694unsigned Rd = fieldFromInstruction(
Insn, 8, 4);
2697 imm |= (fieldFromInstruction(
Insn, 0, 8) << 0);
2698 imm |= (fieldFromInstruction(
Insn, 12, 3) << 8);
2699 imm |= (fieldFromInstruction(
Insn, 16, 4) << 12);
2700 imm |= (fieldFromInstruction(
Insn, 26, 1) << 11);
2719unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
2720unsignedpred = fieldFromInstruction(
Insn, 28, 4);
2723 imm |= (fieldFromInstruction(
Insn, 0, 12) << 0);
2724 imm |= (fieldFromInstruction(
Insn, 16, 4) << 12);
2747unsigned Rd = fieldFromInstruction(
Insn, 16, 4);
2748unsigned Rn = fieldFromInstruction(
Insn, 0, 4);
2749unsigned Rm = fieldFromInstruction(
Insn, 8, 4);
2750unsigned Ra = fieldFromInstruction(
Insn, 12, 4);
2751unsignedpred = fieldFromInstruction(
Insn, 28, 4);
2776unsigned Pred = fieldFromInstruction(
Insn, 28, 4);
2777unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2778unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2798unsigned Imm = fieldFromInstruction(
Insn, 9, 1);
2803if (!FeatureBits[ARM::HasV8_1aOps] ||
2804 !FeatureBits[ARM::HasV8Ops])
2807// Decoder can be called from DecodeTST, which does not check the full 2808// encoding is valid. 2809if (fieldFromInstruction(
Insn, 20,12) != 0xf11 ||
2810 fieldFromInstruction(
Insn, 4,4) != 0)
2812if (fieldFromInstruction(
Insn, 10,10) != 0 ||
2813 fieldFromInstruction(
Insn, 0,4) != 0)
2827unsigned add = fieldFromInstruction(Val, 12, 1);
2828unsigned imm = fieldFromInstruction(Val, 0, 12);
2829unsigned Rn = fieldFromInstruction(Val, 13, 4);
2835if (imm == 0 && !add) imm = INT32_MIN;
2848unsigned Rn = fieldFromInstruction(Val, 9, 4);
2849// U == 1 to add imm, 0 to subtract it. 2850unsigned U = fieldFromInstruction(Val, 8, 1);
2851unsigned imm = fieldFromInstruction(Val, 0, 8);
2869unsigned Rn = fieldFromInstruction(Val, 9, 4);
2870// U == 1 to add imm, 0 to subtract it. 2871unsigned U = fieldFromInstruction(Val, 8, 1);
2872unsigned imm = fieldFromInstruction(Val, 0, 8);
2896// Note the J1 and J2 values are from the encoded instruction. So here 2897// change them to I1 and I2 values via as documented: 2898// I1 = NOT(J1 EOR S); 2899// I2 = NOT(J2 EOR S); 2900// and build the imm32 with one trailing zero as documented: 2901// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2902unsigned S = fieldFromInstruction(
Insn, 26, 1);
2903unsigned J1 = fieldFromInstruction(
Insn, 13, 1);
2904unsigned J2 = fieldFromInstruction(
Insn, 11, 1);
2905unsigned I1 = !(J1 ^ S);
2906unsigned I2 = !(J2 ^ S);
2907unsigned imm10 = fieldFromInstruction(
Insn, 16, 10);
2908unsigned imm11 = fieldFromInstruction(
Insn, 0, 11);
2909unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2910int imm32 = SignExtend32<25>(tmp << 1);
2912true, 4, Inst, Decoder))
2923unsignedpred = fieldFromInstruction(
Insn, 28, 4);
2924unsigned imm = fieldFromInstruction(
Insn, 0, 24) << 2;
2928 imm |= fieldFromInstruction(
Insn, 24, 1) << 1;
2930true, 4, Inst, Decoder))
2936true, 4, Inst, Decoder))
2939// We already have BL_pred for BL w/ predicate, no need to add addition 2940// predicate opreands for BL 2953unsigned Rm = fieldFromInstruction(Val, 0, 4);
2954unsigned align = fieldFromInstruction(Val, 4, 2);
2971unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
2972 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
2973unsigned wb = fieldFromInstruction(
Insn, 16, 4);
2974unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2975 Rn |= fieldFromInstruction(
Insn, 4, 2) << 4;
2976unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2978// First output register 2980case ARM::VLD1q16:
case ARM::VLD1q32:
case ARM::VLD1q64:
case ARM::VLD1q8:
2981case ARM::VLD1q16wb_fixed:
case ARM::VLD1q16wb_register:
2982case ARM::VLD1q32wb_fixed:
case ARM::VLD1q32wb_register:
2983case ARM::VLD1q64wb_fixed:
case ARM::VLD1q64wb_register:
2984case ARM::VLD1q8wb_fixed:
case ARM::VLD1q8wb_register:
2985case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d8:
2986case ARM::VLD2d16wb_fixed:
case ARM::VLD2d16wb_register:
2987case ARM::VLD2d32wb_fixed:
case ARM::VLD2d32wb_register:
2988case ARM::VLD2d8wb_fixed:
case ARM::VLD2d8wb_register:
2995case ARM::VLD2b16wb_fixed:
2996case ARM::VLD2b16wb_register:
2997case ARM::VLD2b32wb_fixed:
2998case ARM::VLD2b32wb_register:
2999case ARM::VLD2b8wb_fixed:
3000case ARM::VLD2b8wb_register:
3009// Second output register 3014case ARM::VLD3d8_UPD:
3015case ARM::VLD3d16_UPD:
3016case ARM::VLD3d32_UPD:
3020case ARM::VLD4d8_UPD:
3021case ARM::VLD4d16_UPD:
3022case ARM::VLD4d32_UPD:
3029case ARM::VLD3q8_UPD:
3030case ARM::VLD3q16_UPD:
3031case ARM::VLD3q32_UPD:
3035case ARM::VLD4q8_UPD:
3036case ARM::VLD4q16_UPD:
3037case ARM::VLD4q32_UPD:
3045// Third output register 3050case ARM::VLD3d8_UPD:
3051case ARM::VLD3d16_UPD:
3052case ARM::VLD3d32_UPD:
3056case ARM::VLD4d8_UPD:
3057case ARM::VLD4d16_UPD:
3058case ARM::VLD4d32_UPD:
3065case ARM::VLD3q8_UPD:
3066case ARM::VLD3q16_UPD:
3067case ARM::VLD3q32_UPD:
3071case ARM::VLD4q8_UPD:
3072case ARM::VLD4q16_UPD:
3073case ARM::VLD4q32_UPD:
3081// Fourth output register 3086case ARM::VLD4d8_UPD:
3087case ARM::VLD4d16_UPD:
3088case ARM::VLD4d32_UPD:
3095case ARM::VLD4q8_UPD:
3096case ARM::VLD4q16_UPD:
3097case ARM::VLD4q32_UPD:
3107case ARM::VLD1d8wb_fixed:
3108case ARM::VLD1d16wb_fixed:
3109case ARM::VLD1d32wb_fixed:
3110case ARM::VLD1d64wb_fixed:
3111case ARM::VLD1d8wb_register:
3112case ARM::VLD1d16wb_register:
3113case ARM::VLD1d32wb_register:
3114case ARM::VLD1d64wb_register:
3115case ARM::VLD1q8wb_fixed:
3116case ARM::VLD1q16wb_fixed:
3117case ARM::VLD1q32wb_fixed:
3118case ARM::VLD1q64wb_fixed:
3119case ARM::VLD1q8wb_register:
3120case ARM::VLD1q16wb_register:
3121case ARM::VLD1q32wb_register:
3122case ARM::VLD1q64wb_register:
3123case ARM::VLD1d8Twb_fixed:
3124case ARM::VLD1d8Twb_register:
3125case ARM::VLD1d16Twb_fixed:
3126case ARM::VLD1d16Twb_register:
3127case ARM::VLD1d32Twb_fixed:
3128case ARM::VLD1d32Twb_register:
3129case ARM::VLD1d64Twb_fixed:
3130case ARM::VLD1d64Twb_register:
3131case ARM::VLD1d8Qwb_fixed:
3132case ARM::VLD1d8Qwb_register:
3133case ARM::VLD1d16Qwb_fixed:
3134case ARM::VLD1d16Qwb_register:
3135case ARM::VLD1d32Qwb_fixed:
3136case ARM::VLD1d32Qwb_register:
3137case ARM::VLD1d64Qwb_fixed:
3138case ARM::VLD1d64Qwb_register:
3139case ARM::VLD2d8wb_fixed:
3140case ARM::VLD2d16wb_fixed:
3141case ARM::VLD2d32wb_fixed:
3142case ARM::VLD2q8wb_fixed:
3143case ARM::VLD2q16wb_fixed:
3144case ARM::VLD2q32wb_fixed:
3145case ARM::VLD2d8wb_register:
3146case ARM::VLD2d16wb_register:
3147case ARM::VLD2d32wb_register:
3148case ARM::VLD2q8wb_register:
3149case ARM::VLD2q16wb_register:
3150case ARM::VLD2q32wb_register:
3151case ARM::VLD2b8wb_fixed:
3152case ARM::VLD2b16wb_fixed:
3153case ARM::VLD2b32wb_fixed:
3154case ARM::VLD2b8wb_register:
3155case ARM::VLD2b16wb_register:
3156case ARM::VLD2b32wb_register:
3159case ARM::VLD3d8_UPD:
3160case ARM::VLD3d16_UPD:
3161case ARM::VLD3d32_UPD:
3162case ARM::VLD3q8_UPD:
3163case ARM::VLD3q16_UPD:
3164case ARM::VLD3q32_UPD:
3165case ARM::VLD4d8_UPD:
3166case ARM::VLD4d16_UPD:
3167case ARM::VLD4d32_UPD:
3168case ARM::VLD4q8_UPD:
3169case ARM::VLD4q16_UPD:
3170case ARM::VLD4q32_UPD:
3178// AddrMode6 Base (register+alignment) 3182// AddrMode6 Offset (register) 3185// The below have been updated to have explicit am6offset split 3186// between fixed and register offset. For those instructions not 3187// yet updated, we need to add an additional reg0 operand for the 3190// The fixed offset encodes as Rm == 0xd, so we check for that. 3195// Fall through to handle the register offset variant. 3197case ARM::VLD1d8wb_fixed:
3198case ARM::VLD1d16wb_fixed:
3199case ARM::VLD1d32wb_fixed:
3200case ARM::VLD1d64wb_fixed:
3201case ARM::VLD1d8Twb_fixed:
3202case ARM::VLD1d16Twb_fixed:
3203case ARM::VLD1d32Twb_fixed:
3204case ARM::VLD1d64Twb_fixed:
3205case ARM::VLD1d8Qwb_fixed:
3206case ARM::VLD1d16Qwb_fixed:
3207case ARM::VLD1d32Qwb_fixed:
3208case ARM::VLD1d64Qwb_fixed:
3209case ARM::VLD1d8wb_register:
3210case ARM::VLD1d16wb_register:
3211case ARM::VLD1d32wb_register:
3212case ARM::VLD1d64wb_register:
3213case ARM::VLD1q8wb_fixed:
3214case ARM::VLD1q16wb_fixed:
3215case ARM::VLD1q32wb_fixed:
3216case ARM::VLD1q64wb_fixed:
3217case ARM::VLD1q8wb_register:
3218case ARM::VLD1q16wb_register:
3219case ARM::VLD1q32wb_register:
3220case ARM::VLD1q64wb_register:
3221// The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3222// variant encodes Rm == 0xf. Anything else is a register offset post- 3223// increment and we need to add the register operand to the instruction. 3224if (Rm != 0xD && Rm != 0xF &&
3228case ARM::VLD2d8wb_fixed:
3229case ARM::VLD2d16wb_fixed:
3230case ARM::VLD2d32wb_fixed:
3231case ARM::VLD2b8wb_fixed:
3232case ARM::VLD2b16wb_fixed:
3233case ARM::VLD2b32wb_fixed:
3234case ARM::VLD2q8wb_fixed:
3235case ARM::VLD2q16wb_fixed:
3236case ARM::VLD2q32wb_fixed:
3246unsigned type = fieldFromInstruction(
Insn, 8, 4);
3247unsigned align = fieldFromInstruction(
Insn, 4, 2);
3252unsignedload = fieldFromInstruction(
Insn, 21, 1);
3260unsignedsize = fieldFromInstruction(
Insn, 6, 2);
3263unsigned type = fieldFromInstruction(
Insn, 8, 4);
3264unsigned align = fieldFromInstruction(
Insn, 4, 2);
3268unsignedload = fieldFromInstruction(
Insn, 21, 1);
3276unsignedsize = fieldFromInstruction(
Insn, 6, 2);
3279unsigned align = fieldFromInstruction(
Insn, 4, 2);
3282unsignedload = fieldFromInstruction(
Insn, 21, 1);
3290unsignedsize = fieldFromInstruction(
Insn, 6, 2);
3293unsignedload = fieldFromInstruction(
Insn, 21, 1);
3303unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3304 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3305unsigned wb = fieldFromInstruction(
Insn, 16, 4);
3306unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3307 Rn |= fieldFromInstruction(
Insn, 4, 2) << 4;
3308unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3312case ARM::VST1d8wb_fixed:
3313case ARM::VST1d16wb_fixed:
3314case ARM::VST1d32wb_fixed:
3315case ARM::VST1d64wb_fixed:
3316case ARM::VST1d8wb_register:
3317case ARM::VST1d16wb_register:
3318case ARM::VST1d32wb_register:
3319case ARM::VST1d64wb_register:
3320case ARM::VST1q8wb_fixed:
3321case ARM::VST1q16wb_fixed:
3322case ARM::VST1q32wb_fixed:
3323case ARM::VST1q64wb_fixed:
3324case ARM::VST1q8wb_register:
3325case ARM::VST1q16wb_register:
3326case ARM::VST1q32wb_register:
3327case ARM::VST1q64wb_register:
3328case ARM::VST1d8Twb_fixed:
3329case ARM::VST1d16Twb_fixed:
3330case ARM::VST1d32Twb_fixed:
3331case ARM::VST1d64Twb_fixed:
3332case ARM::VST1d8Twb_register:
3333case ARM::VST1d16Twb_register:
3334case ARM::VST1d32Twb_register:
3335case ARM::VST1d64Twb_register:
3336case ARM::VST1d8Qwb_fixed:
3337case ARM::VST1d16Qwb_fixed:
3338case ARM::VST1d32Qwb_fixed:
3339case ARM::VST1d64Qwb_fixed:
3340case ARM::VST1d8Qwb_register:
3341case ARM::VST1d16Qwb_register:
3342case ARM::VST1d32Qwb_register:
3343case ARM::VST1d64Qwb_register:
3344case ARM::VST2d8wb_fixed:
3345case ARM::VST2d16wb_fixed:
3346case ARM::VST2d32wb_fixed:
3347case ARM::VST2d8wb_register:
3348case ARM::VST2d16wb_register:
3349case ARM::VST2d32wb_register:
3350case ARM::VST2q8wb_fixed:
3351case ARM::VST2q16wb_fixed:
3352case ARM::VST2q32wb_fixed:
3353case ARM::VST2q8wb_register:
3354case ARM::VST2q16wb_register:
3355case ARM::VST2q32wb_register:
3356case ARM::VST2b8wb_fixed:
3357case ARM::VST2b16wb_fixed:
3358case ARM::VST2b32wb_fixed:
3359case ARM::VST2b8wb_register:
3360case ARM::VST2b16wb_register:
3361case ARM::VST2b32wb_register:
3366case ARM::VST3d8_UPD:
3367case ARM::VST3d16_UPD:
3368case ARM::VST3d32_UPD:
3369case ARM::VST3q8_UPD:
3370case ARM::VST3q16_UPD:
3371case ARM::VST3q32_UPD:
3372case ARM::VST4d8_UPD:
3373case ARM::VST4d16_UPD:
3374case ARM::VST4d32_UPD:
3375case ARM::VST4q8_UPD:
3376case ARM::VST4q16_UPD:
3377case ARM::VST4q32_UPD:
3385// AddrMode6 Base (register+alignment) 3389// AddrMode6 Offset (register) 3399case ARM::VST1d8wb_fixed:
3400case ARM::VST1d16wb_fixed:
3401case ARM::VST1d32wb_fixed:
3402case ARM::VST1d64wb_fixed:
3403case ARM::VST1q8wb_fixed:
3404case ARM::VST1q16wb_fixed:
3405case ARM::VST1q32wb_fixed:
3406case ARM::VST1q64wb_fixed:
3407case ARM::VST1d8Twb_fixed:
3408case ARM::VST1d16Twb_fixed:
3409case ARM::VST1d32Twb_fixed:
3410case ARM::VST1d64Twb_fixed:
3411case ARM::VST1d8Qwb_fixed:
3412case ARM::VST1d16Qwb_fixed:
3413case ARM::VST1d32Qwb_fixed:
3414case ARM::VST1d64Qwb_fixed:
3415case ARM::VST2d8wb_fixed:
3416case ARM::VST2d16wb_fixed:
3417case ARM::VST2d32wb_fixed:
3418case ARM::VST2q8wb_fixed:
3419case ARM::VST2q16wb_fixed:
3420case ARM::VST2q32wb_fixed:
3421case ARM::VST2b8wb_fixed:
3422case ARM::VST2b16wb_fixed:
3423case ARM::VST2b32wb_fixed:
3427// First input register 3433case ARM::VST1q16wb_fixed:
3434case ARM::VST1q16wb_register:
3435case ARM::VST1q32wb_fixed:
3436case ARM::VST1q32wb_register:
3437case ARM::VST1q64wb_fixed:
3438case ARM::VST1q64wb_register:
3439case ARM::VST1q8wb_fixed:
3440case ARM::VST1q8wb_register:
3444case ARM::VST2d16wb_fixed:
3445case ARM::VST2d16wb_register:
3446case ARM::VST2d32wb_fixed:
3447case ARM::VST2d32wb_register:
3448case ARM::VST2d8wb_fixed:
3449case ARM::VST2d8wb_register:
3456case ARM::VST2b16wb_fixed:
3457case ARM::VST2b16wb_register:
3458case ARM::VST2b32wb_fixed:
3459case ARM::VST2b32wb_register:
3460case ARM::VST2b8wb_fixed:
3461case ARM::VST2b8wb_register:
3470// Second input register 3475case ARM::VST3d8_UPD:
3476case ARM::VST3d16_UPD:
3477case ARM::VST3d32_UPD:
3481case ARM::VST4d8_UPD:
3482case ARM::VST4d16_UPD:
3483case ARM::VST4d32_UPD:
3490case ARM::VST3q8_UPD:
3491case ARM::VST3q16_UPD:
3492case ARM::VST3q32_UPD:
3496case ARM::VST4q8_UPD:
3497case ARM::VST4q16_UPD:
3498case ARM::VST4q32_UPD:
3506// Third input register 3511case ARM::VST3d8_UPD:
3512case ARM::VST3d16_UPD:
3513case ARM::VST3d32_UPD:
3517case ARM::VST4d8_UPD:
3518case ARM::VST4d16_UPD:
3519case ARM::VST4d32_UPD:
3526case ARM::VST3q8_UPD:
3527case ARM::VST3q16_UPD:
3528case ARM::VST3q32_UPD:
3532case ARM::VST4q8_UPD:
3533case ARM::VST4q16_UPD:
3534case ARM::VST4q32_UPD:
3542// Fourth input register 3547case ARM::VST4d8_UPD:
3548case ARM::VST4d16_UPD:
3549case ARM::VST4d32_UPD:
3556case ARM::VST4q8_UPD:
3557case ARM::VST4q16_UPD:
3558case ARM::VST4q32_UPD:
3574unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3575 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3576unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3577unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3578unsigned align = fieldFromInstruction(
Insn, 4, 1);
3579unsignedsize = fieldFromInstruction(
Insn, 6, 2);
3581if (
size == 0 && align == 1)
3583 align *= (1 <<
size);
3586case ARM::VLD1DUPq16:
case ARM::VLD1DUPq32:
case ARM::VLD1DUPq8:
3587case ARM::VLD1DUPq16wb_fixed:
case ARM::VLD1DUPq16wb_register:
3588case ARM::VLD1DUPq32wb_fixed:
case ARM::VLD1DUPq32wb_register:
3589case ARM::VLD1DUPq8wb_fixed:
case ARM::VLD1DUPq8wb_register:
3607// The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3608// variant encodes Rm == 0xf. Anything else is a register offset post- 3609// increment and we need to add the register operand to the instruction. 3610if (Rm != 0xD && Rm != 0xF &&
3622unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3623 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3624unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3625unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3626unsigned align = fieldFromInstruction(
Insn, 4, 1);
3627unsignedsize = 1 << fieldFromInstruction(
Insn, 6, 2);
3631case ARM::VLD2DUPd16:
case ARM::VLD2DUPd32:
case ARM::VLD2DUPd8:
3632case ARM::VLD2DUPd16wb_fixed:
case ARM::VLD2DUPd16wb_register:
3633case ARM::VLD2DUPd32wb_fixed:
case ARM::VLD2DUPd32wb_register:
3634case ARM::VLD2DUPd8wb_fixed:
case ARM::VLD2DUPd8wb_register:
3638case ARM::VLD2DUPd16x2:
case ARM::VLD2DUPd32x2:
case ARM::VLD2DUPd8x2:
3639case ARM::VLD2DUPd16x2wb_fixed:
case ARM::VLD2DUPd16x2wb_register:
3640case ARM::VLD2DUPd32x2wb_fixed:
case ARM::VLD2DUPd32x2wb_register:
3641case ARM::VLD2DUPd8x2wb_fixed:
case ARM::VLD2DUPd8x2wb_register:
3658if (Rm != 0xD && Rm != 0xF) {
3671unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3672 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3673unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3674unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3675unsigned inc = fieldFromInstruction(
Insn, 5, 1) + 1;
3707unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3708 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3709unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3710unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3711unsignedsize = fieldFromInstruction(
Insn, 6, 2);
3712unsigned inc = fieldFromInstruction(
Insn, 5, 1) + 1;
3713unsigned align = fieldFromInstruction(
Insn, 4, 1);
3760unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3761 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3762unsigned imm = fieldFromInstruction(
Insn, 0, 4);
3763 imm |= fieldFromInstruction(
Insn, 16, 3) << 4;
3764 imm |= fieldFromInstruction(
Insn, 24, 1) << 7;
3765 imm |= fieldFromInstruction(
Insn, 8, 4) << 8;
3766 imm |= fieldFromInstruction(
Insn, 5, 1) << 12;
3767unsigned Q = fieldFromInstruction(
Insn, 6, 1);
3780case ARM::VORRiv4i16:
3781case ARM::VORRiv2i32:
3782case ARM::VBICiv4i16:
3783case ARM::VBICiv2i32:
3787case ARM::VORRiv8i16:
3788case ARM::VORRiv4i32:
3789case ARM::VBICiv8i16:
3790case ARM::VBICiv4i32:
3806unsigned Qd = ((fieldFromInstruction(
Insn, 22, 1) << 3) |
3807 fieldFromInstruction(
Insn, 13, 3));
3808unsigned cmode = fieldFromInstruction(
Insn, 8, 4);
3809unsigned imm = fieldFromInstruction(
Insn, 0, 4);
3810 imm |= fieldFromInstruction(
Insn, 16, 3) << 4;
3811 imm |= fieldFromInstruction(
Insn, 28, 1) << 7;
3813 imm |= fieldFromInstruction(
Insn, 5, 1) << 12;
3815if (cmode == 0xF && Inst.
getOpcode() == ARM::MVE_VMVNimmi32)
3835unsigned Qd = fieldFromInstruction(
Insn, 13, 3);
3836 Qd |= fieldFromInstruction(
Insn, 22, 1) << 3;
3841unsigned Qn = fieldFromInstruction(
Insn, 17, 3);
3842 Qn |= fieldFromInstruction(
Insn, 7, 1) << 3;
3845unsigned Qm = fieldFromInstruction(
Insn, 1, 3);
3846 Qm |= fieldFromInstruction(
Insn, 5, 1) << 3;
3849if (!fieldFromInstruction(
Insn, 12, 1))
// I bit clear => need input FPSCR 3861unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3862 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3863unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3864 Rm |= fieldFromInstruction(
Insn, 5, 1) << 4;
3865unsignedsize = fieldFromInstruction(
Insn, 18, 2);
3909unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3910 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3911unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3912 Rn |= fieldFromInstruction(
Insn, 7, 1) << 4;
3913unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3914 Rm |= fieldFromInstruction(
Insn, 5, 1) << 4;
3915unsignedop = fieldFromInstruction(
Insn, 6, 1);
3946unsigned dst = fieldFromInstruction(
Insn, 8, 3);
3947unsigned imm = fieldFromInstruction(
Insn, 0, 8);
3956break;
// tADR does not explicitly represent the PC as an operand. 3970true, 2, Inst, Decoder))
3979true, 4, Inst, Decoder))
3988true, 2, Inst, Decoder))
3998unsigned Rn = fieldFromInstruction(Val, 0, 3);
3999unsigned Rm = fieldFromInstruction(Val, 3, 3);
4014unsigned Rn = fieldFromInstruction(Val, 0, 3);
4015unsigned imm = fieldFromInstruction(Val, 3, 5);
4027unsigned imm = Val << 2;
4049unsigned Rn = fieldFromInstruction(Val, 6, 4);
4050unsigned Rm = fieldFromInstruction(Val, 2, 4);
4051unsigned imm = fieldFromInstruction(Val, 0, 2);
4053// Thumb stores cannot use PC as dest register. 4079unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4080unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4083 ((
constMCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4085bool hasMP = featureBits[ARM::FeatureMP];
4086bool hasV7Ops = featureBits[ARM::HasV7Ops];
4141if (!hasV7Ops || !hasMP)
4149unsigned addrmode = fieldFromInstruction(
Insn, 4, 2);
4150 addrmode |= fieldFromInstruction(
Insn, 0, 4) << 2;
4151 addrmode |= fieldFromInstruction(
Insn, 16, 4) << 6;
4163unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4164unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4165unsigned U = fieldFromInstruction(
Insn, 9, 1);
4166unsigned imm = fieldFromInstruction(
Insn, 0, 8);
4169unsigned add = fieldFromInstruction(
Insn, 9, 1);
4172 ((
constMCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4174bool hasMP = featureBits[ARM::FeatureMP];
4175bool hasV7Ops = featureBits[ARM::HasV7Ops];
4230if (!hasV7Ops || !hasMP)
4248unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4249unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4250unsigned imm = fieldFromInstruction(
Insn, 0, 12);
4254 ((
constMCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4256bool hasMP = featureBits[ARM::FeatureMP];
4257bool hasV7Ops = featureBits[ARM::HasV7Ops];
4267case ARM::t2LDRSHi12:
4273case ARM::t2LDRSBi12:
4290case ARM::t2LDRSHi12:
4295case ARM::t2LDRSBi12:
4311if (!hasV7Ops || !hasMP)
4328unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4329unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4330unsigned imm = fieldFromInstruction(
Insn, 0, 8);
4368unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4369unsigned U = fieldFromInstruction(
Insn, 23, 1);
4370int imm = fieldFromInstruction(
Insn, 0, 12);
4373 ((
constMCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4375bool hasV7Ops = featureBits[ARM::HasV7Ops];
4383case ARM::t2LDRSBpci:
4386case ARM::t2LDRSHpci:
4406// Special case for #-0. 4422int imm = Val & 0xFF;
4424if (!(Val & 0x100)) imm *= -1;
4436int imm = Val & 0x7F;
4451unsigned Rn = fieldFromInstruction(Val, 9, 4);
4452unsigned imm = fieldFromInstruction(Val, 0, 9);
4467unsigned Rn = fieldFromInstruction(Val, 8, 4);
4468unsigned imm = fieldFromInstruction(Val, 0, 8);
4483unsigned Rn = fieldFromInstruction(Val, 8, 4);
4484unsigned imm = fieldFromInstruction(Val, 0, 8);
4496int imm = Val & 0xFF;
4499elseif (!(Val & 0x100))
4509int imm = Val & 0x7F;
4512elseif (!(Val & 0x80))
4514if (imm != INT32_MIN)
4515 imm *= (1U << shift);
4526unsigned Rn = fieldFromInstruction(Val, 9, 4);
4527unsigned imm = fieldFromInstruction(Val, 0, 9);
4529// Thumb stores cannot use PC as dest register. 4544// Some instructions always use an additive offset. 4574unsigned Rn = fieldFromInstruction(Val, 8, 3);
4575unsigned imm = fieldFromInstruction(Val, 0, 8);
4579if (!
Check(S, DecodeT2Imm7<shift>(Inst, imm,
Address, Decoder)))
4585template <
int shift,
int WriteBack>
4591unsigned Rn = fieldFromInstruction(Val, 8, 4);
4592unsigned imm = fieldFromInstruction(Val, 0, 8);
4598if (!
Check(S, DecodeT2Imm7<shift>(Inst, imm,
Address, Decoder)))
4609unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4610unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4611unsigned addr = fieldFromInstruction(
Insn, 0, 8);
4612 addr |= fieldFromInstruction(
Insn, 9, 1) << 8;
4614unsignedload = fieldFromInstruction(
Insn, 20, 1);
4619case ARM::t2LDR_POST:
4622case ARM::t2LDRB_PRE:
4623case ARM::t2LDRB_POST:
4626case ARM::t2LDRH_PRE:
4627case ARM::t2LDRH_POST:
4630case ARM::t2LDRSB_PRE:
4631case ARM::t2LDRSB_POST:
4637case ARM::t2LDRSH_PRE:
4638case ARM::t2LDRSH_POST:
4671unsigned Rn = fieldFromInstruction(Val, 13, 4);
4672unsigned imm = fieldFromInstruction(Val, 0, 12);
4674// Thumb stores cannot use PC as dest register. 4696unsigned imm = fieldFromInstruction(
Insn, 0, 7);
4711unsigned Rdm = fieldFromInstruction(
Insn, 0, 3);
4712 Rdm |= fieldFromInstruction(
Insn, 7, 1) << 3;
4719 }
elseif (Inst.
getOpcode() == ARM::tADDspr) {
4720unsigned Rm = fieldFromInstruction(
Insn, 3, 4);
4734unsigned imod = fieldFromInstruction(
Insn, 4, 1) | 0x2;
4735unsigned flags = fieldFromInstruction(
Insn, 0, 3);
4747unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
4748unsigned add = fieldFromInstruction(
Insn, 4, 1);
4761unsigned Rn = fieldFromInstruction(
Insn, 3, 4);
4762unsigned Qm = fieldFromInstruction(
Insn, 0, 3);
4777unsigned Qm = fieldFromInstruction(
Insn, 8, 3);
4778int imm = fieldFromInstruction(
Insn, 0, 7);
4783if(!fieldFromInstruction(
Insn, 7, 1)) {
4785 imm = INT32_MIN;
// indicate -0 4789if (imm != INT32_MIN)
4790 imm *= (1U << shift);
4799// Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4800// Note only one trailing zero not two. Also the J1 and J2 values are from 4801// the encoded instruction. So here change to I1 and I2 values via: 4802// I1 = NOT(J1 EOR S); 4803// I2 = NOT(J2 EOR S); 4804// and build the imm32 with two trailing zeros as documented: 4805// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4806unsigned S = (Val >> 23) & 1;
4807unsigned J1 = (Val >> 22) & 1;
4808unsigned J2 = (Val >> 21) & 1;
4809unsigned I1 = !(J1 ^ S);
4810unsigned I2 = !(J2 ^ S);
4811unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4812int imm32 = SignExtend32<25>(tmp << 1);
4816true, 4, Inst, Decoder))
4824if (Val == 0xA || Val == 0xB)
4828 ((
constMCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4841 ((
constMCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4844unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4845unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
4860unsignedpred = fieldFromInstruction(
Insn, 22, 4);
4862unsigned opc = fieldFromInstruction(
Insn, 4, 28);
4877unsigned imm = fieldFromInstruction(
Insn, 0, 4);
4881unsigned brtarget = fieldFromInstruction(
Insn, 0, 11) << 1;
4882 brtarget |= fieldFromInstruction(
Insn, 11, 1) << 19;
4883 brtarget |= fieldFromInstruction(
Insn, 13, 1) << 18;
4884 brtarget |= fieldFromInstruction(
Insn, 16, 6) << 12;
4885 brtarget |= fieldFromInstruction(
Insn, 26, 1) << 20;
4895// Decode a shifted immediate operand. These basically consist 4896// of an 8-bit value, and a 4-bit directive that specifies either 4897// a splat operation or a rotation. 4900unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4902unsignedbyte = fieldFromInstruction(Val, 8, 2);
4903unsigned imm = fieldFromInstruction(Val, 0, 8);
4920unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4921unsigned rot = fieldFromInstruction(Val, 7, 5);
4922unsigned imm = llvm::rotr<uint32_t>(unrot, rot);
4933true, 2, Inst, Decoder))
4941// Val is passed in as S:J1:J2:imm10:imm11 4942// Note no trailing zero after imm11. Also the J1 and J2 values are from 4943// the encoded instruction. So here change to I1 and I2 values via: 4944// I1 = NOT(J1 EOR S); 4945// I2 = NOT(J2 EOR S); 4946// and build the imm32 with one trailing zero as documented: 4947// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4948unsigned S = (Val >> 23) & 1;
4949unsigned J1 = (Val >> 22) & 1;
4950unsigned J2 = (Val >> 21) & 1;
4951unsigned I1 = !(J1 ^ S);
4952unsigned I2 = !(J2 ^ S);
4953unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4954int imm32 = SignExtend32<25>(tmp << 1);
4957true, 4, Inst, Decoder))
4986 ((
constMCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4988if (FeatureBits[ARM::FeatureMClass]) {
4989unsigned ValLow = Val & 0xff;
4991// Validate the SYSm value first. 5006case 18:
// basepri_max 5008if (!(FeatureBits[ARM::HasV7Ops]))
5009// Values basepri, basepri_max and faultmask are only valid for v7m. 5012case 0x8a:
// msplim_ns 5013case 0x8b:
// psplim_ns 5014case 0x91:
// basepri_ns 5015case 0x93:
// faultmask_ns 5016if (!(FeatureBits[ARM::HasV8MMainlineOps]))
5023case 0x90:
// primask_ns 5024case 0x94:
// control_ns 5026if (!(FeatureBits[ARM::Feature8MSecExt]))
5029case 0x20:
// pac_key_p_0 5030case 0x21:
// pac_key_p_1 5031case 0x22:
// pac_key_p_2 5032case 0x23:
// pac_key_p_3 5033case 0x24:
// pac_key_u_0 5034case 0x25:
// pac_key_u_1 5035case 0x26:
// pac_key_u_2 5036case 0x27:
// pac_key_u_3 5037case 0xa0:
// pac_key_p_0_ns 5038case 0xa1:
// pac_key_p_1_ns 5039case 0xa2:
// pac_key_p_2_ns 5040case 0xa3:
// pac_key_p_3_ns 5041case 0xa4:
// pac_key_u_0_ns 5042case 0xa5:
// pac_key_u_1_ns 5043case 0xa6:
// pac_key_u_2_ns 5044case 0xa7:
// pac_key_u_3_ns 5045if (!(FeatureBits[ARM::FeaturePACBTI]))
5049// Architecturally defined as unpredictable 5055unsigned Mask = fieldFromInstruction(Val, 10, 2);
5056if (!(FeatureBits[ARM::HasV7Ops])) {
5057// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 5063// The ARMv7-M architecture stores an additional 2-bit mask value in 5064// MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 5065// xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 5066// the NZCVQ bits should be moved by the instruction. Bit mask{0} 5067// indicates the move for the GE{3:0} bits, the mask{0} bit can be set 5068// only if the processor includes the DSP extension. 5069if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
5070 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
5086unsigned R = fieldFromInstruction(Val, 5, 1);
5087unsigned SysM = fieldFromInstruction(Val, 0, 5);
5089// The table of encodings for these banked registers comes from B9.2.3 of the 5090// ARM ARM. There are patterns, but nothing regular enough to make this logic 5091// neater. So by fiat, these values are UNPREDICTABLE: 5092if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
5104unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
5105unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5106unsignedpred = fieldFromInstruction(
Insn, 28, 4);
5126unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
5127unsigned Rt = fieldFromInstruction(
Insn, 0, 4);
5128unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5129unsignedpred = fieldFromInstruction(
Insn, 28, 4);
5134if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
5152unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5153unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
5154unsigned imm = fieldFromInstruction(
Insn, 0, 12);
5155 imm |= fieldFromInstruction(
Insn, 16, 4) << 13;
5156 imm |= fieldFromInstruction(
Insn, 23, 1) << 12;
5157unsignedpred = fieldFromInstruction(
Insn, 28, 4);
5178unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5179unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
5180unsigned imm = fieldFromInstruction(
Insn, 0, 12);
5181 imm |= fieldFromInstruction(
Insn, 16, 4) << 13;
5182 imm |= fieldFromInstruction(
Insn, 23, 1) << 12;
5183unsignedpred = fieldFromInstruction(
Insn, 28, 4);
5184unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
5206unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5207unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
5208unsigned imm = fieldFromInstruction(
Insn, 0, 12);
5209 imm |= fieldFromInstruction(
Insn, 16, 4) << 13;
5210 imm |= fieldFromInstruction(
Insn, 23, 1) << 12;
5211unsignedpred = fieldFromInstruction(
Insn, 28, 4);
5232unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5233unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
5234unsigned imm = fieldFromInstruction(
Insn, 0, 12);
5235 imm |= fieldFromInstruction(
Insn, 16, 4) << 13;
5236 imm |= fieldFromInstruction(
Insn, 23, 1) << 12;
5237unsignedpred = fieldFromInstruction(
Insn, 28, 4);
5257unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5258unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
5259unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
5260 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
5261unsignedsize = fieldFromInstruction(
Insn, 10, 2);
5269if (fieldFromInstruction(
Insn, 4, 1))
5271 index = fieldFromInstruction(
Insn, 5, 3);
5274if (fieldFromInstruction(
Insn, 5, 1))
5276 index = fieldFromInstruction(
Insn, 6, 2);
5277if (fieldFromInstruction(
Insn, 4, 1))
5281if (fieldFromInstruction(
Insn, 6, 1))
5283 index = fieldFromInstruction(
Insn, 7, 1);
5285switch (fieldFromInstruction(
Insn, 4, 2)) {
5298if (Rm != 0xF) {
// Writeback 5324unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5325unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
5326unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
5327 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
5328unsignedsize = fieldFromInstruction(
Insn, 10, 2);
5336if (fieldFromInstruction(
Insn, 4, 1))
5338 index = fieldFromInstruction(
Insn, 5, 3);
5341if (fieldFromInstruction(
Insn, 5, 1))
5343 index = fieldFromInstruction(
Insn, 6, 2);
5344if (fieldFromInstruction(
Insn, 4, 1))
5348if (fieldFromInstruction(
Insn, 6, 1))
5350 index = fieldFromInstruction(
Insn, 7, 1);
5352switch (fieldFromInstruction(
Insn, 4, 2)) {
5363if (Rm != 0xF) {
// Writeback 5389unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5390unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
5391unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
5392 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
5393unsignedsize = fieldFromInstruction(
Insn, 10, 2);
5402 index = fieldFromInstruction(
Insn, 5, 3);
5403if (fieldFromInstruction(
Insn, 4, 1))
5407 index = fieldFromInstruction(
Insn, 6, 2);
5408if (fieldFromInstruction(
Insn, 4, 1))
5410if (fieldFromInstruction(
Insn, 5, 1))
5414if (fieldFromInstruction(
Insn, 5, 1))
5416 index = fieldFromInstruction(
Insn, 7, 1);
5417if (fieldFromInstruction(
Insn, 4, 1) != 0)
5419if (fieldFromInstruction(
Insn, 6, 1))
5428if (Rm != 0xF) {
// Writeback 5456unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5457unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
5458unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
5459 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
5460unsignedsize = fieldFromInstruction(
Insn, 10, 2);
5469 index = fieldFromInstruction(
Insn, 5, 3);
5470if (fieldFromInstruction(
Insn, 4, 1))
5474 index = fieldFromInstruction(
Insn, 6, 2);
5475if (fieldFromInstruction(
Insn, 4, 1))
5477if (fieldFromInstruction(
Insn, 5, 1))
5481if (fieldFromInstruction(
Insn, 5, 1))
5483 index = fieldFromInstruction(
Insn, 7, 1);
5484if (fieldFromInstruction(
Insn, 4, 1) != 0)
5486if (fieldFromInstruction(
Insn, 6, 1))
5491if (Rm != 0xF) {
// Writeback 5519unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5520unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
5521unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
5522 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
5523unsignedsize = fieldFromInstruction(
Insn, 10, 2);
5532if (fieldFromInstruction(
Insn, 4, 1))
5534 index = fieldFromInstruction(
Insn, 5, 3);
5537if (fieldFromInstruction(
Insn, 4, 1))
5539 index = fieldFromInstruction(
Insn, 6, 2);
5540if (fieldFromInstruction(
Insn, 5, 1))
5544if (fieldFromInstruction(
Insn, 4, 2))
5546 index = fieldFromInstruction(
Insn, 7, 1);
5547if (fieldFromInstruction(
Insn, 6, 1))
5559if (Rm != 0xF) {
// Writeback 5589unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5590unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
5591unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
5592 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
5593unsignedsize = fieldFromInstruction(
Insn, 10, 2);
5602if (fieldFromInstruction(
Insn, 4, 1))
5604 index = fieldFromInstruction(
Insn, 5, 3);
5607if (fieldFromInstruction(
Insn, 4, 1))
5609 index = fieldFromInstruction(
Insn, 6, 2);
5610if (fieldFromInstruction(
Insn, 5, 1))
5614if (fieldFromInstruction(
Insn, 4, 2))
5616 index = fieldFromInstruction(
Insn, 7, 1);
5617if (fieldFromInstruction(
Insn, 6, 1))
5622if (Rm != 0xF) {
// Writeback 5652unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5653unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
5654unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
5655 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
5656unsignedsize = fieldFromInstruction(
Insn, 10, 2);
5665if (fieldFromInstruction(
Insn, 4, 1))
5667 index = fieldFromInstruction(
Insn, 5, 3);
5670if (fieldFromInstruction(
Insn, 4, 1))
5672 index = fieldFromInstruction(
Insn, 6, 2);
5673if (fieldFromInstruction(
Insn, 5, 1))
5677switch (fieldFromInstruction(
Insn, 4, 2)) {
5683 align = 4 << fieldFromInstruction(
Insn, 4, 2);
break;
5686 index = fieldFromInstruction(
Insn, 7, 1);
5687if (fieldFromInstruction(
Insn, 6, 1))
5701if (Rm != 0xF) {
// Writeback 5733unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5734unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
5735unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
5736 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
5737unsignedsize = fieldFromInstruction(
Insn, 10, 2);
5746if (fieldFromInstruction(
Insn, 4, 1))
5748 index = fieldFromInstruction(
Insn, 5, 3);
5751if (fieldFromInstruction(
Insn, 4, 1))
5753 index = fieldFromInstruction(
Insn, 6, 2);
5754if (fieldFromInstruction(
Insn, 5, 1))
5758switch (fieldFromInstruction(
Insn, 4, 2)) {
5764 align = 4 << fieldFromInstruction(
Insn, 4, 2);
break;
5767 index = fieldFromInstruction(
Insn, 7, 1);
5768if (fieldFromInstruction(
Insn, 6, 1))
5773if (Rm != 0xF) {
// Writeback 5804unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
5805unsigned Rt2 = fieldFromInstruction(
Insn, 16, 4);
5806unsigned Rm = fieldFromInstruction(
Insn, 5, 1);
5807unsignedpred = fieldFromInstruction(
Insn, 28, 4);
5808 Rm |= fieldFromInstruction(
Insn, 0, 4) << 1;
5810if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5830unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
5831unsigned Rt2 = fieldFromInstruction(
Insn, 16, 4);
5832unsigned Rm = fieldFromInstruction(
Insn, 5, 1);
5833unsignedpred = fieldFromInstruction(
Insn, 28, 4);
5834 Rm |= fieldFromInstruction(
Insn, 0, 4) << 1;
5836if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5856unsignedpred = fieldFromInstruction(
Insn, 4, 4);
5857unsigned mask = fieldFromInstruction(
Insn, 0, 4);
5867// IT masks are encoded as a sequence of replacement low-order bits 5868// for the condition code. So if the low bit of the starting 5869// condition code is 1, then we have to flip all the bits above the 5870// terminating bit (which is the lowest 1 bit). 5872unsigned LowBit = mask & -mask;
5873unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
5874 mask ^= BitsAboveLowBit;
5887unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
5888unsigned Rt2 = fieldFromInstruction(
Insn, 8, 4);
5889unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5890unsigned addr = fieldFromInstruction(
Insn, 0, 8);
5891unsigned W = fieldFromInstruction(
Insn, 21, 1);
5892unsigned U = fieldFromInstruction(
Insn, 23, 1);
5893unsignedP = fieldFromInstruction(
Insn, 24, 1);
5894bool writeback = (W == 1) | (
P == 0);
5896 addr |= (U << 8) | (Rn << 9);
5898if (writeback && (Rn == Rt || Rn == Rt2))
5924unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
5925unsigned Rt2 = fieldFromInstruction(
Insn, 8, 4);
5926unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5927unsigned addr = fieldFromInstruction(
Insn, 0, 8);
5928unsigned W = fieldFromInstruction(
Insn, 21, 1);
5929unsigned U = fieldFromInstruction(
Insn, 23, 1);
5930unsignedP = fieldFromInstruction(
Insn, 24, 1);
5931bool writeback = (W == 1) | (
P == 0);
5933 addr |= (U << 8) | (Rn << 9);
5935if (writeback && (Rn == Rt || Rn == Rt2))
5956unsigned sign1 = fieldFromInstruction(
Insn, 21, 1);
5957unsigned sign2 = fieldFromInstruction(
Insn, 23, 1);
5959constunsigned Rd = fieldFromInstruction(
Insn, 8, 4);
5963unsigned Val = fieldFromInstruction(
Insn, 0, 8);
5964 Val |= fieldFromInstruction(
Insn, 12, 3) << 8;
5965 Val |= fieldFromInstruction(
Insn, 26, 1) << 11;
5966// If sign, then it is decreasing the address. 5968// Following ARMv7 Architecture Manual, when the offset 5969// is zero, it is decoded as a subw, not as a adr.w 5985// Shift of "asr #32" is not allowed in Thumb2 mode. 5993unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
5994unsigned Rt2 = fieldFromInstruction(
Insn, 0, 4);
5995unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
5996unsignedpred = fieldFromInstruction(
Insn, 28, 4);
6003if (Rt == Rn || Rn == Rt2)
6021 ((
constMCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6022bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
6024unsigned Vd = (fieldFromInstruction(
Insn, 12, 4) << 0);
6025 Vd |= (fieldFromInstruction(
Insn, 22, 1) << 4);
6026unsigned Vm = (fieldFromInstruction(
Insn, 0, 4) << 0);
6027 Vm |= (fieldFromInstruction(
Insn, 5, 1) << 4);
6028unsigned imm = fieldFromInstruction(
Insn, 16, 6);
6029unsigned cmode = fieldFromInstruction(
Insn, 8, 4);
6030unsignedop = fieldFromInstruction(
Insn, 5, 1);
6034// If the top 3 bits of imm are clear, this is a VMOV (immediate) 6080 ((
constMCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6081bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
6083unsigned Vd = (fieldFromInstruction(
Insn, 12, 4) << 0);
6084 Vd |= (fieldFromInstruction(
Insn, 22, 1) << 4);
6085unsigned Vm = (fieldFromInstruction(
Insn, 0, 4) << 0);
6086 Vm |= (fieldFromInstruction(
Insn, 5, 1) << 4);
6087unsigned imm = fieldFromInstruction(
Insn, 16, 6);
6088unsigned cmode = fieldFromInstruction(
Insn, 8, 4);
6089unsignedop = fieldFromInstruction(
Insn, 5, 1);
6093// If the top 3 bits of imm are clear, this is a VMOV (immediate) 6140unsigned Vd = (fieldFromInstruction(
Insn, 12, 4) << 0);
6141 Vd |= (fieldFromInstruction(
Insn, 22, 1) << 4);
6142unsigned Vn = (fieldFromInstruction(
Insn, 16, 4) << 0);
6143 Vn |= (fieldFromInstruction(
Insn, 7, 1) << 4);
6144unsigned Vm = (fieldFromInstruction(
Insn, 0, 4) << 0);
6145 Vm |= (fieldFromInstruction(
Insn, 5, 1) << 4);
6146unsigned q = (fieldFromInstruction(
Insn, 6, 1) << 0);
6147unsigned rotate = (fieldFromInstruction(
Insn, 20, 2) << 0);
6153if (!
Check(S, DestRegDecoder(Inst, Vd,
Address, Decoder)))
6155if (!
Check(S, DestRegDecoder(Inst, Vd,
Address, Decoder)))
6157if (!
Check(S, DestRegDecoder(Inst, Vn,
Address, Decoder)))
6161// The lane index does not have any bits in the encoding, because it can only 6173unsigned Rn = fieldFromInstruction(Val, 16, 4);
6174unsigned Rt = fieldFromInstruction(Val, 12, 4);
6175unsigned Rm = fieldFromInstruction(Val, 0, 4);
6176 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
6177unsignedCond = fieldFromInstruction(Val, 28, 4);
6179if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
6201unsigned CRm = fieldFromInstruction(Val, 0, 4);
6202unsigned opc1 = fieldFromInstruction(Val, 4, 4);
6203unsigned cop = fieldFromInstruction(Val, 8, 4);
6204unsigned Rt = fieldFromInstruction(Val, 12, 4);
6205unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
6207if ((cop & ~0x1) == 0xa)
6213// We have to check if the instruction is MRRC2 6214// or MCRR2 when constructing the operands for 6215// Inst. Reason is because MRRC2 stores to two 6216// registers so it's tablegen desc has two 6217// outputs whereas MCRR doesn't store to any 6218// registers so all of it's operands are listed 6219// as inputs, therefore the operand order for 6220// MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 6221// and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 6246 ((
constMCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6249// Add explicit operand for the destination sysreg, for cases where 6250// we have to model it for code generation purposes. 6252case ARM::VMSR_FPSCR_NZCVQC:
6261unsigned Rt = fieldFromInstruction(Val, 12, 4);
6263if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
6264if (Rt == 13 || Rt == 15)
6271// Add explicit operand for the source sysreg, similarly to above. 6273case ARM::VMRS_FPSCR_NZCVQC:
6281if (featureBits[ARM::ModeThumb]) {
6285unsignedpred = fieldFromInstruction(Val, 28, 4);
6293template <
bool isSigned,
bool isNeg,
bool zeroPermitted,
int size>
6298if (Val == 0 && !zeroPermitted)
6303 DecVal = SignExtend32<size + 1>(Val << 1);
6305 DecVal = (Val << 1);
6318 Val = LocImm + (2 << Val);
6328if (Val >=
ARMCC::AL)
// also exclude the non-condition NV 6341unsigned Imm = fieldFromInstruction(
Insn, 11, 1) |
6342 fieldFromInstruction(
Insn, 1, 10) << 1;
6344case ARM::t2LEUpdate:
6350if (!
Check(S, DecodeBFLabelOperand<false, true, true, 11>(
6355case ARM::MVE_WLSTP_8:
6356case ARM::MVE_WLSTP_16:
6357case ARM::MVE_WLSTP_32:
6358case ARM::MVE_WLSTP_64:
6363 !
Check(S, DecodeBFLabelOperand<false, false, true, 11>(
6368case ARM::MVE_DLSTP_8:
6369case ARM::MVE_DLSTP_16:
6370case ARM::MVE_DLSTP_32:
6371case ARM::MVE_DLSTP_64:
6372unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
6374// Enforce all the rest of the instruction bits in LCTP, which 6375// won't have been reliably checked based on LCTP's own tablegen 6376// record, because we came to this decode by a roundabout route. 6377uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
6378if ((
Insn & ~SBZMask) != CanonicalLCTP)
6380if (
Insn != CanonicalLCTP)
6387 fieldFromInstruction(
Insn, 16, 4),
6412if ((RegNo) + 1 > 11)
6455unsigned regs = fieldFromInstruction(
Insn, 0, 8);
6457// Register list contains only VPR 6458 }
elseif (Inst.
getOpcode() == ARM::VSCCLRMD) {
6459unsigned reglist = regs | (fieldFromInstruction(
Insn, 12, 4) << 8) |
6460 (fieldFromInstruction(
Insn, 22, 1) << 12);
6465unsigned Vd = (fieldFromInstruction(
Insn, 12, 4) << 1) |
6466 fieldFromInstruction(
Insn, 22, 1);
6467// Registers past s31 are permitted and treated as being half of a d 6468// register, though both halves of each d register must be present. 6469unsigned max_reg = Vd + regs;
6470if (max_reg > 64 || (max_reg > 32 && (max_reg & 1)))
6472unsigned max_sreg = std::min(32u, max_reg);
6473unsigned max_dreg = std::min(32u, max_reg / 2);
6474for (
unsigned i = Vd; i < max_sreg; ++i)
6477for (
unsigned i = 16; i < max_dreg; ++i)
6498 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
6499 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
6514 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
6515 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
6534// Parse VPT mask and encode it in the MCInst as an immediate with the same 6535// format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6536// 't' as 0 and finish with a 1. 6538// We always start with a 't'. 6540for (
int i = 3; i >= 0; --i) {
6541// If the bit we are looking at is not the same as last one, invert the 6542// CurBit, if it is the same leave it as is. 6543 CurBit ^= (Val >> i) & 1U;
6545// Encode the CurBit at the right place in the immediate. 6546 Imm |= (CurBit << i);
6548// If we are done, finish the encoding with a 1. 6549if ((Val & ~(~0U << i)) == 0) {
6563// The vpred_r operand type includes an MQPR register field derived 6564// from the encoding. But we don't actually want to add an operand 6565// to the MCInst at this stage, because AddThumbPredicate will do it 6566// later, and will infer the register number from the TIED_TO 6567// constraint. So this is a deliberately empty decoder method that 6568// will inhibit the auto-generated disassembly code from adding an 6576// Similar to above, we want to ensure that no operands are added for the 6577// vpred operands. (This is marked "maybe_unused" for the moment; because 6578// DecoderEmitter currently (wrongly) omits operands with no instruction bits, 6579// the decoder doesn't actually call it yet. That will be addressed in a 6656unsigned DecodedVal = 64 - Val;
6659case ARM::MVE_VCVTf16s16_fix:
6660case ARM::MVE_VCVTs16f16_fix:
6661case ARM::MVE_VCVTf16u16_fix:
6662case ARM::MVE_VCVTu16f16_fix:
6666case ARM::MVE_VCVTf32s32_fix:
6667case ARM::MVE_VCVTs32f32_fix:
6668case ARM::MVE_VCVTf32u32_fix:
6669case ARM::MVE_VCVTu32f32_fix:
6682case ARM::VSTR_P0_off:
6683case ARM::VSTR_P0_pre:
6684case ARM::VSTR_P0_post:
6685case ARM::VLDR_P0_off:
6686case ARM::VLDR_P0_pre:
6687case ARM::VLDR_P0_post:
6689case ARM::VSTR_FPSCR_NZCVQC_off:
6690case ARM::VSTR_FPSCR_NZCVQC_pre:
6691case ARM::VSTR_FPSCR_NZCVQC_post:
6692case ARM::VLDR_FPSCR_NZCVQC_off:
6693case ARM::VLDR_FPSCR_NZCVQC_pre:
6694case ARM::VLDR_FPSCR_NZCVQC_post:
6701template <
bool Writeback>
6706case ARM::VSTR_FPSCR_pre:
6707case ARM::VSTR_FPSCR_NZCVQC_pre:
6708case ARM::VLDR_FPSCR_pre:
6709case ARM::VLDR_FPSCR_NZCVQC_pre:
6710case ARM::VSTR_FPSCR_off:
6711case ARM::VSTR_FPSCR_NZCVQC_off:
6712case ARM::VLDR_FPSCR_off:
6713case ARM::VLDR_FPSCR_NZCVQC_off:
6714case ARM::VSTR_FPSCR_post:
6715case ARM::VSTR_FPSCR_NZCVQC_post:
6716case ARM::VLDR_FPSCR_post:
6717case ARM::VLDR_FPSCR_NZCVQC_post:
6719 ((
constMCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6721if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
6728unsigned Rn = fieldFromInstruction(Val, 16, 4);
6729unsigned addr = fieldFromInstruction(Val, 0, 7) |
6730 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
6751unsigned Qd = fieldFromInstruction(Val, 13, 3);
6752unsigned addr = fieldFromInstruction(Val, 0, 7) |
6753 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
6759if (!
Check(S, AddrDecoder(Inst, addr,
Address, Decoder)))
6770 fieldFromInstruction(Val, 16, 3),
6772 DecodeTAddrModeImm7<shift>);
6780 fieldFromInstruction(Val, 16, 4),
6782 DecodeT2AddrModeImm7<shift,1>);
6790 fieldFromInstruction(Val, 17, 3),
6792 DecodeMveAddrModeQ<shift>);
6795template <
unsigned MinLog,
unsigned MaxLog>
6801if (Val < MinLog || Val > MaxLog)
6808template <
unsigned start>
6823unsigned Rt = fieldFromInstruction(
Insn, 0, 4);
6824unsigned Rt2 = fieldFromInstruction(
Insn, 16, 4);
6825unsigned Qd = ((fieldFromInstruction(
Insn, 22, 1) << 3) |
6826 fieldFromInstruction(
Insn, 13, 3));
6827unsigned index = fieldFromInstruction(
Insn, 4, 1);
6835if (!
Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index,
Address, Decoder)))
6837if (!
Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index,
Address, Decoder)))
6847unsigned Rt = fieldFromInstruction(
Insn, 0, 4);
6848unsigned Rt2 = fieldFromInstruction(
Insn, 16, 4);
6849unsigned Qd = ((fieldFromInstruction(
Insn, 22, 1) << 3) |
6850 fieldFromInstruction(
Insn, 13, 3));
6851unsigned index = fieldFromInstruction(
Insn, 4, 1);
6861if (!
Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index,
Address, Decoder)))
6863if (!
Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index,
Address, Decoder)))
6874unsigned RdaLo = fieldFromInstruction(
Insn, 17, 3) << 1;
6875unsigned RdaHi = fieldFromInstruction(
Insn, 9, 3) << 1;
6876unsigned Rm = fieldFromInstruction(
Insn, 12, 4);
6879// This value of RdaHi (really indicating pc, because RdaHi has to 6880// be an odd-numbered register, so the low bit will be set by the 6881// decode function below) indicates that we must decode as SQRSHR 6882// or UQRSHL, which both have a single Rda register field with all 6884unsigned Rda = fieldFromInstruction(
Insn, 16, 4);
6888case ARM::MVE_SQRSHRL:
6892case ARM::MVE_UQRSHLL:
6899// Rda as output parameter 6903// Rda again as input parameter 6907// Rm, the amount to shift by 6911if (fieldFromInstruction (
Insn, 6, 3) != 4)
6920// Otherwise, we decode as whichever opcode our caller has already 6921// put into Inst. Those all look the same: 6923// RdaLo,RdaHi as output parameters 6929// RdaLo,RdaHi again as input parameters 6935// Rm, the amount to shift by 6939if (Inst.
getOpcode() == ARM::MVE_SQRSHRL ||
6941unsigned Saturate = fieldFromInstruction(
Insn, 7, 1);
6942// Saturate, the bit position for saturation 6953unsigned Qd = ((fieldFromInstruction(
Insn, 22, 1) << 3) |
6954 fieldFromInstruction(
Insn, 13, 3));
6955unsigned Qm = ((fieldFromInstruction(
Insn, 5, 1) << 3) |
6956 fieldFromInstruction(
Insn, 1, 3));
6957unsigned imm6 = fieldFromInstruction(
Insn, 16, 6);
6969template <
bool scalar, OperandDecoder predicate_decoder>
6974unsigned Qn = fieldFromInstruction(
Insn, 17, 3);
6981 fc = fieldFromInstruction(
Insn, 12, 1) << 2 |
6982 fieldFromInstruction(
Insn, 7, 1) |
6983 fieldFromInstruction(
Insn, 5, 1) << 1;
6984unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
6988 fc = fieldFromInstruction(
Insn, 12, 1) << 2 |
6989 fieldFromInstruction(
Insn, 7, 1) |
6990 fieldFromInstruction(
Insn, 0, 1) << 1;
6991unsigned Qm = fieldFromInstruction(
Insn, 5, 1) << 4 |
6992 fieldFromInstruction(
Insn, 1, 3);
6997if (!
Check(S, predicate_decoder(Inst, fc,
Address, Decoder)))
7011unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
7029constunsigned Rd = fieldFromInstruction(
Insn, 8, 4);
7030constunsigned Rn = fieldFromInstruction(
Insn, 16, 4);
7031constunsigned Imm12 = fieldFromInstruction(
Insn, 26, 1) << 11 |
7032 fieldFromInstruction(
Insn, 12, 3) << 8 |
7033 fieldFromInstruction(
Insn, 0, 8);
7034constunsigned TypeT3 = fieldFromInstruction(
Insn, 25, 1);
7035unsigned sign1 = fieldFromInstruction(
Insn, 21, 1);
7036unsigned sign2 = fieldFromInstruction(
Insn, 23, 1);
7037unsigned S = fieldFromInstruction(
Insn, 20, 1);
7041// T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 7048 Inst.
setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
7051 Inst.
setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
7066constunsigned Rn = fieldFromInstruction(
Insn, 16, 4);
7067// Adding Rn, holding memory location to save/load to/from, the only argument 7068// that is being encoded. 7069// '$Rn' in the assembly. 7072// An optional predicate, '$p' in the assembly. 7074// An immediate that represents a floating point registers list. '$regs' in SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
AMDGPU Mark last scratch load
static bool isVectorPredicable(const MCInstrDesc &MCID)
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t GPRPairDecoderTable[]
static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t DPairSpacedDecoderTable[]
static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, const MCDisassembler *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createARMDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode)
static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t DPairDecoderTable[]
static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t QQQQPRDecoderTable[]
static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t CLRMGPRDecoderTable[]
static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler()
static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const MCDisassembler *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t GPRDecoderTable[]
static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t QQPRDecoderTable[]
static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder, unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder)
static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, uint64_t Address, raw_ostream &CS, uint32_t Insn, DecodeStatus Result)
static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t QPRDecoderTable[]
static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t SPRDecoderTable[]
static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Adddress, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t DPRDecoderTable[]
static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
#define LLVM_EXTERNAL_VISIBILITY
static bool isNeg(Value *V)
Returns true if the operation is a negation of V, and it works for both integers and floats.
static bool isSigned(unsigned int Opcode)
amode Optimize addressing mode
static bool isBranch(unsigned Opcode)
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
This class represents an Operation in the Expression.
Container class for subtarget features.
Context object for machine code objects.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
const MCSubtargetInfo & getSubtargetInfo() const
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
virtual uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
SmallVectorImpl< MCOperand >::iterator iterator
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
ArrayRef< MCOperandInfo > operands() const
unsigned short NumOperands
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(MCRegister Reg)
static MCOperand createImm(int64_t Val)
MCRegister getReg() const
Returns the register number.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
Wrapper class representing virtual and physical registers.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Target - Wrapper for Target specific information.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
getAM5Opc - This function encodes the addrmode5 opc field.
unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset)
getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
bool isVpred(OperandType op)
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
@ D16
Only 16 D registers.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Target & getTheThumbBETarget()
static bool isVPTOpcode(int Opc)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...
Target & getTheARMLETarget()
Target & getTheARMBETarget()
Target & getTheThumbLETarget()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
