Movatterモバイル変換

[0]ホーム
URL:

LLVM 20.0.0git
Classes |Namespaces |Macros |Enumerations
AMDHSAKernelDescriptor.h File Reference

AMDHSA kernel descriptor definitions.More...

#include <cstddef>
#include <cstdint>

Go to the source code of this file.

Classes

struct  llvm::amdhsa::kernel_descriptor_t
 

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
namespace  llvm::amdhsa
 

Macros

#define offsetof(TYPE, MEMBER)   ((size_t)&((TYPE*)0)->MEMBER)
 
#define AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH)
 
#define AMDHSA_BITS_GET(SRC, MSK)   ((SRC & MSK) >> MSK ## _SHIFT)
 
#define AMDHSA_BITS_SET(DST, MSK, VAL)
 
#define COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_ ## NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC1_GFX6_GFX8(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX8_ ## NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC1_GFX6_GFX9(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX9_ ## NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC1_GFX6_GFX11(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX11_##NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC1_GFX9_PLUS(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX9_PLUS_ ## NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC1_GFX10_PLUS(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX10_PLUS_ ## NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC1_GFX12_PLUS(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX12_PLUS_##NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_ ## NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC2_GFX6_GFX11(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX6_GFX11_##NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC2_GFX12_PLUS(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX12_PLUS_##NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC3_GFX90A(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX90A_ ## NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC3_GFX10_PLUS(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_PLUS_ ## NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC3_GFX10(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_##NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC3_GFX10_GFX11(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_GFX11_##NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC3_GFX11_PLUS(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX11_PLUS_ ## NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC3_GFX11(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX11_##NAME, SHIFT, WIDTH)
 
#define COMPUTE_PGM_RSRC3_GFX12_PLUS(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX12_PLUS_##NAME, SHIFT, WIDTH)
 
#define KERNEL_CODE_PROPERTY(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(KERNEL_CODE_PROPERTY_ ## NAME, SHIFT, WIDTH)
 
#define KERNARG_PRELOAD_SPEC(NAME, SHIFT, WIDTH)   AMDHSA_BITS_ENUM_ENTRY(KERNARG_PRELOAD_SPEC_##NAME, SHIFT, WIDTH)
 

Enumerations

enum  : uint8_t {llvm::amdhsa::FLOAT_ROUND_MODE_NEAR_EVEN = 0,llvm::amdhsa::FLOAT_ROUND_MODE_PLUS_INFINITY = 1,llvm::amdhsa::FLOAT_ROUND_MODE_MINUS_INFINITY = 2,llvm::amdhsa::FLOAT_ROUND_MODE_ZERO = 3 }
 
enum  : uint8_t {llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_SRC_DST = 0,llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_DST = 1,llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_SRC = 2,llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE = 3 }
 
enum  : uint8_t {llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_X = 0,llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_X_Y = 1,llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2,llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3 }
 
enum  : int32_t {
  llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),
  llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),
  llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11 =(ENABLE_DX10_CLAMP, 21, 1),llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS =(ENABLE_WG_RR_EN, 21, 1),llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11 =(ENABLE_DX10_CLAMP, 21, 1),
  llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS =(ENABLE_WG_RR_EN, 21, 1),llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX8 =(RESERVED0, 26, 1),
  llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS =(FP16_OVFL, 26, 1),llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX9 =(RESERVED2, 29, 3),llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS =(WGP_MODE, 29, 1),
  llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS =(WGP_MODE, 29, 1),llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS =(WGP_MODE, 29, 1)
}
 
enum  : int32_t {
  llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2_GFX6_GFX11 =(ENABLE_TRAP_HANDLER, 6, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2_GFX12_PLUS =(RESERVED1, 6, 1),
  llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),
  llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),
  llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),
  llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1),llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
}
 
enum  : int32_t {llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6),llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6) }
 
enum  : int32_t {
  llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11 =(SHARED_VGPR_COUNT, 0, 4),llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS =(RESERVED0, 0, 4),llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10 =(RESERVED1, 4, 8),llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX11 =(INST_PREF_SIZE, 4, 6),
  llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX11 =(INST_PREF_SIZE, 4, 6),llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX11 =(INST_PREF_SIZE, 4, 6),llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS =(RESERVED0, 0, 4),llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS =(RESERVED2, 12, 1),
  llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11 =(SHARED_VGPR_COUNT, 0, 4),llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS =(RESERVED0, 0, 4),llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS =(RESERVED2, 12, 1),llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10 =(RESERVED1, 4, 8),
  llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX11_PLUS =(IMAGE_OP, 31, 1)
}
 
enum  : int32_t {
  llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),
  llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),
  llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
}
 
enum  : int32_t {llvm::amdhsa::KERNARG_PRELOAD_SPEC =(LENGTH, 0, 7),llvm::amdhsa::KERNARG_PRELOAD_SPEC =(LENGTH, 0, 7) }
 
enum  : uint32_t {
  llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET = 0,llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET = 4,llvm::amdhsa::KERNARG_SIZE_OFFSET = 8,llvm::amdhsa::RESERVED0_OFFSET = 12,
  llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET = 16,llvm::amdhsa::RESERVED1_OFFSET = 24,llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET = 44,llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET = 48,
  llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET = 52,llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET = 56,llvm::amdhsa::KERNARG_PRELOAD_OFFSET = 58,llvm::amdhsa::RESERVED3_OFFSET = 60
}
 

Detailed Description

AMDHSA kernel descriptor definitions.

For more information, visithttps://llvm.org/docs/AMDGPUUsage.html#kernel-descriptor

Warning
Any changes to this file should also be audited for corresponding changes needed in both the assembler and disassembler, namely:
  • AMDGPUAsmPrinter.{cpp,h}
  • AMDGPUTargetStreamer.{cpp,h}
  • AMDGPUDisassembler.{cpp,h}

Definition in fileAMDHSAKernelDescriptor.h.

Macro Definition Documentation

◆ AMDHSA_BITS_ENUM_ENTRY

#define AMDHSA_BITS_ENUM_ENTRY( NAME,
 SHIFT,
 WIDTH 
)
Value:
NAME ## _SHIFT = (SHIFT), \
NAME ## _WIDTH = (WIDTH), \
NAME = (((1 << (WIDTH)) - 1) << (SHIFT))

Definition at line36 of fileAMDHSAKernelDescriptor.h.

◆ AMDHSA_BITS_GET

#define AMDHSA_BITS_GET( SRC,
 MSK 
)   ((SRC & MSK) >> MSK ## _SHIFT)

Definition at line44 of fileAMDHSAKernelDescriptor.h.

◆ AMDHSA_BITS_SET

#define AMDHSA_BITS_SET( DST,
 MSK,
 VAL 
)
Value:
do { \
auto local = VAL; \
DST &= ~MSK; \
DST |= ((local << MSK##_SHIFT) & MSK); \
}while (0)

Definition at line49 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC1

#define COMPUTE_PGM_RSRC1( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_ ## NAME, SHIFT, WIDTH)

Definition at line86 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC1_GFX10_PLUS

#define COMPUTE_PGM_RSRC1_GFX10_PLUS( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX10_PLUS_ ## NAME, SHIFT, WIDTH)

Definition at line101 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC1_GFX12_PLUS

#define COMPUTE_PGM_RSRC1_GFX12_PLUS( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX12_PLUS_##NAME, SHIFT, WIDTH)

Definition at line104 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC1_GFX6_GFX11

#define COMPUTE_PGM_RSRC1_GFX6_GFX11( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX11_##NAME, SHIFT, WIDTH)

Definition at line95 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC1_GFX6_GFX8

#define COMPUTE_PGM_RSRC1_GFX6_GFX8( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX8_ ## NAME, SHIFT, WIDTH)

Definition at line89 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC1_GFX6_GFX9

#define COMPUTE_PGM_RSRC1_GFX6_GFX9( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX9_ ## NAME, SHIFT, WIDTH)

Definition at line92 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC1_GFX9_PLUS

#define COMPUTE_PGM_RSRC1_GFX9_PLUS( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX9_PLUS_ ## NAME, SHIFT, WIDTH)

Definition at line98 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC2

#define COMPUTE_PGM_RSRC2( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_ ## NAME, SHIFT, WIDTH)

Definition at line134 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC2_GFX12_PLUS

#define COMPUTE_PGM_RSRC2_GFX12_PLUS( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX12_PLUS_##NAME, SHIFT, WIDTH)

Definition at line140 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC2_GFX6_GFX11

#define COMPUTE_PGM_RSRC2_GFX6_GFX11( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX6_GFX11_##NAME, SHIFT, WIDTH)

Definition at line137 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC3_GFX10

#define COMPUTE_PGM_RSRC3_GFX10( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_##NAME, SHIFT, WIDTH)

Definition at line184 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC3_GFX10_GFX11

#define COMPUTE_PGM_RSRC3_GFX10_GFX11( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_GFX11_##NAME, SHIFT, WIDTH)

Definition at line187 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC3_GFX10_PLUS

#define COMPUTE_PGM_RSRC3_GFX10_PLUS( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_PLUS_ ## NAME, SHIFT, WIDTH)

Definition at line181 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC3_GFX11

#define COMPUTE_PGM_RSRC3_GFX11( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX11_##NAME, SHIFT, WIDTH)

Definition at line193 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC3_GFX11_PLUS

#define COMPUTE_PGM_RSRC3_GFX11_PLUS( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX11_PLUS_ ## NAME, SHIFT, WIDTH)

Definition at line190 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC3_GFX12_PLUS

#define COMPUTE_PGM_RSRC3_GFX12_PLUS( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX12_PLUS_##NAME, SHIFT, WIDTH)

Definition at line196 of fileAMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC3_GFX90A

#define COMPUTE_PGM_RSRC3_GFX90A( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX90A_ ## NAME, SHIFT, WIDTH)

Definition at line168 of fileAMDHSAKernelDescriptor.h.

◆ KERNARG_PRELOAD_SPEC

#define KERNARG_PRELOAD_SPEC( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(KERNARG_PRELOAD_SPEC_##NAME, SHIFT, WIDTH)

Definition at line234 of fileAMDHSAKernelDescriptor.h.

◆ KERNEL_CODE_PROPERTY

#define KERNEL_CODE_PROPERTY( NAME,
 SHIFT,
 WIDTH 
)   AMDHSA_BITS_ENUM_ENTRY(KERNEL_CODE_PROPERTY_ ## NAME, SHIFT, WIDTH)

Definition at line216 of fileAMDHSAKernelDescriptor.h.

◆ offsetof

#define offsetof( TYPE,
 MEMBER 
)   ((size_t)&((TYPE*)0)->MEMBER)

Definition at line30 of fileAMDHSAKernelDescriptor.h.

Generated on Sun Jul 20 2025 15:02:47 for LLVM by doxygen 1.9.6
[8]ページ先頭
©2009-2025 Movatter.jp