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LLVM 20.0.0git
AArch64Disassembler.cpp
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1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64Disassembler.h"
13#include "AArch64ExternalSymbolizer.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "MCTargetDesc/AArch64MCTargetDesc.h"
16#include "TargetInfo/AArch64TargetInfo.h"
17#include "Utils/AArch64BaseInfo.h"
18#include "llvm/MC/MCDecoderOps.h"
19#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/Compiler.h"
26#include "llvm/Support/Debug.h"
27#include <memory>
28
29using namespacellvm;
30
31#define DEBUG_TYPE "aarch64-disassembler"
32
33// Pull DecodeStatus and its enum values into the global namespace.
34usingDecodeStatus =MCDisassembler::DecodeStatus;
35
36// Forward declare these because the autogenerated code will reference them.
37// Definitions are further down.
38template <unsigned RegClassID,unsigned FirstReg,unsigned NumRegsInClass>
39staticDecodeStatusDecodeSimpleRegisterClass(MCInst &Inst,unsigned RegNo,
40uint64_t Address,
41constMCDisassembler *Decoder);
42staticDecodeStatus
43DecodeGPR64x8ClassRegisterClass(MCInst &Inst,unsigned RegNo,uint64_t Address,
44constMCDisassembler *Decoder);
45template <unsigned Min,unsigned Max>
46staticDecodeStatusDecodeZPRMul2_MinMax(MCInst &Inst,unsigned RegNo,
47uint64_t Address,
48constMCDisassembler *Decoder);
49staticDecodeStatusDecodeZK(MCInst &Inst,unsigned RegNo,uint64_t Address,
50constMCDisassembler *Decoder);
51template <unsigned Min,unsigned Max>
52staticDecodeStatusDecodeZPR2Mul2RegisterClass(MCInst &Inst,unsigned RegNo,
53uint64_t Address,
54constvoid *Decoder);
55staticDecodeStatusDecodeZPR4Mul4RegisterClass(MCInst &Inst,unsigned RegNo,
56uint64_t Address,
57constvoid *Decoder);
58template <unsigned NumBitsForTile>
59staticDecodeStatusDecodeMatrixTile(MCInst &Inst,unsigned RegNo,
60uint64_t Address,
61constMCDisassembler *Decoder);
62staticDecodeStatus
63DecodeMatrixTileListRegisterClass(MCInst &Inst,unsigned RegMask,
64uint64_t Address,
65constMCDisassembler *Decoder);
66staticDecodeStatusDecodePPR2Mul2RegisterClass(MCInst &Inst,unsigned RegNo,
67uint64_t Address,
68constvoid *Decoder);
69
70staticDecodeStatusDecodeFixedPointScaleImm32(MCInst &Inst,unsigned Imm,
71uint64_t Address,
72constMCDisassembler *Decoder);
73staticDecodeStatusDecodeFixedPointScaleImm64(MCInst &Inst,unsigned Imm,
74uint64_t Address,
75constMCDisassembler *Decoder);
76staticDecodeStatusDecodePCRelLabel16(MCInst &Inst,unsigned Imm,
77uint64_t Address,
78constMCDisassembler *Decoder);
79staticDecodeStatusDecodePCRelLabel19(MCInst &Inst,unsigned Imm,
80uint64_t Address,
81constMCDisassembler *Decoder);
82staticDecodeStatusDecodePCRelLabel9(MCInst &Inst,unsigned Imm,
83uint64_t Address,
84constMCDisassembler *Decoder);
85staticDecodeStatusDecodeMemExtend(MCInst &Inst,unsigned Imm,
86uint64_t Address,
87constMCDisassembler *Decoder);
88staticDecodeStatusDecodeMRSSystemRegister(MCInst &Inst,unsigned Imm,
89uint64_t Address,
90constMCDisassembler *Decoder);
91staticDecodeStatusDecodeMSRSystemRegister(MCInst &Inst,unsigned Imm,
92uint64_t Address,
93constMCDisassembler *Decoder);
94staticDecodeStatus
95DecodeThreeAddrSRegInstruction(MCInst &Inst,uint32_t insn,uint64_t Address,
96constMCDisassembler *Decoder);
97staticDecodeStatusDecodeMoveImmInstruction(MCInst &Inst,uint32_t insn,
98uint64_t Address,
99constMCDisassembler *Decoder);
100staticDecodeStatus
101DecodeUnsignedLdStInstruction(MCInst &Inst,uint32_t insn,uint64_t Address,
102constMCDisassembler *Decoder);
103staticDecodeStatusDecodeSignedLdStInstruction(MCInst &Inst,uint32_t insn,
104uint64_t Address,
105constMCDisassembler *Decoder);
106staticDecodeStatus
107DecodeExclusiveLdStInstruction(MCInst &Inst,uint32_t insn,uint64_t Address,
108constMCDisassembler *Decoder);
109staticDecodeStatusDecodePairLdStInstruction(MCInst &Inst,uint32_t insn,
110uint64_t Address,
111constMCDisassembler *Decoder);
112staticDecodeStatusDecodeAuthLoadInstruction(MCInst &Inst,uint32_t insn,
113uint64_t Address,
114constMCDisassembler *Decoder);
115staticDecodeStatusDecodeAddSubERegInstruction(MCInst &Inst,uint32_t insn,
116uint64_t Address,
117constMCDisassembler *Decoder);
118staticDecodeStatusDecodeLogicalImmInstruction(MCInst &Inst,uint32_t insn,
119uint64_t Address,
120constMCDisassembler *Decoder);
121staticDecodeStatusDecodeModImmInstruction(MCInst &Inst,uint32_t insn,
122uint64_t Address,
123constMCDisassembler *Decoder);
124staticDecodeStatusDecodeModImmTiedInstruction(MCInst &Inst,uint32_t insn,
125uint64_t Address,
126constMCDisassembler *Decoder);
127staticDecodeStatusDecodeAdrInstruction(MCInst &Inst,uint32_t insn,
128uint64_t Address,
129constMCDisassembler *Decoder);
130staticDecodeStatusDecodeAddSubImmShift(MCInst &Inst,uint32_t insn,
131uint64_t Address,
132constMCDisassembler *Decoder);
133staticDecodeStatusDecodeUnconditionalBranch(MCInst &Inst,uint32_t insn,
134uint64_t Address,
135constMCDisassembler *Decoder);
136staticDecodeStatus
137DecodeSystemPStateImm0_15Instruction(MCInst &Inst,uint32_t insn,
138uint64_t Address,
139constMCDisassembler *Decoder);
140staticDecodeStatus
141DecodeSystemPStateImm0_1Instruction(MCInst &Inst,uint32_t insn,
142uint64_t Address,
143constMCDisassembler *Decoder);
144staticDecodeStatusDecodeTestAndBranch(MCInst &Inst,uint32_t insn,
145uint64_t Address,
146constMCDisassembler *Decoder);
147
148staticDecodeStatusDecodeFMOVLaneInstruction(MCInst &Inst,unsignedInsn,
149uint64_t Address,
150constMCDisassembler *Decoder);
151staticDecodeStatusDecodeVecShiftR64Imm(MCInst &Inst,unsigned Imm,
152uint64_tAddr,
153constMCDisassembler *Decoder);
154staticDecodeStatusDecodeVecShiftR64ImmNarrow(MCInst &Inst,unsigned Imm,
155uint64_tAddr,
156constMCDisassembler *Decoder);
157staticDecodeStatusDecodeVecShiftR32Imm(MCInst &Inst,unsigned Imm,
158uint64_tAddr,
159constMCDisassembler *Decoder);
160staticDecodeStatusDecodeVecShiftR32ImmNarrow(MCInst &Inst,unsigned Imm,
161uint64_tAddr,
162constMCDisassembler *Decoder);
163staticDecodeStatusDecodeVecShiftR16Imm(MCInst &Inst,unsigned Imm,
164uint64_tAddr,
165constMCDisassembler *Decoder);
166staticDecodeStatusDecodeVecShiftR16ImmNarrow(MCInst &Inst,unsigned Imm,
167uint64_tAddr,
168constMCDisassembler *Decoder);
169staticDecodeStatusDecodeVecShiftR8Imm(MCInst &Inst,unsigned Imm,
170uint64_tAddr,
171constMCDisassembler *Decoder);
172staticDecodeStatusDecodeVecShiftL64Imm(MCInst &Inst,unsigned Imm,
173uint64_tAddr,
174constMCDisassembler *Decoder);
175staticDecodeStatusDecodeVecShiftL32Imm(MCInst &Inst,unsigned Imm,
176uint64_tAddr,
177constMCDisassembler *Decoder);
178staticDecodeStatusDecodeVecShiftL16Imm(MCInst &Inst,unsigned Imm,
179uint64_tAddr,
180constMCDisassembler *Decoder);
181staticDecodeStatusDecodeVecShiftL8Imm(MCInst &Inst,unsigned Imm,
182uint64_tAddr,
183constMCDisassembler *Decoder);
184staticDecodeStatus
185DecodeWSeqPairsClassRegisterClass(MCInst &Inst,unsigned RegNo,uint64_tAddr,
186constMCDisassembler *Decoder);
187staticDecodeStatus
188DecodeXSeqPairsClassRegisterClass(MCInst &Inst,unsigned RegNo,uint64_tAddr,
189constMCDisassembler *Decoder);
190staticDecodeStatusDecodeSyspXzrInstruction(MCInst &Inst,uint32_t insn,
191uint64_tAddr,
192constMCDisassembler *Decoder);
193staticDecodeStatus
194DecodeSVELogicalImmInstruction(MCInst &Inst,uint32_t insn,uint64_t Address,
195constMCDisassembler *Decoder);
196template <int Bits>
197staticDecodeStatusDecodeSImm(MCInst &Inst,uint64_t Imm,uint64_t Address,
198constMCDisassembler *Decoder);
199template <int ElementWidth>
200staticDecodeStatusDecodeImm8OptLsl(MCInst &Inst,unsigned Imm,uint64_tAddr,
201constMCDisassembler *Decoder);
202staticDecodeStatusDecodeSVEIncDecImm(MCInst &Inst,unsigned Imm,
203uint64_tAddr,
204constMCDisassembler *Decoder);
205staticDecodeStatusDecodeSVCROp(MCInst &Inst,unsigned Imm,uint64_t Address,
206constMCDisassembler *Decoder);
207staticDecodeStatusDecodeCPYMemOpInstruction(MCInst &Inst,uint32_t insn,
208uint64_tAddr,
209constMCDisassembler *Decoder);
210staticDecodeStatusDecodeSETMemOpInstruction(MCInst &Inst,uint32_t insn,
211uint64_tAddr,
212constMCDisassembler *Decoder);
213staticDecodeStatusDecodePRFMRegInstruction(MCInst &Inst,uint32_t insn,
214uint64_t Address,
215constMCDisassembler *Decoder);
216
217#include "AArch64GenDisassemblerTables.inc"
218#include "AArch64GenInstrInfo.inc"
219
220#define Success MCDisassembler::Success
221#define Fail MCDisassembler::Fail
222#define SoftFail MCDisassembler::SoftFail
223
224staticMCDisassembler *createAArch64Disassembler(constTarget &T,
225constMCSubtargetInfo &STI,
226MCContext &Ctx) {
227
228returnnewAArch64Disassembler(STI, Ctx,T.createMCInstrInfo());
229}
230
231DecodeStatusAArch64Disassembler::getInstruction(MCInst &MI,uint64_t &Size,
232ArrayRef<uint8_t> Bytes,
233uint64_t Address,
234raw_ostream &CS) const{
235CommentStream = &CS;
236
237Size = 0;
238// We want to read exactly 4 bytes of data.
239if (Bytes.size() < 4)
240returnFail;
241Size = 4;
242
243// Encoded as a small-endian 32-bit word in the stream.
244uint32_tInsn =
245 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
246
247constuint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
248
249for (constauto *Table : Tables) {
250DecodeStatus Result =
251 decodeInstruction(Table,MI,Insn,Address,this,STI);
252
253constMCInstrDesc &Desc = MCII->get(MI.getOpcode());
254
255// For Scalable Matrix Extension (SME) instructions that have an implicit
256// operand for the accumulator (ZA) or implicit immediate zero which isn't
257// encoded, manually insert operand.
258for (unsigned i = 0; i <Desc.getNumOperands(); i++) {
259if (Desc.operands()[i].OperandType ==MCOI::OPERAND_REGISTER) {
260switch (Desc.operands()[i].RegClass) {
261default:
262break;
263case AArch64::MPRRegClassID:
264MI.insert(MI.begin() + i,MCOperand::createReg(AArch64::ZA));
265break;
266case AArch64::MPR8RegClassID:
267MI.insert(MI.begin() + i,MCOperand::createReg(AArch64::ZAB0));
268break;
269case AArch64::ZTRRegClassID:
270MI.insert(MI.begin() + i,MCOperand::createReg(AArch64::ZT0));
271break;
272 }
273 }elseif (Desc.operands()[i].OperandType ==
274AArch64::OPERAND_IMPLICIT_IMM_0) {
275MI.insert(MI.begin() + i,MCOperand::createImm(0));
276 }
277 }
278
279if (MI.getOpcode() == AArch64::LDR_ZA ||
280MI.getOpcode() == AArch64::STR_ZA) {
281// Spill and fill instructions have a single immediate used for both
282// the vector select offset and optional memory offset. Replicate
283// the decoded immediate.
284constMCOperand &Imm4Op =MI.getOperand(2);
285assert(Imm4Op.isImm() &&"Unexpected operand type!");
286MI.addOperand(Imm4Op);
287 }
288
289if (Result !=MCDisassembler::Fail)
290return Result;
291 }
292
293returnMCDisassembler::Fail;
294}
295
296uint64_tAArch64Disassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
297uint64_tAddress) const{
298// AArch64 instructions are always 4 bytes wide, so there's no point
299// in skipping any smaller number of bytes if an instruction can't
300// be decoded.
301return 4;
302}
303
304staticMCSymbolizer *
305createAArch64ExternalSymbolizer(constTriple &TT,LLVMOpInfoCallback GetOpInfo,
306LLVMSymbolLookupCallback SymbolLookUp,
307void *DisInfo,MCContext *Ctx,
308 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
309returnnewAArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
310 SymbolLookUp, DisInfo);
311}
312
313extern"C"LLVM_EXTERNAL_VISIBILITYvoidLLVMInitializeAArch64Disassembler() {
314TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
315createAArch64Disassembler);
316TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
317createAArch64Disassembler);
318TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
319createAArch64ExternalSymbolizer);
320TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
321createAArch64ExternalSymbolizer);
322TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
323createAArch64Disassembler);
324TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
325createAArch64ExternalSymbolizer);
326
327TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
328createAArch64Disassembler);
329TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
330createAArch64ExternalSymbolizer);
331TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
332createAArch64Disassembler);
333TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
334createAArch64ExternalSymbolizer);
335}
336
337template <unsigned RegClassID,unsigned FirstReg,unsigned NumRegsInClass>
338staticDecodeStatusDecodeSimpleRegisterClass(MCInst &Inst,unsigned RegNo,
339uint64_tAddress,
340constMCDisassembler *Decoder) {
341if (RegNo > NumRegsInClass - 1)
342returnFail;
343
344unsignedRegister =
345 AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg);
346 Inst.addOperand(MCOperand::createReg(Register));
347returnSuccess;
348}
349
350staticDecodeStatus
351DecodeGPR64x8ClassRegisterClass(MCInst &Inst,unsigned RegNo,uint64_tAddress,
352constMCDisassembler *Decoder) {
353if (RegNo > 22)
354returnFail;
355if (RegNo & 1)
356returnFail;
357
358unsignedRegister =
359 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
360 RegNo >> 1);
361 Inst.addOperand(MCOperand::createReg(Register));
362returnSuccess;
363}
364
365template <unsigned Min,unsigned Max>
366staticDecodeStatusDecodeZPRMul2_MinMax(MCInst &Inst,unsigned RegNo,
367uint64_tAddress,
368constMCDisassembler *Decoder) {
369unsigned Reg = (RegNo * 2) + Min;
370if (Reg < Min || Reg > Max || (Reg & 1))
371returnFail;
372unsignedRegister =
373 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(Reg);
374 Inst.addOperand(MCOperand::createReg(Register));
375returnSuccess;
376}
377
378template <unsigned Min,unsigned Max>
379staticDecodeStatusDecodeZPR2Mul2RegisterClass(MCInst &Inst,unsigned RegNo,
380uint64_tAddress,
381constvoid *Decoder) {
382unsigned Reg = (RegNo * 2) + Min;
383if (Reg < Min || Reg > Max || (Reg & 1))
384returnFail;
385
386unsignedRegister =
387 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(Reg);
388 Inst.addOperand(MCOperand::createReg(Register));
389returnSuccess;
390}
391
392staticDecodeStatusDecodeZK(MCInst &Inst,unsigned RegNo,uint64_tAddress,
393constMCDisassembler *Decoder) {
394if (RegNo > 7)
395returnFail;
396
397unsignedRegister =
398 AArch64MCRegisterClasses[AArch64::ZPR_KRegClassID].getRegister(RegNo);
399 Inst.addOperand(MCOperand::createReg(Register));
400returnSuccess;
401}
402
403staticDecodeStatusDecodeZPR4Mul4RegisterClass(MCInst &Inst,unsigned RegNo,
404uint64_tAddress,
405constvoid *Decoder) {
406if (RegNo * 4 > 28)
407returnFail;
408unsignedRegister =
409 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
410 Inst.addOperand(MCOperand::createReg(Register));
411returnSuccess;
412}
413
414staticDecodeStatus
415DecodeMatrixTileListRegisterClass(MCInst &Inst,unsigned RegMask,
416uint64_tAddress,
417constMCDisassembler *Decoder) {
418if (RegMask > 0xFF)
419returnFail;
420 Inst.addOperand(MCOperand::createImm(RegMask));
421returnSuccess;
422}
423
424staticconstMCPhysRegMatrixZATileDecoderTable[5][16] = {
425 {AArch64::ZAB0},
426 {AArch64::ZAH0, AArch64::ZAH1},
427 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
428 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
429 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
430 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
431 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
432 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
433 AArch64::ZAQ14, AArch64::ZAQ15}};
434
435template <unsigned NumBitsForTile>
436staticDecodeStatusDecodeMatrixTile(MCInst &Inst,unsigned RegNo,
437uint64_tAddress,
438constMCDisassembler *Decoder) {
439unsigned LastReg = (1 << NumBitsForTile) - 1;
440if (RegNo > LastReg)
441returnFail;
442 Inst.addOperand(
443MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
444returnSuccess;
445}
446
447staticDecodeStatusDecodePPR2Mul2RegisterClass(MCInst &Inst,unsigned RegNo,
448uint64_tAddress,
449constvoid *Decoder) {
450if ((RegNo * 2) > 14)
451returnFail;
452unsignedRegister =
453 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
454 Inst.addOperand(MCOperand::createReg(Register));
455returnSuccess;
456}
457
458staticDecodeStatusDecodeFixedPointScaleImm32(MCInst &Inst,unsigned Imm,
459uint64_tAddr,
460constMCDisassembler *Decoder) {
461// scale{5} is asserted as 1 in tblgen.
462 Imm |= 0x20;
463 Inst.addOperand(MCOperand::createImm(64 - Imm));
464returnSuccess;
465}
466
467staticDecodeStatusDecodeFixedPointScaleImm64(MCInst &Inst,unsigned Imm,
468uint64_tAddr,
469constMCDisassembler *Decoder) {
470 Inst.addOperand(MCOperand::createImm(64 - Imm));
471returnSuccess;
472}
473
474staticDecodeStatusDecodePCRelLabel16(MCInst &Inst,unsigned Imm,
475uint64_tAddr,
476constMCDisassembler *Decoder) {
477// Immediate is encoded as the top 16-bits of an unsigned 18-bit negative
478// PC-relative offset.
479uint64_t ImmVal = Imm;
480if (ImmVal > (1 << 16))
481returnFail;
482 ImmVal = -ImmVal;
483if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal << 2),Addr,
484/*IsBranch=*/false, 0, 0, 4))
485 Inst.addOperand(MCOperand::createImm(ImmVal));
486returnSuccess;
487}
488
489staticDecodeStatusDecodePCRelLabel19(MCInst &Inst,unsigned Imm,
490uint64_tAddr,
491constMCDisassembler *Decoder) {
492 int64_t ImmVal = Imm;
493
494// Sign-extend 19-bit immediate.
495if (ImmVal & (1 << (19 - 1)))
496 ImmVal |= ~((1LL << 19) - 1);
497
498if (!Decoder->tryAddingSymbolicOperand(
499 Inst, ImmVal * 4,Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))
500 Inst.addOperand(MCOperand::createImm(ImmVal));
501returnSuccess;
502}
503
504staticDecodeStatusDecodePCRelLabel9(MCInst &Inst,unsigned Imm,uint64_tAddr,
505constMCDisassembler *Decoder) {
506 int64_t ImmVal = Imm;
507
508// Sign-extend 9-bit immediate.
509if (ImmVal & (1 << (9 - 1)))
510 ImmVal |= ~((1LL << 9) - 1);
511
512if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal * 4),Addr,
513/*IsBranch=*/true, 0, 0, 4))
514 Inst.addOperand(MCOperand::createImm(ImmVal));
515returnSuccess;
516}
517
518staticDecodeStatusDecodeMemExtend(MCInst &Inst,unsigned Imm,
519uint64_tAddress,
520constMCDisassembler *Decoder) {
521 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
522 Inst.addOperand(MCOperand::createImm(Imm & 1));
523returnSuccess;
524}
525
526staticDecodeStatusDecodeMRSSystemRegister(MCInst &Inst,unsigned Imm,
527uint64_tAddress,
528constMCDisassembler *Decoder) {
529 Inst.addOperand(MCOperand::createImm(Imm));
530
531// Every system register in the encoding space is valid with the syntax
532// S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
533returnSuccess;
534}
535
536staticDecodeStatusDecodeMSRSystemRegister(MCInst &Inst,unsigned Imm,
537uint64_tAddress,
538constMCDisassembler *Decoder) {
539 Inst.addOperand(MCOperand::createImm(Imm));
540
541returnSuccess;
542}
543
544staticDecodeStatusDecodeFMOVLaneInstruction(MCInst &Inst,unsignedInsn,
545uint64_tAddress,
546constMCDisassembler *Decoder) {
547// This decoder exists to add the dummy Lane operand to the MCInst, which must
548// be 1 in assembly but has no other real manifestation.
549unsigned Rd = fieldFromInstruction(Insn, 0, 5);
550unsigned Rn = fieldFromInstruction(Insn, 5, 5);
551unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
552
553if (IsToVec) {
554 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(
555 Inst, Rd,Address, Decoder);
556 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
557 Inst, Rn,Address, Decoder);
558 }else {
559 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
560 Inst, Rd,Address, Decoder);
561 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(
562 Inst, Rn,Address, Decoder);
563 }
564
565// Add the lane
566 Inst.addOperand(MCOperand::createImm(1));
567
568returnSuccess;
569}
570
571staticDecodeStatusDecodeVecShiftRImm(MCInst &Inst,unsigned Imm,
572unsignedAdd) {
573 Inst.addOperand(MCOperand::createImm(Add - Imm));
574returnSuccess;
575}
576
577staticDecodeStatusDecodeVecShiftLImm(MCInst &Inst,unsigned Imm,
578unsignedAdd) {
579 Inst.addOperand(MCOperand::createImm((Imm +Add) & (Add - 1)));
580returnSuccess;
581}
582
583staticDecodeStatusDecodeVecShiftR64Imm(MCInst &Inst,unsigned Imm,
584uint64_tAddr,
585constMCDisassembler *Decoder) {
586returnDecodeVecShiftRImm(Inst, Imm, 64);
587}
588
589staticDecodeStatusDecodeVecShiftR64ImmNarrow(MCInst &Inst,unsigned Imm,
590uint64_tAddr,
591constMCDisassembler *Decoder) {
592returnDecodeVecShiftRImm(Inst, Imm | 0x20, 64);
593}
594
595staticDecodeStatusDecodeVecShiftR32Imm(MCInst &Inst,unsigned Imm,
596uint64_tAddr,
597constMCDisassembler *Decoder) {
598returnDecodeVecShiftRImm(Inst, Imm, 32);
599}
600
601staticDecodeStatusDecodeVecShiftR32ImmNarrow(MCInst &Inst,unsigned Imm,
602uint64_tAddr,
603constMCDisassembler *Decoder) {
604returnDecodeVecShiftRImm(Inst, Imm | 0x10, 32);
605}
606
607staticDecodeStatusDecodeVecShiftR16Imm(MCInst &Inst,unsigned Imm,
608uint64_tAddr,
609constMCDisassembler *Decoder) {
610returnDecodeVecShiftRImm(Inst, Imm, 16);
611}
612
613staticDecodeStatusDecodeVecShiftR16ImmNarrow(MCInst &Inst,unsigned Imm,
614uint64_tAddr,
615constMCDisassembler *Decoder) {
616returnDecodeVecShiftRImm(Inst, Imm | 0x8, 16);
617}
618
619staticDecodeStatusDecodeVecShiftR8Imm(MCInst &Inst,unsigned Imm,
620uint64_tAddr,
621constMCDisassembler *Decoder) {
622returnDecodeVecShiftRImm(Inst, Imm, 8);
623}
624
625staticDecodeStatusDecodeVecShiftL64Imm(MCInst &Inst,unsigned Imm,
626uint64_tAddr,
627constMCDisassembler *Decoder) {
628returnDecodeVecShiftLImm(Inst, Imm, 64);
629}
630
631staticDecodeStatusDecodeVecShiftL32Imm(MCInst &Inst,unsigned Imm,
632uint64_tAddr,
633constMCDisassembler *Decoder) {
634returnDecodeVecShiftLImm(Inst, Imm, 32);
635}
636
637staticDecodeStatusDecodeVecShiftL16Imm(MCInst &Inst,unsigned Imm,
638uint64_tAddr,
639constMCDisassembler *Decoder) {
640returnDecodeVecShiftLImm(Inst, Imm, 16);
641}
642
643staticDecodeStatusDecodeVecShiftL8Imm(MCInst &Inst,unsigned Imm,
644uint64_tAddr,
645constMCDisassembler *Decoder) {
646returnDecodeVecShiftLImm(Inst, Imm, 8);
647}
648
649staticDecodeStatus
650DecodeThreeAddrSRegInstruction(MCInst &Inst,uint32_t insn,uint64_tAddr,
651constMCDisassembler *Decoder) {
652unsigned Rd = fieldFromInstruction(insn, 0, 5);
653unsigned Rn = fieldFromInstruction(insn, 5, 5);
654unsigned Rm = fieldFromInstruction(insn, 16, 5);
655unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
656unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
657unsigned shift = (shiftHi << 6) | shiftLo;
658switch (Inst.getOpcode()) {
659default:
660returnFail;
661case AArch64::ADDWrs:
662case AArch64::ADDSWrs:
663case AArch64::SUBWrs:
664case AArch64::SUBSWrs:
665// if shift == '11' then ReservedValue()
666if (shiftHi == 0x3)
667returnFail;
668 [[fallthrough]];
669case AArch64::ANDWrs:
670case AArch64::ANDSWrs:
671case AArch64::BICWrs:
672case AArch64::BICSWrs:
673case AArch64::ORRWrs:
674case AArch64::ORNWrs:
675case AArch64::EORWrs:
676case AArch64::EONWrs: {
677// if sf == '0' and imm6<5> == '1' then ReservedValue()
678if (shiftLo >> 5 == 1)
679returnFail;
680 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd,Addr,
681 Decoder);
682 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn,Addr,
683 Decoder);
684 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm,Addr,
685 Decoder);
686break;
687 }
688case AArch64::ADDXrs:
689case AArch64::ADDSXrs:
690case AArch64::SUBXrs:
691case AArch64::SUBSXrs:
692// if shift == '11' then ReservedValue()
693if (shiftHi == 0x3)
694returnFail;
695 [[fallthrough]];
696case AArch64::ANDXrs:
697case AArch64::ANDSXrs:
698case AArch64::BICXrs:
699case AArch64::BICSXrs:
700case AArch64::ORRXrs:
701case AArch64::ORNXrs:
702case AArch64::EORXrs:
703case AArch64::EONXrs:
704 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd,Addr,
705 Decoder);
706 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn,Addr,
707 Decoder);
708 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm,Addr,
709 Decoder);
710break;
711 }
712
713 Inst.addOperand(MCOperand::createImm(shift));
714returnSuccess;
715}
716
717staticDecodeStatusDecodeMoveImmInstruction(MCInst &Inst,uint32_t insn,
718uint64_tAddr,
719constMCDisassembler *Decoder) {
720unsigned Rd = fieldFromInstruction(insn, 0, 5);
721unsigned imm = fieldFromInstruction(insn, 5, 16);
722unsigned shift = fieldFromInstruction(insn, 21, 2);
723 shift <<= 4;
724switch (Inst.getOpcode()) {
725default:
726returnFail;
727case AArch64::MOVZWi:
728case AArch64::MOVNWi:
729case AArch64::MOVKWi:
730if (shift & (1U << 5))
731returnFail;
732 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd,Addr,
733 Decoder);
734break;
735case AArch64::MOVZXi:
736case AArch64::MOVNXi:
737case AArch64::MOVKXi:
738 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd,Addr,
739 Decoder);
740break;
741 }
742
743if (Inst.getOpcode() == AArch64::MOVKWi ||
744 Inst.getOpcode() == AArch64::MOVKXi)
745 Inst.addOperand(Inst.getOperand(0));
746
747 Inst.addOperand(MCOperand::createImm(imm));
748 Inst.addOperand(MCOperand::createImm(shift));
749returnSuccess;
750}
751
752staticDecodeStatus
753DecodeUnsignedLdStInstruction(MCInst &Inst,uint32_t insn,uint64_tAddr,
754constMCDisassembler *Decoder) {
755unsigned Rt = fieldFromInstruction(insn, 0, 5);
756unsigned Rn = fieldFromInstruction(insn, 5, 5);
757unsigned offset = fieldFromInstruction(insn, 10, 12);
758
759switch (Inst.getOpcode()) {
760default:
761returnFail;
762case AArch64::PRFMui:
763// Rt is an immediate in prefetch.
764 Inst.addOperand(MCOperand::createImm(Rt));
765break;
766case AArch64::STRBBui:
767case AArch64::LDRBBui:
768case AArch64::LDRSBWui:
769case AArch64::STRHHui:
770case AArch64::LDRHHui:
771case AArch64::LDRSHWui:
772case AArch64::STRWui:
773case AArch64::LDRWui:
774 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt,Addr,
775 Decoder);
776break;
777case AArch64::LDRSBXui:
778case AArch64::LDRSHXui:
779case AArch64::LDRSWui:
780case AArch64::STRXui:
781case AArch64::LDRXui:
782 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt,Addr,
783 Decoder);
784break;
785case AArch64::LDRQui:
786case AArch64::STRQui:
787 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt,Addr,
788 Decoder);
789break;
790case AArch64::LDRDui:
791case AArch64::STRDui:
792 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt,Addr,
793 Decoder);
794break;
795case AArch64::LDRSui:
796case AArch64::STRSui:
797 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt,Addr,
798 Decoder);
799break;
800case AArch64::LDRHui:
801case AArch64::STRHui:
802 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt,Addr,
803 Decoder);
804break;
805case AArch64::LDRBui:
806case AArch64::STRBui:
807 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt,Addr,
808 Decoder);
809break;
810 }
811
812 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
813 Decoder);
814if (!Decoder->tryAddingSymbolicOperand(Inst, offset,Addr,Fail, 0, 0, 4))
815 Inst.addOperand(MCOperand::createImm(offset));
816returnSuccess;
817}
818
819staticDecodeStatusDecodeSignedLdStInstruction(MCInst &Inst,uint32_t insn,
820uint64_tAddr,
821constMCDisassembler *Decoder) {
822unsigned Rt = fieldFromInstruction(insn, 0, 5);
823unsigned Rn = fieldFromInstruction(insn, 5, 5);
824 int64_t offset = fieldFromInstruction(insn, 12, 9);
825
826// offset is a 9-bit signed immediate, so sign extend it to
827// fill the unsigned.
828if (offset & (1 << (9 - 1)))
829 offset |= ~((1LL << 9) - 1);
830
831// First operand is always the writeback to the address register, if needed.
832switch (Inst.getOpcode()) {
833default:
834break;
835case AArch64::LDRSBWpre:
836case AArch64::LDRSHWpre:
837case AArch64::STRBBpre:
838case AArch64::LDRBBpre:
839case AArch64::STRHHpre:
840case AArch64::LDRHHpre:
841case AArch64::STRWpre:
842case AArch64::LDRWpre:
843case AArch64::LDRSBWpost:
844case AArch64::LDRSHWpost:
845case AArch64::STRBBpost:
846case AArch64::LDRBBpost:
847case AArch64::STRHHpost:
848case AArch64::LDRHHpost:
849case AArch64::STRWpost:
850case AArch64::LDRWpost:
851case AArch64::LDRSBXpre:
852case AArch64::LDRSHXpre:
853case AArch64::STRXpre:
854case AArch64::LDRSWpre:
855case AArch64::LDRXpre:
856case AArch64::LDRSBXpost:
857case AArch64::LDRSHXpost:
858case AArch64::STRXpost:
859case AArch64::LDRSWpost:
860case AArch64::LDRXpost:
861case AArch64::LDRQpre:
862case AArch64::STRQpre:
863case AArch64::LDRQpost:
864case AArch64::STRQpost:
865case AArch64::LDRDpre:
866case AArch64::STRDpre:
867case AArch64::LDRDpost:
868case AArch64::STRDpost:
869case AArch64::LDRSpre:
870case AArch64::STRSpre:
871case AArch64::LDRSpost:
872case AArch64::STRSpost:
873case AArch64::LDRHpre:
874case AArch64::STRHpre:
875case AArch64::LDRHpost:
876case AArch64::STRHpost:
877case AArch64::LDRBpre:
878case AArch64::STRBpre:
879case AArch64::LDRBpost:
880case AArch64::STRBpost:
881 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
882 Decoder);
883break;
884 }
885
886switch (Inst.getOpcode()) {
887default:
888returnFail;
889case AArch64::PRFUMi:
890// Rt is an immediate in prefetch.
891 Inst.addOperand(MCOperand::createImm(Rt));
892break;
893case AArch64::STURBBi:
894case AArch64::LDURBBi:
895case AArch64::LDURSBWi:
896case AArch64::STURHHi:
897case AArch64::LDURHHi:
898case AArch64::LDURSHWi:
899case AArch64::STURWi:
900case AArch64::LDURWi:
901case AArch64::LDTRSBWi:
902case AArch64::LDTRSHWi:
903case AArch64::STTRWi:
904case AArch64::LDTRWi:
905case AArch64::STTRHi:
906case AArch64::LDTRHi:
907case AArch64::LDTRBi:
908case AArch64::STTRBi:
909case AArch64::LDRSBWpre:
910case AArch64::LDRSHWpre:
911case AArch64::STRBBpre:
912case AArch64::LDRBBpre:
913case AArch64::STRHHpre:
914case AArch64::LDRHHpre:
915case AArch64::STRWpre:
916case AArch64::LDRWpre:
917case AArch64::LDRSBWpost:
918case AArch64::LDRSHWpost:
919case AArch64::STRBBpost:
920case AArch64::LDRBBpost:
921case AArch64::STRHHpost:
922case AArch64::LDRHHpost:
923case AArch64::STRWpost:
924case AArch64::LDRWpost:
925case AArch64::STLURBi:
926case AArch64::STLURHi:
927case AArch64::STLURWi:
928case AArch64::LDAPURBi:
929case AArch64::LDAPURSBWi:
930case AArch64::LDAPURHi:
931case AArch64::LDAPURSHWi:
932case AArch64::LDAPURi:
933 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt,Addr,
934 Decoder);
935break;
936case AArch64::LDURSBXi:
937case AArch64::LDURSHXi:
938case AArch64::LDURSWi:
939case AArch64::STURXi:
940case AArch64::LDURXi:
941case AArch64::LDTRSBXi:
942case AArch64::LDTRSHXi:
943case AArch64::LDTRSWi:
944case AArch64::STTRXi:
945case AArch64::LDTRXi:
946case AArch64::LDRSBXpre:
947case AArch64::LDRSHXpre:
948case AArch64::STRXpre:
949case AArch64::LDRSWpre:
950case AArch64::LDRXpre:
951case AArch64::LDRSBXpost:
952case AArch64::LDRSHXpost:
953case AArch64::STRXpost:
954case AArch64::LDRSWpost:
955case AArch64::LDRXpost:
956case AArch64::LDAPURSWi:
957case AArch64::LDAPURSHXi:
958case AArch64::LDAPURSBXi:
959case AArch64::STLURXi:
960case AArch64::LDAPURXi:
961 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt,Addr,
962 Decoder);
963break;
964case AArch64::LDURQi:
965case AArch64::STURQi:
966case AArch64::LDRQpre:
967case AArch64::STRQpre:
968case AArch64::LDRQpost:
969case AArch64::STRQpost:
970 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt,Addr,
971 Decoder);
972break;
973case AArch64::LDURDi:
974case AArch64::STURDi:
975case AArch64::LDRDpre:
976case AArch64::STRDpre:
977case AArch64::LDRDpost:
978case AArch64::STRDpost:
979 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt,Addr,
980 Decoder);
981break;
982case AArch64::LDURSi:
983case AArch64::STURSi:
984case AArch64::LDRSpre:
985case AArch64::STRSpre:
986case AArch64::LDRSpost:
987case AArch64::STRSpost:
988 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt,Addr,
989 Decoder);
990break;
991case AArch64::LDURHi:
992case AArch64::STURHi:
993case AArch64::LDRHpre:
994case AArch64::STRHpre:
995case AArch64::LDRHpost:
996case AArch64::STRHpost:
997 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt,Addr,
998 Decoder);
999break;
1000case AArch64::LDURBi:
1001case AArch64::STURBi:
1002case AArch64::LDRBpre:
1003case AArch64::STRBpre:
1004case AArch64::LDRBpost:
1005case AArch64::STRBpost:
1006 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt,Addr,
1007 Decoder);
1008break;
1009 }
1010
1011 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
1012 Decoder);
1013 Inst.addOperand(MCOperand::createImm(offset));
1014
1015bool IsLoad = fieldFromInstruction(insn, 22, 1);
1016bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1017bool IsFP = fieldFromInstruction(insn, 26, 1);
1018
1019// Cannot write back to a transfer register (but xzr != sp).
1020if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1021returnSoftFail;
1022
1023returnSuccess;
1024}
1025
1026staticDecodeStatus
1027DecodeExclusiveLdStInstruction(MCInst &Inst,uint32_t insn,uint64_tAddr,
1028constMCDisassembler *Decoder) {
1029unsigned Rt = fieldFromInstruction(insn, 0, 5);
1030unsigned Rn = fieldFromInstruction(insn, 5, 5);
1031unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1032unsigned Rs = fieldFromInstruction(insn, 16, 5);
1033
1034unsigned Opcode = Inst.getOpcode();
1035switch (Opcode) {
1036default:
1037returnFail;
1038case AArch64::STLXRW:
1039case AArch64::STLXRB:
1040case AArch64::STLXRH:
1041case AArch64::STXRW:
1042case AArch64::STXRB:
1043case AArch64::STXRH:
1044 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs,Addr,
1045 Decoder);
1046 [[fallthrough]];
1047case AArch64::LDARW:
1048case AArch64::LDARB:
1049case AArch64::LDARH:
1050case AArch64::LDAXRW:
1051case AArch64::LDAXRB:
1052case AArch64::LDAXRH:
1053case AArch64::LDXRW:
1054case AArch64::LDXRB:
1055case AArch64::LDXRH:
1056case AArch64::STLRW:
1057case AArch64::STLRB:
1058case AArch64::STLRH:
1059case AArch64::STLLRW:
1060case AArch64::STLLRB:
1061case AArch64::STLLRH:
1062case AArch64::LDLARW:
1063case AArch64::LDLARB:
1064case AArch64::LDLARH:
1065 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt,Addr,
1066 Decoder);
1067break;
1068case AArch64::STLXRX:
1069case AArch64::STXRX:
1070 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs,Addr,
1071 Decoder);
1072 [[fallthrough]];
1073case AArch64::LDARX:
1074case AArch64::LDAXRX:
1075case AArch64::LDXRX:
1076case AArch64::STLRX:
1077case AArch64::LDLARX:
1078case AArch64::STLLRX:
1079 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt,Addr,
1080 Decoder);
1081break;
1082case AArch64::STLXPW:
1083case AArch64::STXPW:
1084 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs,Addr,
1085 Decoder);
1086 [[fallthrough]];
1087case AArch64::LDAXPW:
1088case AArch64::LDXPW:
1089 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt,Addr,
1090 Decoder);
1091 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2,Addr,
1092 Decoder);
1093break;
1094case AArch64::STLXPX:
1095case AArch64::STXPX:
1096 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs,Addr,
1097 Decoder);
1098 [[fallthrough]];
1099case AArch64::LDAXPX:
1100case AArch64::LDXPX:
1101 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt,Addr,
1102 Decoder);
1103 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2,Addr,
1104 Decoder);
1105break;
1106 }
1107
1108 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
1109 Decoder);
1110
1111// You shouldn't load to the same register twice in an instruction...
1112if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1113 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1114 Rt == Rt2)
1115returnSoftFail;
1116
1117returnSuccess;
1118}
1119
1120staticDecodeStatusDecodePairLdStInstruction(MCInst &Inst,uint32_t insn,
1121uint64_tAddr,
1122constMCDisassembler *Decoder) {
1123unsigned Rt = fieldFromInstruction(insn, 0, 5);
1124unsigned Rn = fieldFromInstruction(insn, 5, 5);
1125unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1126 int64_t offset = fieldFromInstruction(insn, 15, 7);
1127bool IsLoad = fieldFromInstruction(insn, 22, 1);
1128
1129// offset is a 7-bit signed immediate, so sign extend it to
1130// fill the unsigned.
1131if (offset & (1 << (7 - 1)))
1132 offset |= ~((1LL << 7) - 1);
1133
1134unsigned Opcode = Inst.getOpcode();
1135bool NeedsDisjointWritebackTransfer =false;
1136
1137// First operand is always writeback of base register.
1138switch (Opcode) {
1139default:
1140break;
1141case AArch64::LDPXpost:
1142case AArch64::STPXpost:
1143case AArch64::LDPSWpost:
1144case AArch64::LDPXpre:
1145case AArch64::STPXpre:
1146case AArch64::LDPSWpre:
1147case AArch64::LDPWpost:
1148case AArch64::STPWpost:
1149case AArch64::LDPWpre:
1150case AArch64::STPWpre:
1151case AArch64::LDPQpost:
1152case AArch64::STPQpost:
1153case AArch64::LDPQpre:
1154case AArch64::STPQpre:
1155case AArch64::LDPDpost:
1156case AArch64::STPDpost:
1157case AArch64::LDPDpre:
1158case AArch64::STPDpre:
1159case AArch64::LDPSpost:
1160case AArch64::STPSpost:
1161case AArch64::LDPSpre:
1162case AArch64::STPSpre:
1163case AArch64::STGPpre:
1164case AArch64::STGPpost:
1165case AArch64::LDTPpre:
1166case AArch64::LDTPpost:
1167case AArch64::LDTPQpost:
1168case AArch64::LDTPQpre:
1169case AArch64::STTPpost:
1170case AArch64::STTPpre:
1171case AArch64::STTPQpost:
1172case AArch64::STTPQpre:
1173 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
1174 Decoder);
1175break;
1176 }
1177
1178switch (Opcode) {
1179default:
1180returnFail;
1181case AArch64::LDPXpost:
1182case AArch64::STPXpost:
1183case AArch64::LDPSWpost:
1184case AArch64::LDPXpre:
1185case AArch64::STPXpre:
1186case AArch64::LDPSWpre:
1187case AArch64::STGPpre:
1188case AArch64::STGPpost:
1189case AArch64::LDTPpost:
1190case AArch64::LDTPpre:
1191case AArch64::STTPpost:
1192case AArch64::STTPpre:
1193 NeedsDisjointWritebackTransfer =true;
1194 [[fallthrough]];
1195case AArch64::LDNPXi:
1196case AArch64::STNPXi:
1197case AArch64::LDPXi:
1198case AArch64::STPXi:
1199case AArch64::LDPSWi:
1200case AArch64::STGPi:
1201case AArch64::LDTPi:
1202case AArch64::STTPi:
1203case AArch64::STTNPXi:
1204case AArch64::LDTNPXi:
1205 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt,Addr,
1206 Decoder);
1207 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2,Addr,
1208 Decoder);
1209break;
1210case AArch64::LDPWpost:
1211case AArch64::STPWpost:
1212case AArch64::LDPWpre:
1213case AArch64::STPWpre:
1214 NeedsDisjointWritebackTransfer =true;
1215 [[fallthrough]];
1216case AArch64::LDNPWi:
1217case AArch64::STNPWi:
1218case AArch64::LDPWi:
1219case AArch64::STPWi:
1220 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt,Addr,
1221 Decoder);
1222 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2,Addr,
1223 Decoder);
1224break;
1225case AArch64::LDNPQi:
1226case AArch64::STNPQi:
1227case AArch64::LDPQpost:
1228case AArch64::STPQpost:
1229case AArch64::LDPQi:
1230case AArch64::STPQi:
1231case AArch64::LDPQpre:
1232case AArch64::STPQpre:
1233case AArch64::LDTPQi:
1234case AArch64::LDTPQpost:
1235case AArch64::LDTPQpre:
1236case AArch64::LDTNPQi:
1237case AArch64::STTPQi:
1238case AArch64::STTPQpost:
1239case AArch64::STTPQpre:
1240case AArch64::STTNPQi:
1241 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt,Addr,
1242 Decoder);
1243 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt2,Addr,
1244 Decoder);
1245break;
1246case AArch64::LDNPDi:
1247case AArch64::STNPDi:
1248case AArch64::LDPDpost:
1249case AArch64::STPDpost:
1250case AArch64::LDPDi:
1251case AArch64::STPDi:
1252case AArch64::LDPDpre:
1253case AArch64::STPDpre:
1254 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt,Addr,
1255 Decoder);
1256 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt2,Addr,
1257 Decoder);
1258break;
1259case AArch64::LDNPSi:
1260case AArch64::STNPSi:
1261case AArch64::LDPSpost:
1262case AArch64::STPSpost:
1263case AArch64::LDPSi:
1264case AArch64::STPSi:
1265case AArch64::LDPSpre:
1266case AArch64::STPSpre:
1267 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt,Addr,
1268 Decoder);
1269 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt2,Addr,
1270 Decoder);
1271break;
1272 }
1273
1274 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
1275 Decoder);
1276 Inst.addOperand(MCOperand::createImm(offset));
1277
1278// You shouldn't load to the same register twice in an instruction...
1279if (IsLoad && Rt == Rt2)
1280returnSoftFail;
1281
1282// ... or do any operation that writes-back to a transfer register. But note
1283// that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1284if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1285returnSoftFail;
1286
1287returnSuccess;
1288}
1289
1290staticDecodeStatusDecodeAuthLoadInstruction(MCInst &Inst,uint32_t insn,
1291uint64_tAddr,
1292constMCDisassembler *Decoder) {
1293unsigned Rt = fieldFromInstruction(insn, 0, 5);
1294unsigned Rn = fieldFromInstruction(insn, 5, 5);
1295uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1296 fieldFromInstruction(insn, 12, 9);
1297unsigned writeback = fieldFromInstruction(insn, 11, 1);
1298
1299switch (Inst.getOpcode()) {
1300default:
1301returnFail;
1302case AArch64::LDRAAwriteback:
1303case AArch64::LDRABwriteback:
1304 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1305 Inst, Rn/* writeback register */,Addr, Decoder);
1306break;
1307case AArch64::LDRAAindexed:
1308case AArch64::LDRABindexed:
1309break;
1310 }
1311
1312 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt,Addr,
1313 Decoder);
1314 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
1315 Decoder);
1316 DecodeSImm<10>(Inst, offset,Addr, Decoder);
1317
1318if (writeback && Rt == Rn && Rn != 31) {
1319returnSoftFail;
1320 }
1321
1322returnSuccess;
1323}
1324
1325staticDecodeStatusDecodeAddSubERegInstruction(MCInst &Inst,uint32_t insn,
1326uint64_tAddr,
1327constMCDisassembler *Decoder) {
1328unsigned Rd = fieldFromInstruction(insn, 0, 5);
1329unsigned Rn = fieldFromInstruction(insn, 5, 5);
1330unsigned Rm = fieldFromInstruction(insn, 16, 5);
1331unsigned extend = fieldFromInstruction(insn, 10, 6);
1332
1333unsigned shift = extend & 0x7;
1334if (shift > 4)
1335returnFail;
1336
1337switch (Inst.getOpcode()) {
1338default:
1339returnFail;
1340case AArch64::ADDWrx:
1341case AArch64::SUBWrx:
1342 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rd,Addr,
1343 Decoder);
1344 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn,Addr,
1345 Decoder);
1346 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm,Addr,
1347 Decoder);
1348break;
1349case AArch64::ADDSWrx:
1350case AArch64::SUBSWrx:
1351 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd,Addr,
1352 Decoder);
1353 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn,Addr,
1354 Decoder);
1355 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm,Addr,
1356 Decoder);
1357break;
1358case AArch64::ADDXrx:
1359case AArch64::SUBXrx:
1360 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd,Addr,
1361 Decoder);
1362 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
1363 Decoder);
1364 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm,Addr,
1365 Decoder);
1366break;
1367case AArch64::ADDSXrx:
1368case AArch64::SUBSXrx:
1369 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd,Addr,
1370 Decoder);
1371 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
1372 Decoder);
1373 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm,Addr,
1374 Decoder);
1375break;
1376case AArch64::ADDXrx64:
1377case AArch64::SUBXrx64:
1378 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd,Addr,
1379 Decoder);
1380 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
1381 Decoder);
1382 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm,Addr,
1383 Decoder);
1384break;
1385case AArch64::SUBSXrx64:
1386case AArch64::ADDSXrx64:
1387 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd,Addr,
1388 Decoder);
1389 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
1390 Decoder);
1391 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm,Addr,
1392 Decoder);
1393break;
1394 }
1395
1396 Inst.addOperand(MCOperand::createImm(extend));
1397returnSuccess;
1398}
1399
1400staticDecodeStatusDecodeLogicalImmInstruction(MCInst &Inst,uint32_t insn,
1401uint64_tAddr,
1402constMCDisassembler *Decoder) {
1403unsigned Rd = fieldFromInstruction(insn, 0, 5);
1404unsigned Rn = fieldFromInstruction(insn, 5, 5);
1405unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1406unsigned imm;
1407
1408if (Datasize) {
1409if (Inst.getOpcode() == AArch64::ANDSXri)
1410 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd,Addr,
1411 Decoder);
1412else
1413 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1414 Inst, Rd,Addr, Decoder);
1415 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn,Addr,
1416 Decoder);
1417 imm = fieldFromInstruction(insn, 10, 13);
1418if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1419returnFail;
1420 }else {
1421if (Inst.getOpcode() == AArch64::ANDSWri)
1422 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd,Addr,
1423 Decoder);
1424else
1425 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(
1426 Inst, Rd,Addr, Decoder);
1427 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn,Addr,
1428 Decoder);
1429 imm = fieldFromInstruction(insn, 10, 12);
1430if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1431returnFail;
1432 }
1433 Inst.addOperand(MCOperand::createImm(imm));
1434returnSuccess;
1435}
1436
1437staticDecodeStatusDecodeModImmInstruction(MCInst &Inst,uint32_t insn,
1438uint64_tAddr,
1439constMCDisassembler *Decoder) {
1440unsigned Rd = fieldFromInstruction(insn, 0, 5);
1441unsigned cmode = fieldFromInstruction(insn, 12, 4);
1442unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1443 imm |= fieldFromInstruction(insn, 5, 5);
1444
1445if (Inst.getOpcode() == AArch64::MOVID)
1446 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rd,Addr,
1447 Decoder);
1448else
1449 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd,Addr,
1450 Decoder);
1451
1452 Inst.addOperand(MCOperand::createImm(imm));
1453
1454switch (Inst.getOpcode()) {
1455default:
1456break;
1457case AArch64::MOVIv4i16:
1458case AArch64::MOVIv8i16:
1459case AArch64::MVNIv4i16:
1460case AArch64::MVNIv8i16:
1461case AArch64::MOVIv2i32:
1462case AArch64::MOVIv4i32:
1463case AArch64::MVNIv2i32:
1464case AArch64::MVNIv4i32:
1465 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1466break;
1467case AArch64::MOVIv2s_msl:
1468case AArch64::MOVIv4s_msl:
1469case AArch64::MVNIv2s_msl:
1470case AArch64::MVNIv4s_msl:
1471 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1472break;
1473 }
1474
1475returnSuccess;
1476}
1477
1478staticDecodeStatusDecodeModImmTiedInstruction(MCInst &Inst,uint32_t insn,
1479uint64_tAddr,
1480constMCDisassembler *Decoder) {
1481unsigned Rd = fieldFromInstruction(insn, 0, 5);
1482unsigned cmode = fieldFromInstruction(insn, 12, 4);
1483unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1484 imm |= fieldFromInstruction(insn, 5, 5);
1485
1486// Tied operands added twice.
1487 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd,Addr,
1488 Decoder);
1489 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd,Addr,
1490 Decoder);
1491
1492 Inst.addOperand(MCOperand::createImm(imm));
1493 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1494
1495returnSuccess;
1496}
1497
1498staticDecodeStatusDecodeAdrInstruction(MCInst &Inst,uint32_t insn,
1499uint64_tAddr,
1500constMCDisassembler *Decoder) {
1501unsigned Rd = fieldFromInstruction(insn, 0, 5);
1502 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1503 imm |= fieldFromInstruction(insn, 29, 2);
1504
1505// Sign-extend the 21-bit immediate.
1506if (imm & (1 << (21 - 1)))
1507 imm |= ~((1LL << 21) - 1);
1508
1509 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd,Addr,
1510 Decoder);
1511if (!Decoder->tryAddingSymbolicOperand(Inst, imm,Addr,Fail, 0, 0, 4))
1512 Inst.addOperand(MCOperand::createImm(imm));
1513
1514returnSuccess;
1515}
1516
1517staticDecodeStatusDecodeAddSubImmShift(MCInst &Inst,uint32_t insn,
1518uint64_tAddr,
1519constMCDisassembler *Decoder) {
1520unsigned Rd = fieldFromInstruction(insn, 0, 5);
1521unsigned Rn = fieldFromInstruction(insn, 5, 5);
1522unsigned Imm = fieldFromInstruction(insn, 10, 14);
1523unsigned S = fieldFromInstruction(insn, 29, 1);
1524unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1525
1526unsigned ShifterVal = (Imm >> 12) & 3;
1527unsigned ImmVal = Imm & 0xFFF;
1528
1529if (ShifterVal != 0 && ShifterVal != 1)
1530returnFail;
1531
1532if (Datasize) {
1533if (Rd == 31 && !S)
1534 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1535 Inst, Rd,Addr, Decoder);
1536else
1537 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd,Addr,
1538 Decoder);
1539 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
1540 Decoder);
1541 }else {
1542if (Rd == 31 && !S)
1543 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(
1544 Inst, Rd,Addr, Decoder);
1545else
1546 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd,Addr,
1547 Decoder);
1548 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn,Addr,
1549 Decoder);
1550 }
1551
1552if (!Decoder->tryAddingSymbolicOperand(Inst, Imm,Addr,Fail, 0, 0, 4))
1553 Inst.addOperand(MCOperand::createImm(ImmVal));
1554 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1555returnSuccess;
1556}
1557
1558staticDecodeStatusDecodeUnconditionalBranch(MCInst &Inst,uint32_t insn,
1559uint64_tAddr,
1560constMCDisassembler *Decoder) {
1561 int64_t imm = fieldFromInstruction(insn, 0, 26);
1562
1563// Sign-extend the 26-bit immediate.
1564if (imm & (1 << (26 - 1)))
1565 imm |= ~((1LL << 26) - 1);
1566
1567if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4,Addr,true, 0, 0, 4))
1568 Inst.addOperand(MCOperand::createImm(imm));
1569
1570returnSuccess;
1571}
1572
1573staticboolisInvalidPState(uint64_t Op1,uint64_t Op2) {
1574return Op1 == 0b000 && (Op2 == 0b000 ||// CFINV
1575 Op2 == 0b001 ||// XAFlag
1576 Op2 == 0b010);// AXFlag
1577}
1578
1579staticDecodeStatus
1580DecodeSystemPStateImm0_15Instruction(MCInst &Inst,uint32_t insn,uint64_tAddr,
1581constMCDisassembler *Decoder) {
1582uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1583uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1584uint64_t imm = fieldFromInstruction(insn, 8, 4);
1585uint64_t pstate_field = (op1 << 3) | op2;
1586
1587if (isInvalidPState(op1, op2))
1588returnFail;
1589
1590 Inst.addOperand(MCOperand::createImm(pstate_field));
1591 Inst.addOperand(MCOperand::createImm(imm));
1592
1593auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1594if (PState &&
1595 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1596returnSuccess;
1597returnFail;
1598}
1599
1600staticDecodeStatus
1601DecodeSystemPStateImm0_1Instruction(MCInst &Inst,uint32_t insn,uint64_tAddr,
1602constMCDisassembler *Decoder) {
1603uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1604uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1605uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1606uint64_t imm = fieldFromInstruction(insn, 8, 1);
1607uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1608
1609if (isInvalidPState(op1, op2))
1610returnFail;
1611
1612 Inst.addOperand(MCOperand::createImm(pstate_field));
1613 Inst.addOperand(MCOperand::createImm(imm));
1614
1615auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1616if (PState &&
1617 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1618returnSuccess;
1619returnFail;
1620}
1621
1622staticDecodeStatusDecodeTestAndBranch(MCInst &Inst,uint32_t insn,
1623uint64_tAddr,
1624constMCDisassembler *Decoder) {
1625uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1626uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1627 bit |= fieldFromInstruction(insn, 19, 5);
1628 int64_t dst = fieldFromInstruction(insn, 5, 14);
1629
1630// Sign-extend 14-bit immediate.
1631if (dst & (1 << (14 - 1)))
1632 dst |= ~((1LL << 14) - 1);
1633
1634if (fieldFromInstruction(insn, 31, 1) == 0)
1635 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt,Addr,
1636 Decoder);
1637else
1638 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt,Addr,
1639 Decoder);
1640 Inst.addOperand(MCOperand::createImm(bit));
1641if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4,Addr,true, 0, 0, 4))
1642 Inst.addOperand(MCOperand::createImm(dst));
1643
1644returnSuccess;
1645}
1646
1647staticDecodeStatus
1648DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,unsigned RegClassID,
1649unsigned RegNo,uint64_tAddr,
1650constMCDisassembler *Decoder) {
1651// Register number must be even (see CASP instruction)
1652if (RegNo & 0x1)
1653returnFail;
1654
1655unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1656 Inst.addOperand(MCOperand::createReg(Reg));
1657returnSuccess;
1658}
1659
1660staticDecodeStatus
1661DecodeWSeqPairsClassRegisterClass(MCInst &Inst,unsigned RegNo,uint64_tAddr,
1662constMCDisassembler *Decoder) {
1663returnDecodeGPRSeqPairsClassRegisterClass(
1664 Inst, AArch64::WSeqPairsClassRegClassID, RegNo,Addr, Decoder);
1665}
1666
1667staticDecodeStatus
1668DecodeXSeqPairsClassRegisterClass(MCInst &Inst,unsigned RegNo,uint64_tAddr,
1669constMCDisassembler *Decoder) {
1670returnDecodeGPRSeqPairsClassRegisterClass(
1671 Inst, AArch64::XSeqPairsClassRegClassID, RegNo,Addr, Decoder);
1672}
1673
1674staticDecodeStatusDecodeSyspXzrInstruction(MCInst &Inst,uint32_t insn,
1675uint64_tAddr,
1676constMCDisassembler *Decoder) {
1677unsigned op1 = fieldFromInstruction(insn, 16, 3);
1678unsigned CRn = fieldFromInstruction(insn, 12, 4);
1679unsigned CRm = fieldFromInstruction(insn, 8, 4);
1680unsigned op2 = fieldFromInstruction(insn, 5, 3);
1681unsigned Rt = fieldFromInstruction(insn, 0, 5);
1682if (Rt != 0b11111)
1683returnFail;
1684
1685 Inst.addOperand(MCOperand::createImm(op1));
1686 Inst.addOperand(MCOperand::createImm(CRn));
1687 Inst.addOperand(MCOperand::createImm(CRm));
1688 Inst.addOperand(MCOperand::createImm(op2));
1689 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt,Addr,
1690 Decoder);
1691
1692returnSuccess;
1693}
1694
1695staticDecodeStatus
1696DecodeSVELogicalImmInstruction(MCInst &Inst,uint32_t insn,uint64_tAddr,
1697constMCDisassembler *Decoder) {
1698unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1699unsigned imm = fieldFromInstruction(insn, 5, 13);
1700if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1701returnFail;
1702
1703// The same (tied) operand is added twice to the instruction.
1704 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn,Addr,
1705 Decoder);
1706if (Inst.getOpcode() != AArch64::DUPM_ZI)
1707 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn,Addr,
1708 Decoder);
1709 Inst.addOperand(MCOperand::createImm(imm));
1710returnSuccess;
1711}
1712
1713template <int Bits>
1714staticDecodeStatusDecodeSImm(MCInst &Inst,uint64_t Imm,uint64_tAddress,
1715constMCDisassembler *Decoder) {
1716if (Imm & ~((1LL << Bits) - 1))
1717returnFail;
1718
1719// Imm is a signed immediate, so sign extend it.
1720if (Imm & (1 << (Bits - 1)))
1721 Imm |= ~((1LL << Bits) - 1);
1722
1723 Inst.addOperand(MCOperand::createImm(Imm));
1724returnSuccess;
1725}
1726
1727// Decode 8-bit signed/unsigned immediate for a given element width.
1728template <int ElementWidth>
1729staticDecodeStatusDecodeImm8OptLsl(MCInst &Inst,unsigned Imm,uint64_tAddr,
1730constMCDisassembler *Decoder) {
1731unsigned Val = (uint8_t)Imm;
1732unsigned Shift = (Imm & 0x100) ? 8 : 0;
1733if (ElementWidth == 8 && Shift)
1734returnFail;
1735 Inst.addOperand(MCOperand::createImm(Val));
1736 Inst.addOperand(MCOperand::createImm(Shift));
1737returnSuccess;
1738}
1739
1740// Decode uimm4 ranged from 1-16.
1741staticDecodeStatusDecodeSVEIncDecImm(MCInst &Inst,unsigned Imm,
1742uint64_tAddr,
1743constMCDisassembler *Decoder) {
1744 Inst.addOperand(MCOperand::createImm(Imm + 1));
1745returnSuccess;
1746}
1747
1748staticDecodeStatusDecodeSVCROp(MCInst &Inst,unsigned Imm,uint64_tAddress,
1749constMCDisassembler *Decoder) {
1750if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
1751 Inst.addOperand(MCOperand::createImm(Imm));
1752returnSuccess;
1753 }
1754returnFail;
1755}
1756
1757staticDecodeStatusDecodeCPYMemOpInstruction(MCInst &Inst,uint32_t insn,
1758uint64_tAddr,
1759constMCDisassembler *Decoder) {
1760unsigned Rd = fieldFromInstruction(insn, 0, 5);
1761unsigned Rs = fieldFromInstruction(insn, 16, 5);
1762unsigned Rn = fieldFromInstruction(insn, 5, 5);
1763
1764// None of the registers may alias: if they do, then the instruction is not
1765// merely unpredictable but actually entirely unallocated.
1766if (Rd == Rs || Rs == Rn || Rd == Rn)
1767returnMCDisassembler::Fail;
1768
1769// All three register operands are written back, so they all appear
1770// twice in the operand list, once as outputs and once as inputs.
1771if (!DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1772 Inst, Rd,Addr, Decoder) ||
1773 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1774 Inst, Rs,Addr, Decoder) ||
1775 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1776 Inst, Rn,Addr, Decoder) ||
1777 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1778 Inst, Rd,Addr, Decoder) ||
1779 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1780 Inst, Rs,Addr, Decoder) ||
1781 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1782 Inst, Rn,Addr, Decoder))
1783returnMCDisassembler::Fail;
1784
1785returnMCDisassembler::Success;
1786}
1787
1788staticDecodeStatusDecodeSETMemOpInstruction(MCInst &Inst,uint32_t insn,
1789uint64_tAddr,
1790constMCDisassembler *Decoder) {
1791unsigned Rd = fieldFromInstruction(insn, 0, 5);
1792unsigned Rm = fieldFromInstruction(insn, 16, 5);
1793unsigned Rn = fieldFromInstruction(insn, 5, 5);
1794
1795// None of the registers may alias: if they do, then the instruction is not
1796// merely unpredictable but actually entirely unallocated.
1797if (Rd == Rm || Rm == Rn || Rd == Rn)
1798returnMCDisassembler::Fail;
1799
1800// Rd and Rn (not Rm) register operands are written back, so they appear
1801// twice in the operand list, once as outputs and once as inputs.
1802if (!DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1803 Inst, Rd,Addr, Decoder) ||
1804 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1805 Inst, Rn,Addr, Decoder) ||
1806 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1807 Inst, Rd,Addr, Decoder) ||
1808 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1809 Inst, Rn,Addr, Decoder) ||
1810 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1811 Inst, Rm,Addr, Decoder))
1812returnMCDisassembler::Fail;
1813
1814returnMCDisassembler::Success;
1815}
1816
1817staticDecodeStatusDecodePRFMRegInstruction(MCInst &Inst,uint32_t insn,
1818uint64_tAddr,
1819constMCDisassembler *Decoder) {
1820// PRFM with Rt = '11xxx' should be decoded as RPRFM.
1821// Fail to decode and defer to fallback decoder table to decode RPRFM.
1822unsigned Mask = 0x18;
1823uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1824if ((Rt & Mask) == Mask)
1825returnFail;
1826
1827uint64_t Rn = fieldFromInstruction(insn, 5, 5);
1828uint64_t Shift = fieldFromInstruction(insn, 12, 1);
1829uint64_t Extend = fieldFromInstruction(insn, 15, 1);
1830uint64_t Rm = fieldFromInstruction(insn, 16, 5);
1831
1832 Inst.addOperand(MCOperand::createImm(Rt));
1833 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn,Addr,
1834 Decoder);
1835
1836switch (Inst.getOpcode()) {
1837default:
1838returnFail;
1839case AArch64::PRFMroW:
1840 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm,Addr,
1841 Decoder);
1842break;
1843case AArch64::PRFMroX:
1844 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm,Addr,
1845 Decoder);
1846break;
1847 }
1848
1849DecodeMemExtend(Inst, (Extend << 1) | Shift,Addr, Decoder);
1850
1851returnSuccess;
1852}
AArch64AddressingModes.h
AArch64BaseInfo.h
DecodeUnconditionalBranch
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1558
DecodeZPRMul2_MinMax
static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:366
DecodeVecShiftL64Imm
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:625
DecodeVecShiftL32Imm
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:631
createAArch64ExternalSymbolizer
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition:AArch64Disassembler.cpp:305
DecodeCPYMemOpInstruction
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1757
DecodeVecShiftR8Imm
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:619
DecodeFixedPointScaleImm64
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:467
DecodeAddSubERegInstruction
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1325
DecodeModImmInstruction
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1437
DecodeLogicalImmInstruction
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1400
DecodeMoveImmInstruction
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:717
DecodeSystemPStateImm0_1Instruction
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1601
createAArch64Disassembler
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition:AArch64Disassembler.cpp:224
DecodeGPR64x8ClassRegisterClass
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:351
DecodeUnsignedLdStInstruction
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:753
MatrixZATileDecoderTable
static const MCPhysReg MatrixZATileDecoderTable[5][16]
Definition:AArch64Disassembler.cpp:424
DecodeXSeqPairsClassRegisterClass
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1668
DecodeAuthLoadInstruction
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1290
DecodeVecShiftL16Imm
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:637
DecodePairLdStInstruction
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1120
SoftFail
#define SoftFail
Definition:AArch64Disassembler.cpp:222
DecodeMatrixTile
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:436
DecodeSImm
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1714
DecodeVecShiftR32ImmNarrow
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:601
DecodeZK
static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:392
DecodePPR2Mul2RegisterClass
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition:AArch64Disassembler.cpp:447
DecodeSystemPStateImm0_15Instruction
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1580
DecodeVecShiftL8Imm
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:643
DecodePCRelLabel16
static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:474
DecodeSVEIncDecImm
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1741
DecodeFixedPointScaleImm32
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:458
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1622
DecodeSVELogicalImmInstruction
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1696
DecodeVecShiftRImm
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition:AArch64Disassembler.cpp:571
LLVMInitializeAArch64Disassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
Definition:AArch64Disassembler.cpp:313
DecodeVecShiftR64Imm
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:583
DecodeVecShiftLImm
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition:AArch64Disassembler.cpp:577
DecodeVecShiftR16ImmNarrow
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:613
DecodePCRelLabel9
static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:504
DecodeSVCROp
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1748
DecodeWSeqPairsClassRegisterClass
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1661
DecodeVecShiftR64ImmNarrow
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:589
DecodeZPR4Mul4RegisterClass
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition:AArch64Disassembler.cpp:403
DecodeAddSubImmShift
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1517
Fail
#define Fail
Definition:AArch64Disassembler.cpp:221
DecodeMSRSystemRegister
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:536
DecodeZPR2Mul2RegisterClass
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition:AArch64Disassembler.cpp:379
Success
#define Success
Definition:AArch64Disassembler.cpp:220
DecodeSETMemOpInstruction
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1788
DecodePCRelLabel19
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:489
DecodeThreeAddrSRegInstruction
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:650
DecodeMemExtend
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:518
DecodeSignedLdStInstruction
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:819
DecodeExclusiveLdStInstruction
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1027
DecodeSyspXzrInstruction
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1674
DecodeFMOVLaneInstruction
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:544
isInvalidPState
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
Definition:AArch64Disassembler.cpp:1573
DecodeSimpleRegisterClass
static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:338
DecodeMatrixTileListRegisterClass
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:415
DecodeAdrInstruction
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1498
DecodePRFMRegInstruction
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1817
DecodeVecShiftR16Imm
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:607
DecodeVecShiftR32Imm
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:595
DecodeImm8OptLsl
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1729
DecodeGPRSeqPairsClassRegisterClass
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1648
DecodeMRSSystemRegister
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:526
DecodeModImmTiedInstruction
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition:AArch64Disassembler.cpp:1478
AArch64Disassembler.h
AArch64ExternalSymbolizer.h
AArch64MCTargetDesc.h
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition:AArch64MIPeepholeOpt.cpp:167
AArch64TargetInfo.h
Compiler.h
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition:Compiler.h:128
Debug.h
Addr
uint64_t Addr
Definition:ELFObjHandler.cpp:79
Size
uint64_t Size
Definition:ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition:IRTranslator.cpp:112
MCDecoderOps.h
MCInst.h
MCInstrDesc.h
MCRegisterInfo.h
MCRelocationInfo.h
MCSubtargetInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
TargetRegistry.h
T
llvm::AArch64Disassembler
Definition:AArch64Disassembler.h:20
llvm::AArch64Disassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition:AArch64Disassembler.cpp:231
llvm::AArch64Disassembler::suggestBytesToSkip
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
Definition:AArch64Disassembler.cpp:296
llvm::AArch64ExternalSymbolizer
Definition:AArch64ExternalSymbolizer.h:20
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition:ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition:ArrayRef.h:168
llvm::MCContext
Context object for machine code objects.
Definition:MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition:MCDisassembler.h:84
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
Definition:MCDisassembler.cpp:28
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition:MCDisassembler.h:217
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition:MCDisassembler.h:200
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition:MCDisassembler.h:224
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition:MCDisassembler.h:108
llvm::MCDisassembler::Fail
@ Fail
Definition:MCDisassembler.h:109
llvm::MCDisassembler::Success
@ Success
Definition:MCDisassembler.h:111
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition:MCInst.h:185
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition:MCInst.h:199
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition:MCInst.h:211
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition:MCInst.h:207
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition:MCInstrDesc.h:198
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition:MCInst.h:37
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition:MCInst.h:135
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition:MCInst.h:142
llvm::MCOperand::isImm
bool isImm() const
Definition:MCInst.h:63
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition:MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition:MCSubtargetInfo.h:114
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition:MCSymbolizer.h:39
llvm::Register
Wrapper class representing virtual and physical registers.
Definition:Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition:TargetRegistry.h:144
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition:Triple.h:44
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition:raw_ostream.h:52
uint16_t
uint32_t
uint64_t
uint8_t
LLVMSymbolLookupCallback
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition:DisassemblerTypes.h:118
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition:DisassemblerTypes.h:48
llvm::AArch64_AM::isValidDecodeLogicalImmediate
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
Definition:AArch64AddressingModes.h:321
llvm::AArch64::OPERAND_IMPLICIT_IMM_0
@ OPERAND_IMPLICIT_IMM_0
Definition:AArch64MCTargetDesc.h:72
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition:MCInstrDesc.h:61
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:AddressRanges.h:18
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition:AArch64TargetInfo.cpp:17
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition:AArch64TargetInfo.cpp:13
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition:AArch64TargetInfo.cpp:21
llvm::CaptureComponents::Address
@ Address
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition:AArch64TargetInfo.cpp:29
llvm::RecurKind::Add
@ Add
Sum of integers.
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition:AArch64TargetInfo.cpp:25
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition:DWARFExpression.h:66
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition:TargetRegistry.h:964
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition:TargetRegistry.h:878
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