1//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7//===----------------------------------------------------------------------===// 9// This file contains small standalone helper functions and enum definitions for 10// the AArch64 target useful for the compiler back-end and the MC libraries. 11// As such, it deliberately does not include references to LLVM core 12// code gen types, passes, etc.. 14//===----------------------------------------------------------------------===// 16#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 17#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 19// FIXME: Is it easiest to fix this layering violation by moving the .inc 20// #includes from AArch64MCTargetDesc.h to here? 32case AArch64::X0:
return AArch64::W0;
33case AArch64::X1:
return AArch64::W1;
34case AArch64::X2:
return AArch64::W2;
35case AArch64::X3:
return AArch64::W3;
36case AArch64::X4:
return AArch64::W4;
37case AArch64::X5:
return AArch64::W5;
38case AArch64::X6:
return AArch64::W6;
39case AArch64::X7:
return AArch64::W7;
40case AArch64::X8:
return AArch64::W8;
41case AArch64::X9:
return AArch64::W9;
42case AArch64::X10:
return AArch64::W10;
43case AArch64::X11:
return AArch64::W11;
44case AArch64::X12:
return AArch64::W12;
45case AArch64::X13:
return AArch64::W13;
46case AArch64::X14:
return AArch64::W14;
47case AArch64::X15:
return AArch64::W15;
48case AArch64::X16:
return AArch64::W16;
49case AArch64::X17:
return AArch64::W17;
50case AArch64::X18:
return AArch64::W18;
51case AArch64::X19:
return AArch64::W19;
52case AArch64::X20:
return AArch64::W20;
53case AArch64::X21:
return AArch64::W21;
54case AArch64::X22:
return AArch64::W22;
55case AArch64::X23:
return AArch64::W23;
56case AArch64::X24:
return AArch64::W24;
57case AArch64::X25:
return AArch64::W25;
58case AArch64::X26:
return AArch64::W26;
59case AArch64::X27:
return AArch64::W27;
60case AArch64::X28:
return AArch64::W28;
61case AArch64::FP:
return AArch64::W29;
62case AArch64::LR:
return AArch64::W30;
63case AArch64::SP:
return AArch64::WSP;
64case AArch64::XZR:
return AArch64::WZR;
66// For anything else, return it unchanged. 72case AArch64::W0:
return AArch64::X0;
73case AArch64::W1:
return AArch64::X1;
74case AArch64::W2:
return AArch64::X2;
75case AArch64::W3:
return AArch64::X3;
76case AArch64::W4:
return AArch64::X4;
77case AArch64::W5:
return AArch64::X5;
78case AArch64::W6:
return AArch64::X6;
79case AArch64::W7:
return AArch64::X7;
80case AArch64::W8:
return AArch64::X8;
81case AArch64::W9:
return AArch64::X9;
82case AArch64::W10:
return AArch64::X10;
83case AArch64::W11:
return AArch64::X11;
84case AArch64::W12:
return AArch64::X12;
85case AArch64::W13:
return AArch64::X13;
86case AArch64::W14:
return AArch64::X14;
87case AArch64::W15:
return AArch64::X15;
88case AArch64::W16:
return AArch64::X16;
89case AArch64::W17:
return AArch64::X17;
90case AArch64::W18:
return AArch64::X18;
91case AArch64::W19:
return AArch64::X19;
92case AArch64::W20:
return AArch64::X20;
93case AArch64::W21:
return AArch64::X21;
94case AArch64::W22:
return AArch64::X22;
95case AArch64::W23:
return AArch64::X23;
96case AArch64::W24:
return AArch64::X24;
97case AArch64::W25:
return AArch64::X25;
98case AArch64::W26:
return AArch64::X26;
99case AArch64::W27:
return AArch64::X27;
100case AArch64::W28:
return AArch64::X28;
101case AArch64::W29:
return AArch64::FP;
102case AArch64::W30:
return AArch64::LR;
103case AArch64::WSP:
return AArch64::SP;
104case AArch64::WZR:
return AArch64::XZR;
106// For anything else, return it unchanged. 111switch (RegTuple.
id()) {
112case AArch64::X0_X1_X2_X3_X4_X5_X6_X7:
return AArch64::X0;
113case AArch64::X2_X3_X4_X5_X6_X7_X8_X9:
return AArch64::X2;
114case AArch64::X4_X5_X6_X7_X8_X9_X10_X11:
return AArch64::X4;
115case AArch64::X6_X7_X8_X9_X10_X11_X12_X13:
return AArch64::X6;
116case AArch64::X8_X9_X10_X11_X12_X13_X14_X15:
return AArch64::X8;
117case AArch64::X10_X11_X12_X13_X14_X15_X16_X17:
return AArch64::X10;
118case AArch64::X12_X13_X14_X15_X16_X17_X18_X19:
return AArch64::X12;
119case AArch64::X14_X15_X16_X17_X18_X19_X20_X21:
return AArch64::X14;
120case AArch64::X16_X17_X18_X19_X20_X21_X22_X23:
return AArch64::X16;
121case AArch64::X18_X19_X20_X21_X22_X23_X24_X25:
return AArch64::X18;
122case AArch64::X20_X21_X22_X23_X24_X25_X26_X27:
return AArch64::X20;
123case AArch64::X22_X23_X24_X25_X26_X27_X28_FP:
return AArch64::X22;
125// For anything else, return it unchanged. 131case AArch64::D0:
return AArch64::B0;
132case AArch64::D1:
return AArch64::B1;
133case AArch64::D2:
return AArch64::B2;
134case AArch64::D3:
return AArch64::B3;
135case AArch64::D4:
return AArch64::B4;
136case AArch64::D5:
return AArch64::B5;
137case AArch64::D6:
return AArch64::B6;
138case AArch64::D7:
return AArch64::B7;
139case AArch64::D8:
return AArch64::B8;
140case AArch64::D9:
return AArch64::B9;
141case AArch64::D10:
return AArch64::B10;
142case AArch64::D11:
return AArch64::B11;
143case AArch64::D12:
return AArch64::B12;
144case AArch64::D13:
return AArch64::B13;
145case AArch64::D14:
return AArch64::B14;
146case AArch64::D15:
return AArch64::B15;
147case AArch64::D16:
return AArch64::B16;
148case AArch64::D17:
return AArch64::B17;
149case AArch64::D18:
return AArch64::B18;
150case AArch64::D19:
return AArch64::B19;
151case AArch64::D20:
return AArch64::B20;
152case AArch64::D21:
return AArch64::B21;
153case AArch64::D22:
return AArch64::B22;
154case AArch64::D23:
return AArch64::B23;
155case AArch64::D24:
return AArch64::B24;
156case AArch64::D25:
return AArch64::B25;
157case AArch64::D26:
return AArch64::B26;
158case AArch64::D27:
return AArch64::B27;
159case AArch64::D28:
return AArch64::B28;
160case AArch64::D29:
return AArch64::B29;
161case AArch64::D30:
return AArch64::B30;
162case AArch64::D31:
return AArch64::B31;
164// For anything else, return it unchanged. 170case AArch64::B0:
return AArch64::D0;
171case AArch64::B1:
return AArch64::D1;
172case AArch64::B2:
return AArch64::D2;
173case AArch64::B3:
return AArch64::D3;
174case AArch64::B4:
return AArch64::D4;
175case AArch64::B5:
return AArch64::D5;
176case AArch64::B6:
return AArch64::D6;
177case AArch64::B7:
return AArch64::D7;
178case AArch64::B8:
return AArch64::D8;
179case AArch64::B9:
return AArch64::D9;
180case AArch64::B10:
return AArch64::D10;
181case AArch64::B11:
return AArch64::D11;
182case AArch64::B12:
return AArch64::D12;
183case AArch64::B13:
return AArch64::D13;
184case AArch64::B14:
return AArch64::D14;
185case AArch64::B15:
return AArch64::D15;
186case AArch64::B16:
return AArch64::D16;
187case AArch64::B17:
return AArch64::D17;
188case AArch64::B18:
return AArch64::D18;
189case AArch64::B19:
return AArch64::D19;
190case AArch64::B20:
return AArch64::D20;
191case AArch64::B21:
return AArch64::D21;
192case AArch64::B22:
return AArch64::D22;
193case AArch64::B23:
return AArch64::D23;
194case AArch64::B24:
return AArch64::D24;
195case AArch64::B25:
return AArch64::D25;
196case AArch64::B26:
return AArch64::D26;
197case AArch64::B27:
return AArch64::D27;
198case AArch64::B28:
return AArch64::D28;
199case AArch64::B29:
return AArch64::D29;
200case AArch64::B30:
return AArch64::D30;
201case AArch64::B31:
return AArch64::D31;
203// For anything else, return it unchanged. 209case AArch64::LDADDAB:
case AArch64::LDADDAH:
210case AArch64::LDADDAW:
case AArch64::LDADDAX:
211case AArch64::LDADDALB:
case AArch64::LDADDALH:
212case AArch64::LDADDALW:
case AArch64::LDADDALX:
213case AArch64::LDCLRAB:
case AArch64::LDCLRAH:
214case AArch64::LDCLRAW:
case AArch64::LDCLRAX:
215case AArch64::LDCLRALB:
case AArch64::LDCLRALH:
216case AArch64::LDCLRALW:
case AArch64::LDCLRALX:
217case AArch64::LDEORAB:
case AArch64::LDEORAH:
218case AArch64::LDEORAW:
case AArch64::LDEORAX:
219case AArch64::LDEORALB:
case AArch64::LDEORALH:
220case AArch64::LDEORALW:
case AArch64::LDEORALX:
221case AArch64::LDSETAB:
case AArch64::LDSETAH:
222case AArch64::LDSETAW:
case AArch64::LDSETAX:
223case AArch64::LDSETALB:
case AArch64::LDSETALH:
224case AArch64::LDSETALW:
case AArch64::LDSETALX:
225case AArch64::LDSMAXAB:
case AArch64::LDSMAXAH:
226case AArch64::LDSMAXAW:
case AArch64::LDSMAXAX:
227case AArch64::LDSMAXALB:
case AArch64::LDSMAXALH:
228case AArch64::LDSMAXALW:
case AArch64::LDSMAXALX:
229case AArch64::LDSMINAB:
case AArch64::LDSMINAH:
230case AArch64::LDSMINAW:
case AArch64::LDSMINAX:
231case AArch64::LDSMINALB:
case AArch64::LDSMINALH:
232case AArch64::LDSMINALW:
case AArch64::LDSMINALX:
233case AArch64::LDUMAXAB:
case AArch64::LDUMAXAH:
234case AArch64::LDUMAXAW:
case AArch64::LDUMAXAX:
235case AArch64::LDUMAXALB:
case AArch64::LDUMAXALH:
236case AArch64::LDUMAXALW:
case AArch64::LDUMAXALX:
237case AArch64::LDUMINAB:
case AArch64::LDUMINAH:
238case AArch64::LDUMINAW:
case AArch64::LDUMINAX:
239case AArch64::LDUMINALB:
case AArch64::LDUMINALH:
240case AArch64::LDUMINALW:
case AArch64::LDUMINALX:
241case AArch64::SWPAB:
case AArch64::SWPAH:
242case AArch64::SWPAW:
case AArch64::SWPAX:
243case AArch64::SWPALB:
case AArch64::SWPALH:
244case AArch64::SWPALW:
case AArch64::SWPALX:
252// The CondCodes constants map directly to the 4-bit encoding of the condition 253// field for predicated instructions. 254enumCondCode {
// Meaning (integer) Meaning (floating-point) 255EQ = 0x0,
// Equal Equal 256NE = 0x1,
// Not equal Not equal, or unordered 257HS = 0x2,
// Unsigned higher or same >, ==, or unordered 258LO = 0x3,
// Unsigned lower Less than 259MI = 0x4,
// Minus, negative Less than 260PL = 0x5,
// Plus, positive or zero >, ==, or unordered 261VS = 0x6,
// Overflow Unordered 262VC = 0x7,
// No overflow Not unordered 263HI = 0x8,
// Unsigned higher Greater than, or unordered 264LS = 0x9,
// Unsigned lower or same Less than or equal 265GE = 0xa,
// Greater than or equal Greater than or equal 266LT = 0xb,
// Less than Less than, or unordered 267GT = 0xc,
// Greater than Greater than 268LE = 0xd,
// Less than or equal <, ==, or unordered 269AL = 0xe,
// Always (unconditional) Always (unconditional) 270NV = 0xf,
// Always (unconditional) Always (unconditional) 271// Note the NV exists purely to disassemble 0b1111. Execution is "always". 274// Common aliases used for SVE. 304// To reverse a condition it's necessary to only invert the low bit: 306returnstatic_cast<CondCode>(
static_cast<unsigned>(Code) ^ 0x1);
309/// getSwappedCondition - assume the flags are set by MI(a,b), return 310/// the condition code if we modify the instructions such that flags are 339/// Given a condition code, return NZCV flags that would satisfy that condition. 340/// The flag bits are in the format expected by the ccmp instructions. 341/// Note that many different flag settings can satisfy a given condition code, 342/// this function just returns one of them. 344// NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7. 345enum {
N = 8, Z = 4,
C = 2, V = 1 };
348caseEQ:
return Z;
// Z == 1 349caseNE:
return 0;
// Z == 0 350caseHS:
returnC;
// C == 1 351caseLO:
return 0;
// C == 0 352caseMI:
returnN;
// N == 1 353casePL:
return 0;
// N == 0 354caseVS:
return V;
// V == 1 355caseVC:
return 0;
// V == 0 356caseHI:
returnC;
// C == 1 && Z == 0 357caseLS:
return 0;
// C == 0 || Z == 1 358caseGE:
return 0;
// N == V 359caseLT:
returnN;
// N != V 360caseGT:
return 0;
// Z == 0 && N == V 361caseLE:
return Z;
// Z == 1 || N != V 365}
// end namespace AArch64CC 377return ActiveFeatures[llvm::AArch64::FeatureAll] ||
400namespaceAArch64SVCR {
404#define GET_SVCRValues_DECL 405#define GET_SVCRsList_DECL 406#include "AArch64GenSystemOperands.inc" 413#define GET_ATValues_DECL 414#define GET_ATsList_DECL 415#include "AArch64GenSystemOperands.inc" 422#define GET_DBValues_DECL 423#define GET_DBsList_DECL 424#include "AArch64GenSystemOperands.inc" 427namespaceAArch64DBnXS {
431#define GET_DBnXSValues_DECL 432#define GET_DBnXSsList_DECL 433#include "AArch64GenSystemOperands.inc" 440#define GET_DCValues_DECL 441#define GET_DCsList_DECL 442#include "AArch64GenSystemOperands.inc" 449#define GET_ICValues_DECL 450#define GET_ICsList_DECL 451#include "AArch64GenSystemOperands.inc" 458#define GET_ISBValues_DECL 459#define GET_ISBsList_DECL 460#include "AArch64GenSystemOperands.inc" 467#define GET_TSBValues_DECL 468#define GET_TSBsList_DECL 469#include "AArch64GenSystemOperands.inc" 472namespaceAArch64PRFM {
476#define GET_PRFMValues_DECL 477#define GET_PRFMsList_DECL 478#include "AArch64GenSystemOperands.inc" 481namespaceAArch64SVEPRFM {
485#define GET_SVEPRFMValues_DECL 486#define GET_SVEPRFMsList_DECL 487#include "AArch64GenSystemOperands.inc" 490namespaceAArch64RPRFM {
494#define GET_RPRFMValues_DECL 495#define GET_RPRFMsList_DECL 496#include "AArch64GenSystemOperands.inc" 497}
// namespace AArch64RPRFM 499namespaceAArch64SVEPredPattern {
504#define GET_SVEPREDPATValues_DECL 505#define GET_SVEPREDPATsList_DECL 506#include "AArch64GenSystemOperands.inc" 509namespaceAArch64SVEVecLenSpecifier {
514#define GET_SVEVECLENSPECIFIERValues_DECL 515#define GET_SVEVECLENSPECIFIERsList_DECL 516#include "AArch64GenSystemOperands.inc" 517}
// namespace AArch64SVEVecLenSpecifier 519/// Return the number of active elements for VL1 to VL256 predicate pattern, 520/// zero for all other patterns. 525case AArch64SVEPredPattern::vl1:
526case AArch64SVEPredPattern::vl2:
527case AArch64SVEPredPattern::vl3:
528case AArch64SVEPredPattern::vl4:
529case AArch64SVEPredPattern::vl5:
530case AArch64SVEPredPattern::vl6:
531case AArch64SVEPredPattern::vl7:
532case AArch64SVEPredPattern::vl8:
534case AArch64SVEPredPattern::vl16:
536case AArch64SVEPredPattern::vl32:
538case AArch64SVEPredPattern::vl64:
540case AArch64SVEPredPattern::vl128:
542case AArch64SVEPredPattern::vl256:
547/// Return specific VL predicate pattern based on the number of elements. 548inline std::optional<unsigned>
563return AArch64SVEPredPattern::vl16;
565return AArch64SVEPredPattern::vl32;
567return AArch64SVEPredPattern::vl64;
569return AArch64SVEPredPattern::vl128;
571return AArch64SVEPredPattern::vl256;
575/// An enum to describe what types of loops we should attempt to tail-fold: 577/// Reductions: Loops containing reductions 578/// Recurrences: Loops with first-order recurrences, i.e. that would 579/// require a SVE splice instruction 580/// Reverse: Reverse loops 581/// Simple: Loops that are not reversed and don't contain reductions 582/// or first-order recurrences. 596namespaceAArch64ExactFPImm {
601#define GET_ExactFPImmValues_DECL 602#define GET_ExactFPImmsList_DECL 603#include "AArch64GenSystemOperands.inc" 606namespaceAArch64PState {
610#define GET_PStateImm0_15Values_DECL 611#define GET_PStateImm0_15sList_DECL 612#include "AArch64GenSystemOperands.inc" 617#define GET_PStateImm0_1Values_DECL 618#define GET_PStateImm0_1sList_DECL 619#include "AArch64GenSystemOperands.inc" 622namespaceAArch64PSBHint {
626#define GET_PSBValues_DECL 627#define GET_PSBsList_DECL 628#include "AArch64GenSystemOperands.inc" 631namespaceAArch64PHint {
638return ActiveFeatures[llvm::AArch64::FeatureAll] ||
643#define GET_PHintValues_DECL 644#define GET_PHintsList_DECL 645#include "AArch64GenSystemOperands.inc" 649}
// namespace AArch64PHint 651namespaceAArch64BTIHint {
655#define GET_BTIValues_DECL 656#define GET_BTIsList_DECL 657#include "AArch64GenSystemOperands.inc" 689namespaceAArch64Layout {
702// Bare layout for the 128-bit vector 703// (only show ".b", ".h", ".s", ".d" without vector number) 711inlinestaticconstchar *
748namespaceAArch64SysReg {
757return ActiveFeatures[llvm::AArch64::FeatureAll] ||
762#define GET_SysRegsList_DECL 763#define GET_SysRegValues_DECL 764#include "AArch64GenSystemOperands.inc" 770namespaceAArch64TLBI {
774 #define GET_TLBITable_DECL 775 #include "AArch64GenSystemOperands.inc" 779/// Target Operand Flag enum. 781//===------------------------------------------------------------------===// 782// AArch64 Specific MachineOperand flags. 788 /// MO_PAGE - A symbol operand with this flag represents the pc-relative 789 /// offset of the 4K page containing the symbol. This is used with the 790 /// ADRP instruction. 793 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of 794 /// that symbol within a 4K page. This offset is added to the page address 795 /// to produce the complete address. 798 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high 799 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction 802 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits 803 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction 806 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits 807 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction 810 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits 811 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction 814 /// MO_HI12 - This flag indicates that a symbol operand represents the bits 815 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left- 816 /// by-12-bits instruction. 819 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the 820 /// reference is actually to the ".refptr.FOO" symbol. This is used for 821 /// stub symbols on windows. 824 /// MO_GOT - This flag indicates that a symbol operand represents the 825 /// address of the GOT entry for the symbol, rather than the address of 826 /// the symbol itself. 829 /// MO_NC - Indicates whether the linker is expected to check the symbol 830 /// reference for overflow. For example in an ADRP/ADD pair of relocations 831 /// the ADRP usually does check, but not the ADD. 834 /// MO_TLS - Indicates that the operand being accessed is some kind of 835 /// thread-local symbol. On Darwin, only one type of thread-local access 836 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the 837 /// referee will affect interpretation. 840 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference 841 /// to the symbol is for an import stub. This is used for DLL import 842 /// storage class indication on Windows. 845 /// MO_S - Indicates that the bits of the symbol operand represented by 846 /// MO_G0 etc are signed. 849 /// MO_PREL - Indicates that the bits of the symbol operand represented by 850 /// MO_G0 etc are PC relative. 853 /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag 855 /// On a FrameIndex operand, indicates that the underlying memory is tagged 856 /// with an unknown tag value (MTE); this needs to be lowered either to an 857 /// SP-relative load or store instruction (which do not check tags), or to 858 /// an LDG instruction to obtain the tag value. 861 /// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version 862 /// of a symbol, not the original. For dllimport symbols, this means it 863 /// uses "__imp_aux". For other symbols, this means it uses the mangled 864 /// ("#" prefix for C) name. 867}
// end namespace AArch64II 869//===----------------------------------------------------------------------===// 870// v8.3a Pointer Authentication 873namespaceAArch64PACKey {
881}
// namespace AArch64PACKey 883/// Return 2-letter identifier string for numeric key ID. 898/// Return numeric key ID for 2-letter identifier string. 899inlinestatic std::optional<AArch64PACKey::ID>
913// The number of bits in a SVE register is architecturally defined 914// to be a multiple of this value. If <M x t> has this number of bits, 915// a <n x M x t> vector can be stored in a SVE register without any 916// redundant bits. If <M x t> has this number of bits divided by P, 917// a <n x M x t> vector is stored in a SVE register by placing index i 918// in index i*P of a <n x (M*P) x t> vector. The other elements of the 919// <n x (M*P) x t> vector (such as index 1) are undefined. 922}
// end namespace AArch64 923}
// end namespace llvm #define LLVM_DECLARE_ENUM_AS_BITMASK(Enum, LargestValue)
LLVM_DECLARE_ENUM_AS_BITMASK can be used to declare an enum type as a bit set, so that bitwise operat...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains some templates that are useful if you are working with the STL at all.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Container class for subtarget features.
Wrapper class representing physical registers. Should be passed by value.
constexpr unsigned id() const
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static CondCode getSwappedCondition(CondCode CC)
getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the...
static const char * getCondCodeName(CondCode Code)
static CondCode getInvertedCondCode(CondCode Code)
static unsigned getNZCVToSatisfyCondCode(CondCode Code)
Given a condition code, return NZCV flags that would satisfy that condition.
TOF
Target Operand Flag enum.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_G1
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address,...
@ MO_S
MO_S - Indicates that the bits of the symbol operand represented by MO_G0 etc are signed.
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_PREL
MO_PREL - Indicates that the bits of the symbol operand represented by MO_G0 etc are PC relative.
@ MO_G0
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address,...
@ MO_ARM64EC_CALLMANGLE
MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version of a symbol,...
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
@ MO_HI12
MO_HI12 - This flag indicates that a symbol operand represents the bits 13-24 of a 64-bit address,...
@ MO_TLS
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
@ MO_G2
MO_G2 - A symbol operand with this flag (granule 2) represents the bits 32-47 of a 64-bit address,...
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
const PHint * lookupPHintByName(StringRef)
const PHint * lookupPHintByEncoding(uint16_t)
uint32_t parseGenericRegister(StringRef Name)
std::string genericRegisterString(uint32_t Bits)
static constexpr unsigned SVEMaxBitsPerVector
static constexpr unsigned SVEBitsPerBlock
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
static std::optional< AArch64PACKey::ID > AArch64StringToPACKeyID(StringRef Name)
Return numeric key ID for 2-letter identifier string.
TailFoldingOpts
An enum to describe what types of loops we should attempt to tail-fold: Disabled: None Reductions: Lo...
static AArch64Layout::VectorLayout AArch64StringToVectorLayout(StringRef LayoutStr)
static const char * AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)
std::optional< unsigned > getSVEPredPatternFromNumElements(unsigned MinNumElts)
Return specific VL predicate pattern based on the number of elements.
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
static MCRegister getXRegFromWReg(MCRegister Reg)
static MCRegister getXRegFromXRegTuple(MCRegister RegTuple)
static MCRegister getWRegFromXReg(MCRegister Reg)
unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
Return the number of active elements for VL1 to VL256 predicate pattern, zero for all other patterns.
static MCRegister getDRegFromBReg(MCRegister Reg)
static MCRegister getBRegFromDReg(MCRegister Reg)
static StringRef AArch64PACKeyIDToString(AArch64PACKey::ID KeyID)
Return 2-letter identifier string for numeric key ID.
bool haveFeatures(FeatureBitset ActiveFeatures) const
FeatureBitset FeaturesRequired
FeatureBitset FeaturesRequired
bool haveFeatures(FeatureBitset ActiveFeatures) const
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
bool haveFeatures(FeatureBitset ActiveFeatures) const
constexpr SysAlias(const char *N, uint16_t E)
FeatureBitset getRequiredFeatures() const
FeatureBitset FeaturesRequired
constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)