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LLVM 20.0.0git
AArch64BaseInfo.h
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1//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone helper functions and enum definitions for
10// the AArch64 target useful for the compiler back-end and the MC libraries.
11// As such, it deliberately does not include references to LLVM core
12// code gen types, passes, etc..
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
17#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18
19// FIXME: Is it easiest to fix this layering violation by moving the .inc
20// #includes from AArch64MCTargetDesc.h to here?
21#include "MCTargetDesc/AArch64MCTargetDesc.h"// For AArch64::X0 and friends.
22#include "llvm/ADT/BitmaskEnum.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/StringSwitch.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/TargetParser/SubtargetFeature.h"
27
28namespacellvm {
29
30inlinestaticMCRegistergetWRegFromXReg(MCRegisterReg) {
31switch (Reg.id()) {
32case AArch64::X0:return AArch64::W0;
33case AArch64::X1:return AArch64::W1;
34case AArch64::X2:return AArch64::W2;
35case AArch64::X3:return AArch64::W3;
36case AArch64::X4:return AArch64::W4;
37case AArch64::X5:return AArch64::W5;
38case AArch64::X6:return AArch64::W6;
39case AArch64::X7:return AArch64::W7;
40case AArch64::X8:return AArch64::W8;
41case AArch64::X9:return AArch64::W9;
42case AArch64::X10:return AArch64::W10;
43case AArch64::X11:return AArch64::W11;
44case AArch64::X12:return AArch64::W12;
45case AArch64::X13:return AArch64::W13;
46case AArch64::X14:return AArch64::W14;
47case AArch64::X15:return AArch64::W15;
48case AArch64::X16:return AArch64::W16;
49case AArch64::X17:return AArch64::W17;
50case AArch64::X18:return AArch64::W18;
51case AArch64::X19:return AArch64::W19;
52case AArch64::X20:return AArch64::W20;
53case AArch64::X21:return AArch64::W21;
54case AArch64::X22:return AArch64::W22;
55case AArch64::X23:return AArch64::W23;
56case AArch64::X24:return AArch64::W24;
57case AArch64::X25:return AArch64::W25;
58case AArch64::X26:return AArch64::W26;
59case AArch64::X27:return AArch64::W27;
60case AArch64::X28:return AArch64::W28;
61case AArch64::FP:return AArch64::W29;
62case AArch64::LR:return AArch64::W30;
63case AArch64::SP:return AArch64::WSP;
64case AArch64::XZR:return AArch64::WZR;
65 }
66// For anything else, return it unchanged.
67returnReg;
68}
69
70inlinestaticMCRegistergetXRegFromWReg(MCRegisterReg) {
71switch (Reg.id()) {
72case AArch64::W0:return AArch64::X0;
73case AArch64::W1:return AArch64::X1;
74case AArch64::W2:return AArch64::X2;
75case AArch64::W3:return AArch64::X3;
76case AArch64::W4:return AArch64::X4;
77case AArch64::W5:return AArch64::X5;
78case AArch64::W6:return AArch64::X6;
79case AArch64::W7:return AArch64::X7;
80case AArch64::W8:return AArch64::X8;
81case AArch64::W9:return AArch64::X9;
82case AArch64::W10:return AArch64::X10;
83case AArch64::W11:return AArch64::X11;
84case AArch64::W12:return AArch64::X12;
85case AArch64::W13:return AArch64::X13;
86case AArch64::W14:return AArch64::X14;
87case AArch64::W15:return AArch64::X15;
88case AArch64::W16:return AArch64::X16;
89case AArch64::W17:return AArch64::X17;
90case AArch64::W18:return AArch64::X18;
91case AArch64::W19:return AArch64::X19;
92case AArch64::W20:return AArch64::X20;
93case AArch64::W21:return AArch64::X21;
94case AArch64::W22:return AArch64::X22;
95case AArch64::W23:return AArch64::X23;
96case AArch64::W24:return AArch64::X24;
97case AArch64::W25:return AArch64::X25;
98case AArch64::W26:return AArch64::X26;
99case AArch64::W27:return AArch64::X27;
100case AArch64::W28:return AArch64::X28;
101case AArch64::W29:return AArch64::FP;
102case AArch64::W30:return AArch64::LR;
103case AArch64::WSP:return AArch64::SP;
104case AArch64::WZR:return AArch64::XZR;
105 }
106// For anything else, return it unchanged.
107returnReg;
108}
109
110inlinestaticMCRegistergetXRegFromXRegTuple(MCRegister RegTuple) {
111switch (RegTuple.id()) {
112case AArch64::X0_X1_X2_X3_X4_X5_X6_X7:return AArch64::X0;
113case AArch64::X2_X3_X4_X5_X6_X7_X8_X9:return AArch64::X2;
114case AArch64::X4_X5_X6_X7_X8_X9_X10_X11:return AArch64::X4;
115case AArch64::X6_X7_X8_X9_X10_X11_X12_X13:return AArch64::X6;
116case AArch64::X8_X9_X10_X11_X12_X13_X14_X15:return AArch64::X8;
117case AArch64::X10_X11_X12_X13_X14_X15_X16_X17:return AArch64::X10;
118case AArch64::X12_X13_X14_X15_X16_X17_X18_X19:return AArch64::X12;
119case AArch64::X14_X15_X16_X17_X18_X19_X20_X21:return AArch64::X14;
120case AArch64::X16_X17_X18_X19_X20_X21_X22_X23:return AArch64::X16;
121case AArch64::X18_X19_X20_X21_X22_X23_X24_X25:return AArch64::X18;
122case AArch64::X20_X21_X22_X23_X24_X25_X26_X27:return AArch64::X20;
123case AArch64::X22_X23_X24_X25_X26_X27_X28_FP:return AArch64::X22;
124 }
125// For anything else, return it unchanged.
126return RegTuple;
127}
128
129staticinlineMCRegistergetBRegFromDReg(MCRegisterReg) {
130switch (Reg.id()) {
131case AArch64::D0:return AArch64::B0;
132case AArch64::D1:return AArch64::B1;
133case AArch64::D2:return AArch64::B2;
134case AArch64::D3:return AArch64::B3;
135case AArch64::D4:return AArch64::B4;
136case AArch64::D5:return AArch64::B5;
137case AArch64::D6:return AArch64::B6;
138case AArch64::D7:return AArch64::B7;
139case AArch64::D8:return AArch64::B8;
140case AArch64::D9:return AArch64::B9;
141case AArch64::D10:return AArch64::B10;
142case AArch64::D11:return AArch64::B11;
143case AArch64::D12:return AArch64::B12;
144case AArch64::D13:return AArch64::B13;
145case AArch64::D14:return AArch64::B14;
146case AArch64::D15:return AArch64::B15;
147case AArch64::D16:return AArch64::B16;
148case AArch64::D17:return AArch64::B17;
149case AArch64::D18:return AArch64::B18;
150case AArch64::D19:return AArch64::B19;
151case AArch64::D20:return AArch64::B20;
152case AArch64::D21:return AArch64::B21;
153case AArch64::D22:return AArch64::B22;
154case AArch64::D23:return AArch64::B23;
155case AArch64::D24:return AArch64::B24;
156case AArch64::D25:return AArch64::B25;
157case AArch64::D26:return AArch64::B26;
158case AArch64::D27:return AArch64::B27;
159case AArch64::D28:return AArch64::B28;
160case AArch64::D29:return AArch64::B29;
161case AArch64::D30:return AArch64::B30;
162case AArch64::D31:return AArch64::B31;
163 }
164// For anything else, return it unchanged.
165returnReg;
166}
167
168staticinlineMCRegistergetDRegFromBReg(MCRegisterReg) {
169switch (Reg.id()) {
170case AArch64::B0:return AArch64::D0;
171case AArch64::B1:return AArch64::D1;
172case AArch64::B2:return AArch64::D2;
173case AArch64::B3:return AArch64::D3;
174case AArch64::B4:return AArch64::D4;
175case AArch64::B5:return AArch64::D5;
176case AArch64::B6:return AArch64::D6;
177case AArch64::B7:return AArch64::D7;
178case AArch64::B8:return AArch64::D8;
179case AArch64::B9:return AArch64::D9;
180case AArch64::B10:return AArch64::D10;
181case AArch64::B11:return AArch64::D11;
182case AArch64::B12:return AArch64::D12;
183case AArch64::B13:return AArch64::D13;
184case AArch64::B14:return AArch64::D14;
185case AArch64::B15:return AArch64::D15;
186case AArch64::B16:return AArch64::D16;
187case AArch64::B17:return AArch64::D17;
188case AArch64::B18:return AArch64::D18;
189case AArch64::B19:return AArch64::D19;
190case AArch64::B20:return AArch64::D20;
191case AArch64::B21:return AArch64::D21;
192case AArch64::B22:return AArch64::D22;
193case AArch64::B23:return AArch64::D23;
194case AArch64::B24:return AArch64::D24;
195case AArch64::B25:return AArch64::D25;
196case AArch64::B26:return AArch64::D26;
197case AArch64::B27:return AArch64::D27;
198case AArch64::B28:return AArch64::D28;
199case AArch64::B29:return AArch64::D29;
200case AArch64::B30:return AArch64::D30;
201case AArch64::B31:return AArch64::D31;
202 }
203// For anything else, return it unchanged.
204returnReg;
205}
206
207staticinlineboolatomicBarrierDroppedOnZero(unsigned Opcode) {
208switch (Opcode) {
209case AArch64::LDADDAB:case AArch64::LDADDAH:
210case AArch64::LDADDAW:case AArch64::LDADDAX:
211case AArch64::LDADDALB:case AArch64::LDADDALH:
212case AArch64::LDADDALW:case AArch64::LDADDALX:
213case AArch64::LDCLRAB:case AArch64::LDCLRAH:
214case AArch64::LDCLRAW:case AArch64::LDCLRAX:
215case AArch64::LDCLRALB:case AArch64::LDCLRALH:
216case AArch64::LDCLRALW:case AArch64::LDCLRALX:
217case AArch64::LDEORAB:case AArch64::LDEORAH:
218case AArch64::LDEORAW:case AArch64::LDEORAX:
219case AArch64::LDEORALB:case AArch64::LDEORALH:
220case AArch64::LDEORALW:case AArch64::LDEORALX:
221case AArch64::LDSETAB:case AArch64::LDSETAH:
222case AArch64::LDSETAW:case AArch64::LDSETAX:
223case AArch64::LDSETALB:case AArch64::LDSETALH:
224case AArch64::LDSETALW:case AArch64::LDSETALX:
225case AArch64::LDSMAXAB:case AArch64::LDSMAXAH:
226case AArch64::LDSMAXAW:case AArch64::LDSMAXAX:
227case AArch64::LDSMAXALB:case AArch64::LDSMAXALH:
228case AArch64::LDSMAXALW:case AArch64::LDSMAXALX:
229case AArch64::LDSMINAB:case AArch64::LDSMINAH:
230case AArch64::LDSMINAW:case AArch64::LDSMINAX:
231case AArch64::LDSMINALB:case AArch64::LDSMINALH:
232case AArch64::LDSMINALW:case AArch64::LDSMINALX:
233case AArch64::LDUMAXAB:case AArch64::LDUMAXAH:
234case AArch64::LDUMAXAW:case AArch64::LDUMAXAX:
235case AArch64::LDUMAXALB:case AArch64::LDUMAXALH:
236case AArch64::LDUMAXALW:case AArch64::LDUMAXALX:
237case AArch64::LDUMINAB:case AArch64::LDUMINAH:
238case AArch64::LDUMINAW:case AArch64::LDUMINAX:
239case AArch64::LDUMINALB:case AArch64::LDUMINALH:
240case AArch64::LDUMINALW:case AArch64::LDUMINALX:
241case AArch64::SWPAB:case AArch64::SWPAH:
242case AArch64::SWPAW:case AArch64::SWPAX:
243case AArch64::SWPALB:case AArch64::SWPALH:
244case AArch64::SWPALW:case AArch64::SWPALX:
245returntrue;
246 }
247returnfalse;
248}
249
250namespaceAArch64CC {
251
252// The CondCodes constants map directly to the 4-bit encoding of the condition
253// field for predicated instructions.
254enumCondCode {// Meaning (integer) Meaning (floating-point)
255EQ = 0x0,// Equal Equal
256NE = 0x1,// Not equal Not equal, or unordered
257HS = 0x2,// Unsigned higher or same >, ==, or unordered
258LO = 0x3,// Unsigned lower Less than
259MI = 0x4,// Minus, negative Less than
260PL = 0x5,// Plus, positive or zero >, ==, or unordered
261VS = 0x6,// Overflow Unordered
262VC = 0x7,// No overflow Not unordered
263HI = 0x8,// Unsigned higher Greater than, or unordered
264LS = 0x9,// Unsigned lower or same Less than or equal
265GE = 0xa,// Greater than or equal Greater than or equal
266LT = 0xb,// Less than Less than, or unordered
267GT = 0xc,// Greater than Greater than
268LE = 0xd,// Less than or equal <, ==, or unordered
269AL = 0xe,// Always (unconditional) Always (unconditional)
270NV = 0xf,// Always (unconditional) Always (unconditional)
271// Note the NV exists purely to disassemble 0b1111. Execution is "always".
272Invalid,
273
274// Common aliases used for SVE.
275ANY_ACTIVE =NE,// (!Z)
276FIRST_ACTIVE =MI,// ( N)
277LAST_ACTIVE =LO,// (!C)
278NONE_ACTIVE =EQ// ( Z)
279};
280
281inlinestaticconstchar *getCondCodeName(CondCode Code) {
282switch (Code) {
283default:llvm_unreachable("Unknown condition code");
284caseEQ:return"eq";
285caseNE:return"ne";
286caseHS:return"hs";
287caseLO:return"lo";
288caseMI:return"mi";
289casePL:return"pl";
290caseVS:return"vs";
291caseVC:return"vc";
292caseHI:return"hi";
293caseLS:return"ls";
294caseGE:return"ge";
295caseLT:return"lt";
296caseGT:return"gt";
297caseLE:return"le";
298caseAL:return"al";
299caseNV:return"nv";
300 }
301}
302
303inlinestaticCondCodegetInvertedCondCode(CondCode Code) {
304// To reverse a condition it's necessary to only invert the low bit:
305
306returnstatic_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
307}
308
309/// getSwappedCondition - assume the flags are set by MI(a,b), return
310/// the condition code if we modify the instructions such that flags are
311/// set by MI(b,a).
312inlinestaticCondCodegetSwappedCondition(CondCodeCC) {
313switch (CC) {
314default:
315returnAL;
316caseEQ:
317returnEQ;
318caseNE:
319returnNE;
320caseHS:
321returnLS;
322caseLO:
323returnHI;
324caseHI:
325returnLO;
326caseLS:
327returnHS;
328caseGE:
329returnLE;
330caseLT:
331returnGT;
332caseGT:
333returnLT;
334caseLE:
335returnGE;
336 }
337}
338
339/// Given a condition code, return NZCV flags that would satisfy that condition.
340/// The flag bits are in the format expected by the ccmp instructions.
341/// Note that many different flag settings can satisfy a given condition code,
342/// this function just returns one of them.
343inlinestaticunsignedgetNZCVToSatisfyCondCode(CondCode Code) {
344// NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
345enum {N = 8, Z = 4,C = 2, V = 1 };
346switch (Code) {
347default:llvm_unreachable("Unknown condition code");
348caseEQ:return Z;// Z == 1
349caseNE:return 0;// Z == 0
350caseHS:returnC;// C == 1
351caseLO:return 0;// C == 0
352caseMI:returnN;// N == 1
353casePL:return 0;// N == 0
354caseVS:return V;// V == 1
355caseVC:return 0;// V == 0
356caseHI:returnC;// C == 1 && Z == 0
357caseLS:return 0;// C == 0 || Z == 1
358caseGE:return 0;// N == V
359caseLT:returnN;// N != V
360caseGT:return 0;// Z == 0 && N == V
361caseLE:return Z;// Z == 1 || N != V
362 }
363}
364
365}// end namespace AArch64CC
366
367structSysAlias {
368constchar *Name;
369uint16_tEncoding;
370FeatureBitsetFeaturesRequired;
371
372constexprSysAlias(constchar *N,uint16_tE) :Name(N),Encoding(E) {}
373constexprSysAlias(constchar *N,uint16_tE,FeatureBitsetF)
374 :Name(N),Encoding(E),FeaturesRequired(F) {}
375
376boolhaveFeatures(FeatureBitset ActiveFeatures) const{
377return ActiveFeatures[llvm::AArch64::FeatureAll] ||
378 (FeaturesRequired & ActiveFeatures) ==FeaturesRequired;
379 }
380
381FeatureBitsetgetRequiredFeatures() const{returnFeaturesRequired; }
382};
383
384structSysAliasReg :SysAlias {
385boolNeedsReg;
386constexprSysAliasReg(constchar *N,uint16_tE,bool R)
387 :SysAlias(N,E),NeedsReg(R) {}
388constexprSysAliasReg(constchar *N,uint16_tE,bool R,FeatureBitsetF)
389 :SysAlias(N,E,F),NeedsReg(R) {}
390};
391
392structSysAliasImm :SysAlias {
393uint16_tImmValue;
394constexprSysAliasImm(constchar *N,uint16_tE,uint16_tI)
395 :SysAlias(N,E),ImmValue(I) {}
396constexprSysAliasImm(constchar *N,uint16_tE,uint16_tI,FeatureBitsetF)
397 :SysAlias(N,E,F),ImmValue(I) {}
398};
399
400namespaceAArch64SVCR {
401structSVCR :SysAlias{
402usingSysAlias::SysAlias;
403 };
404#define GET_SVCRValues_DECL
405#define GET_SVCRsList_DECL
406#include "AArch64GenSystemOperands.inc"
407}
408
409namespaceAArch64AT{
410structAT :SysAlias {
411usingSysAlias::SysAlias;
412 };
413#define GET_ATValues_DECL
414#define GET_ATsList_DECL
415#include "AArch64GenSystemOperands.inc"
416}
417
418namespaceAArch64DB {
419structDB :SysAlias {
420usingSysAlias::SysAlias;
421 };
422#define GET_DBValues_DECL
423#define GET_DBsList_DECL
424#include "AArch64GenSystemOperands.inc"
425}
426
427namespaceAArch64DBnXS {
428structDBnXS :SysAliasImm {
429usingSysAliasImm::SysAliasImm;
430 };
431#define GET_DBnXSValues_DECL
432#define GET_DBnXSsList_DECL
433#include "AArch64GenSystemOperands.inc"
434}
435
436namespaceAArch64DC {
437structDC :SysAlias {
438usingSysAlias::SysAlias;
439 };
440#define GET_DCValues_DECL
441#define GET_DCsList_DECL
442#include "AArch64GenSystemOperands.inc"
443}
444
445namespaceAArch64IC {
446structIC :SysAliasReg {
447usingSysAliasReg::SysAliasReg;
448 };
449#define GET_ICValues_DECL
450#define GET_ICsList_DECL
451#include "AArch64GenSystemOperands.inc"
452}
453
454namespaceAArch64ISB {
455structISB :SysAlias {
456usingSysAlias::SysAlias;
457 };
458#define GET_ISBValues_DECL
459#define GET_ISBsList_DECL
460#include "AArch64GenSystemOperands.inc"
461}
462
463namespaceAArch64TSB {
464structTSB :SysAlias {
465usingSysAlias::SysAlias;
466 };
467#define GET_TSBValues_DECL
468#define GET_TSBsList_DECL
469#include "AArch64GenSystemOperands.inc"
470}
471
472namespaceAArch64PRFM {
473structPRFM :SysAlias {
474usingSysAlias::SysAlias;
475 };
476#define GET_PRFMValues_DECL
477#define GET_PRFMsList_DECL
478#include "AArch64GenSystemOperands.inc"
479}
480
481namespaceAArch64SVEPRFM {
482structSVEPRFM :SysAlias {
483usingSysAlias::SysAlias;
484 };
485#define GET_SVEPRFMValues_DECL
486#define GET_SVEPRFMsList_DECL
487#include "AArch64GenSystemOperands.inc"
488}
489
490namespaceAArch64RPRFM {
491structRPRFM :SysAlias {
492usingSysAlias::SysAlias;
493};
494#define GET_RPRFMValues_DECL
495#define GET_RPRFMsList_DECL
496#include "AArch64GenSystemOperands.inc"
497}// namespace AArch64RPRFM
498
499namespaceAArch64SVEPredPattern {
500structSVEPREDPAT {
501constchar *Name;
502uint16_tEncoding;
503 };
504#define GET_SVEPREDPATValues_DECL
505#define GET_SVEPREDPATsList_DECL
506#include "AArch64GenSystemOperands.inc"
507}
508
509namespaceAArch64SVEVecLenSpecifier {
510structSVEVECLENSPECIFIER {
511constchar *Name;
512uint16_tEncoding;
513 };
514#define GET_SVEVECLENSPECIFIERValues_DECL
515#define GET_SVEVECLENSPECIFIERsList_DECL
516#include "AArch64GenSystemOperands.inc"
517}// namespace AArch64SVEVecLenSpecifier
518
519/// Return the number of active elements for VL1 to VL256 predicate pattern,
520/// zero for all other patterns.
521inlineunsignedgetNumElementsFromSVEPredPattern(unsignedPattern) {
522switch (Pattern) {
523default:
524return 0;
525case AArch64SVEPredPattern::vl1:
526case AArch64SVEPredPattern::vl2:
527case AArch64SVEPredPattern::vl3:
528case AArch64SVEPredPattern::vl4:
529case AArch64SVEPredPattern::vl5:
530case AArch64SVEPredPattern::vl6:
531case AArch64SVEPredPattern::vl7:
532case AArch64SVEPredPattern::vl8:
533returnPattern;
534case AArch64SVEPredPattern::vl16:
535return 16;
536case AArch64SVEPredPattern::vl32:
537return 32;
538case AArch64SVEPredPattern::vl64:
539return 64;
540case AArch64SVEPredPattern::vl128:
541return 128;
542case AArch64SVEPredPattern::vl256:
543return 256;
544 }
545}
546
547/// Return specific VL predicate pattern based on the number of elements.
548inline std::optional<unsigned>
549getSVEPredPatternFromNumElements(unsigned MinNumElts) {
550switch (MinNumElts) {
551default:
552return std::nullopt;
553case 1:
554case 2:
555case 3:
556case 4:
557case 5:
558case 6:
559case 7:
560case 8:
561return MinNumElts;
562case 16:
563return AArch64SVEPredPattern::vl16;
564case 32:
565return AArch64SVEPredPattern::vl32;
566case 64:
567return AArch64SVEPredPattern::vl64;
568case 128:
569return AArch64SVEPredPattern::vl128;
570case 256:
571return AArch64SVEPredPattern::vl256;
572 }
573}
574
575/// An enum to describe what types of loops we should attempt to tail-fold:
576/// Disabled: None
577/// Reductions: Loops containing reductions
578/// Recurrences: Loops with first-order recurrences, i.e. that would
579/// require a SVE splice instruction
580/// Reverse: Reverse loops
581/// Simple: Loops that are not reversed and don't contain reductions
582/// or first-order recurrences.
583/// All: All
584enum classTailFoldingOpts :uint8_t {
585Disabled = 0x00,
586Simple = 0x01,
587Reductions = 0x02,
588Recurrences = 0x04,
589Reverse = 0x08,
590All =Reductions |Recurrences |Simple |Reverse
591};
592
593LLVM_DECLARE_ENUM_AS_BITMASK(TailFoldingOpts,
594/* LargestValue */ (long)TailFoldingOpts::Reverse);
595
596namespaceAArch64ExactFPImm {
597structExactFPImm {
598intEnum;
599constchar *Repr;
600};
601#define GET_ExactFPImmValues_DECL
602#define GET_ExactFPImmsList_DECL
603#include "AArch64GenSystemOperands.inc"
604}
605
606namespaceAArch64PState {
607structPStateImm0_15 :SysAlias{
608usingSysAlias::SysAlias;
609 };
610#define GET_PStateImm0_15Values_DECL
611#define GET_PStateImm0_15sList_DECL
612#include "AArch64GenSystemOperands.inc"
613
614structPStateImm0_1 :SysAlias{
615usingSysAlias::SysAlias;
616 };
617#define GET_PStateImm0_1Values_DECL
618#define GET_PStateImm0_1sList_DECL
619#include "AArch64GenSystemOperands.inc"
620}
621
622namespaceAArch64PSBHint {
623structPSB :SysAlias {
624usingSysAlias::SysAlias;
625 };
626#define GET_PSBValues_DECL
627#define GET_PSBsList_DECL
628#include "AArch64GenSystemOperands.inc"
629}
630
631namespaceAArch64PHint {
632structPHint {
633constchar *Name;
634unsignedEncoding;
635FeatureBitsetFeaturesRequired;
636
637boolhaveFeatures(FeatureBitset ActiveFeatures) const{
638return ActiveFeatures[llvm::AArch64::FeatureAll] ||
639 (FeaturesRequired & ActiveFeatures) ==FeaturesRequired;
640 }
641};
642
643#define GET_PHintValues_DECL
644#define GET_PHintsList_DECL
645#include "AArch64GenSystemOperands.inc"
646
647constPHint *lookupPHintByName(StringRef);
648constPHint *lookupPHintByEncoding(uint16_t);
649}// namespace AArch64PHint
650
651namespaceAArch64BTIHint {
652structBTI :SysAlias {
653usingSysAlias::SysAlias;
654 };
655#define GET_BTIValues_DECL
656#define GET_BTIsList_DECL
657#include "AArch64GenSystemOperands.inc"
658}
659
660namespaceAArch64SME {
661enumToggleCondition :unsigned {
662Always,
663IfCallerIsStreaming,
664IfCallerIsNonStreaming
665};
666}
667
668namespaceAArch64SE {
669enumShiftExtSpecifiers {
670Invalid = -1,
671LSL,
672MSL,
673LSR,
674ASR,
675ROR,
676
677UXTB,
678UXTH,
679UXTW,
680UXTX,
681
682SXTB,
683SXTH,
684SXTW,
685SXTX
686 };
687}
688
689namespaceAArch64Layout {
690enumVectorLayout {
691Invalid = -1,
692VL_8B,
693VL_4H,
694VL_2S,
695VL_1D,
696
697VL_16B,
698VL_8H,
699VL_4S,
700VL_2D,
701
702// Bare layout for the 128-bit vector
703// (only show ".b", ".h", ".s", ".d" without vector number)
704VL_B,
705VL_H,
706VL_S,
707VL_D
708 };
709}
710
711inlinestaticconstchar *
712AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
713switch (Layout) {
714caseAArch64Layout::VL_8B:return".8b";
715caseAArch64Layout::VL_4H:return".4h";
716caseAArch64Layout::VL_2S:return".2s";
717caseAArch64Layout::VL_1D:return".1d";
718caseAArch64Layout::VL_16B:return".16b";
719caseAArch64Layout::VL_8H:return".8h";
720caseAArch64Layout::VL_4S:return".4s";
721caseAArch64Layout::VL_2D:return".2d";
722caseAArch64Layout::VL_B:return".b";
723caseAArch64Layout::VL_H:return".h";
724caseAArch64Layout::VL_S:return".s";
725caseAArch64Layout::VL_D:return".d";
726default:llvm_unreachable("Unknown Vector Layout");
727 }
728}
729
730inlinestaticAArch64Layout::VectorLayout
731AArch64StringToVectorLayout(StringRef LayoutStr) {
732returnStringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
733 .Case(".8b",AArch64Layout::VL_8B)
734 .Case(".4h",AArch64Layout::VL_4H)
735 .Case(".2s",AArch64Layout::VL_2S)
736 .Case(".1d",AArch64Layout::VL_1D)
737 .Case(".16b",AArch64Layout::VL_16B)
738 .Case(".8h",AArch64Layout::VL_8H)
739 .Case(".4s",AArch64Layout::VL_4S)
740 .Case(".2d",AArch64Layout::VL_2D)
741 .Case(".b",AArch64Layout::VL_B)
742 .Case(".h",AArch64Layout::VL_H)
743 .Case(".s",AArch64Layout::VL_S)
744 .Case(".d",AArch64Layout::VL_D)
745 .Default(AArch64Layout::Invalid);
746}
747
748namespaceAArch64SysReg {
749structSysReg {
750constcharName[32];
751unsignedEncoding;
752boolReadable;
753boolWriteable;
754FeatureBitsetFeaturesRequired;
755
756boolhaveFeatures(FeatureBitset ActiveFeatures) const{
757return ActiveFeatures[llvm::AArch64::FeatureAll] ||
758 (FeaturesRequired & ActiveFeatures) ==FeaturesRequired;
759 }
760 };
761
762#define GET_SysRegsList_DECL
763#define GET_SysRegValues_DECL
764#include "AArch64GenSystemOperands.inc"
765
766uint32_tparseGenericRegister(StringRefName);
767 std::stringgenericRegisterString(uint32_t Bits);
768}
769
770namespaceAArch64TLBI {
771structTLBI :SysAliasReg {
772usingSysAliasReg::SysAliasReg;
773 };
774 #define GET_TLBITable_DECL
775 #include "AArch64GenSystemOperands.inc"
776}
777
778namespaceAArch64II {
779/// Target Operand Flag enum.
780enumTOF {
781//===------------------------------------------------------------------===//
782// AArch64 Specific MachineOperand flags.
783
784MO_NO_FLAG,
785
786MO_FRAGMENT = 0x7,
787
788 /// MO_PAGE - A symbol operand with this flag represents the pc-relative
789 /// offset of the 4K page containing the symbol. This is used with the
790 /// ADRP instruction.
791MO_PAGE = 1,
792
793 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
794 /// that symbol within a 4K page. This offset is added to the page address
795 /// to produce the complete address.
796MO_PAGEOFF = 2,
797
798 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
799 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
800MO_G3 = 3,
801
802 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
803 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
804MO_G2 = 4,
805
806 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
807 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
808MO_G1 = 5,
809
810 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
811 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
812MO_G0 = 6,
813
814 /// MO_HI12 - This flag indicates that a symbol operand represents the bits
815 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
816 /// by-12-bits instruction.
817MO_HI12 = 7,
818
819 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
820 /// reference is actually to the ".refptr.FOO" symbol. This is used for
821 /// stub symbols on windows.
822MO_COFFSTUB = 0x8,
823
824 /// MO_GOT - This flag indicates that a symbol operand represents the
825 /// address of the GOT entry for the symbol, rather than the address of
826 /// the symbol itself.
827MO_GOT = 0x10,
828
829 /// MO_NC - Indicates whether the linker is expected to check the symbol
830 /// reference for overflow. For example in an ADRP/ADD pair of relocations
831 /// the ADRP usually does check, but not the ADD.
832MO_NC = 0x20,
833
834 /// MO_TLS - Indicates that the operand being accessed is some kind of
835 /// thread-local symbol. On Darwin, only one type of thread-local access
836 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
837 /// referee will affect interpretation.
838MO_TLS = 0x40,
839
840 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
841 /// to the symbol is for an import stub. This is used for DLL import
842 /// storage class indication on Windows.
843MO_DLLIMPORT = 0x80,
844
845 /// MO_S - Indicates that the bits of the symbol operand represented by
846 /// MO_G0 etc are signed.
847MO_S = 0x100,
848
849 /// MO_PREL - Indicates that the bits of the symbol operand represented by
850 /// MO_G0 etc are PC relative.
851MO_PREL = 0x200,
852
853 /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
854 /// in bits 56-63.
855 /// On a FrameIndex operand, indicates that the underlying memory is tagged
856 /// with an unknown tag value (MTE); this needs to be lowered either to an
857 /// SP-relative load or store instruction (which do not check tags), or to
858 /// an LDG instruction to obtain the tag value.
859MO_TAGGED = 0x400,
860
861 /// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version
862 /// of a symbol, not the original. For dllimport symbols, this means it
863 /// uses "__imp_aux". For other symbols, this means it uses the mangled
864 /// ("#" prefix for C) name.
865MO_ARM64EC_CALLMANGLE = 0x800,
866};
867}// end namespace AArch64II
868
869//===----------------------------------------------------------------------===//
870// v8.3a Pointer Authentication
871//
872
873namespaceAArch64PACKey {
874enumID :uint8_t {
875IA = 0,
876IB = 1,
877DA = 2,
878DB = 3,
879LAST =DB
880};
881}// namespace AArch64PACKey
882
883/// Return 2-letter identifier string for numeric key ID.
884inlinestaticStringRefAArch64PACKeyIDToString(AArch64PACKey::ID KeyID) {
885switch (KeyID) {
886caseAArch64PACKey::IA:
887returnStringRef("ia");
888caseAArch64PACKey::IB:
889returnStringRef("ib");
890caseAArch64PACKey::DA:
891returnStringRef("da");
892caseAArch64PACKey::DB:
893returnStringRef("db");
894 }
895llvm_unreachable("Unhandled AArch64PACKey::ID enum");
896}
897
898/// Return numeric key ID for 2-letter identifier string.
899inlinestatic std::optional<AArch64PACKey::ID>
900AArch64StringToPACKeyID(StringRefName) {
901if (Name =="ia")
902returnAArch64PACKey::IA;
903if (Name =="ib")
904returnAArch64PACKey::IB;
905if (Name =="da")
906returnAArch64PACKey::DA;
907if (Name =="db")
908returnAArch64PACKey::DB;
909return std::nullopt;
910}
911
912namespaceAArch64 {
913// The number of bits in a SVE register is architecturally defined
914// to be a multiple of this value. If <M x t> has this number of bits,
915// a <n x M x t> vector can be stored in a SVE register without any
916// redundant bits. If <M x t> has this number of bits divided by P,
917// a <n x M x t> vector is stored in a SVE register by placing index i
918// in index i*P of a <n x (M*P) x t> vector. The other elements of the
919// <n x (M*P) x t> vector (such as index 1) are undefined.
920staticconstexprunsignedSVEBitsPerBlock = 128;
921staticconstexprunsignedSVEMaxBitsPerVector = 2048;
922}// end namespace AArch64
923}// end namespace llvm
924
925#endif
AArch64MCTargetDesc.h
BitmaskEnum.h
LLVM_DECLARE_ENUM_AS_BITMASK
#define LLVM_DECLARE_ENUM_AS_BITMASK(Enum, LargestValue)
LLVM_DECLARE_ENUM_AS_BITMASK can be used to declare an enum type as a bit set, so that bitwise operat...
Definition:BitmaskEnum.h:66
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Name
std::string Name
Definition:ELFObjHandler.cpp:77
F
#define F(x, y, z)
Definition:MD5.cpp:55
I
#define I(x, y, z)
Definition:MD5.cpp:58
Reg
unsigned Reg
Definition:MachineSink.cpp:2028
CC
auto CC
Definition:RISCVRedundantCopyElimination.cpp:79
STLExtras.h
This file contains some templates that are useful if you are working with the STL at all.
StringSwitch.h
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
SubtargetFeature.h
llvm::FeatureBitset
Container class for subtarget features.
Definition:SubtargetFeature.h:41
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition:MCRegister.h:33
llvm::MCRegister::id
constexpr unsigned id() const
Definition:MCRegister.h:83
llvm::Pattern
Definition:FileCheckImpl.h:565
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition:StringRef.h:51
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition:StringSwitch.h:44
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition:StringSwitch.h:69
llvm::StringSwitch::Default
R Default(T Value)
Definition:StringSwitch.h:182
uint16_t
uint32_t
uint8_t
ErrorHandling.h
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition:ErrorHandling.h:143
llvm::AArch64CC::getSwappedCondition
static CondCode getSwappedCondition(CondCode CC)
getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the...
Definition:AArch64BaseInfo.h:312
llvm::AArch64CC::CondCode
CondCode
Definition:AArch64BaseInfo.h:254
llvm::AArch64CC::VC
@ VC
Definition:AArch64BaseInfo.h:262
llvm::AArch64CC::NONE_ACTIVE
@ NONE_ACTIVE
Definition:AArch64BaseInfo.h:278
llvm::AArch64CC::NE
@ NE
Definition:AArch64BaseInfo.h:256
llvm::AArch64CC::GE
@ GE
Definition:AArch64BaseInfo.h:265
llvm::AArch64CC::PL
@ PL
Definition:AArch64BaseInfo.h:260
llvm::AArch64CC::LAST_ACTIVE
@ LAST_ACTIVE
Definition:AArch64BaseInfo.h:277
llvm::AArch64CC::EQ
@ EQ
Definition:AArch64BaseInfo.h:255
llvm::AArch64CC::HS
@ HS
Definition:AArch64BaseInfo.h:257
llvm::AArch64CC::MI
@ MI
Definition:AArch64BaseInfo.h:259
llvm::AArch64CC::GT
@ GT
Definition:AArch64BaseInfo.h:267
llvm::AArch64CC::LT
@ LT
Definition:AArch64BaseInfo.h:266
llvm::AArch64CC::VS
@ VS
Definition:AArch64BaseInfo.h:261
llvm::AArch64CC::HI
@ HI
Definition:AArch64BaseInfo.h:263
llvm::AArch64CC::FIRST_ACTIVE
@ FIRST_ACTIVE
Definition:AArch64BaseInfo.h:276
llvm::AArch64CC::LO
@ LO
Definition:AArch64BaseInfo.h:258
llvm::AArch64CC::AL
@ AL
Definition:AArch64BaseInfo.h:269
llvm::AArch64CC::ANY_ACTIVE
@ ANY_ACTIVE
Definition:AArch64BaseInfo.h:275
llvm::AArch64CC::LE
@ LE
Definition:AArch64BaseInfo.h:268
llvm::AArch64CC::Invalid
@ Invalid
Definition:AArch64BaseInfo.h:272
llvm::AArch64CC::NV
@ NV
Definition:AArch64BaseInfo.h:270
llvm::AArch64CC::LS
@ LS
Definition:AArch64BaseInfo.h:264
llvm::AArch64CC::getCondCodeName
static const char * getCondCodeName(CondCode Code)
Definition:AArch64BaseInfo.h:281
llvm::AArch64CC::getInvertedCondCode
static CondCode getInvertedCondCode(CondCode Code)
Definition:AArch64BaseInfo.h:303
llvm::AArch64CC::getNZCVToSatisfyCondCode
static unsigned getNZCVToSatisfyCondCode(CondCode Code)
Given a condition code, return NZCV flags that would satisfy that condition.
Definition:AArch64BaseInfo.h:343
llvm::AArch64II::TOF
TOF
Target Operand Flag enum.
Definition:AArch64BaseInfo.h:780
llvm::AArch64II::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition:AArch64BaseInfo.h:843
llvm::AArch64II::MO_NC
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
Definition:AArch64BaseInfo.h:832
llvm::AArch64II::MO_G1
@ MO_G1
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address,...
Definition:AArch64BaseInfo.h:808
llvm::AArch64II::MO_S
@ MO_S
MO_S - Indicates that the bits of the symbol operand represented by MO_G0 etc are signed.
Definition:AArch64BaseInfo.h:847
llvm::AArch64II::MO_PAGEOFF
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
Definition:AArch64BaseInfo.h:796
llvm::AArch64II::MO_GOT
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
Definition:AArch64BaseInfo.h:827
llvm::AArch64II::MO_FRAGMENT
@ MO_FRAGMENT
Definition:AArch64BaseInfo.h:786
llvm::AArch64II::MO_NO_FLAG
@ MO_NO_FLAG
Definition:AArch64BaseInfo.h:784
llvm::AArch64II::MO_PREL
@ MO_PREL
MO_PREL - Indicates that the bits of the symbol operand represented by MO_G0 etc are PC relative.
Definition:AArch64BaseInfo.h:851
llvm::AArch64II::MO_G0
@ MO_G0
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address,...
Definition:AArch64BaseInfo.h:812
llvm::AArch64II::MO_ARM64EC_CALLMANGLE
@ MO_ARM64EC_CALLMANGLE
MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version of a symbol,...
Definition:AArch64BaseInfo.h:865
llvm::AArch64II::MO_PAGE
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
Definition:AArch64BaseInfo.h:791
llvm::AArch64II::MO_HI12
@ MO_HI12
MO_HI12 - This flag indicates that a symbol operand represents the bits 13-24 of a 64-bit address,...
Definition:AArch64BaseInfo.h:817
llvm::AArch64II::MO_TLS
@ MO_TLS
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
Definition:AArch64BaseInfo.h:838
llvm::AArch64II::MO_G2
@ MO_G2
MO_G2 - A symbol operand with this flag (granule 2) represents the bits 32-47 of a 64-bit address,...
Definition:AArch64BaseInfo.h:804
llvm::AArch64II::MO_TAGGED
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
Definition:AArch64BaseInfo.h:859
llvm::AArch64II::MO_G3
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
Definition:AArch64BaseInfo.h:800
llvm::AArch64II::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition:AArch64BaseInfo.h:822
llvm::AArch64Layout::VectorLayout
VectorLayout
Definition:AArch64BaseInfo.h:690
llvm::AArch64Layout::VL_1D
@ VL_1D
Definition:AArch64BaseInfo.h:695
llvm::AArch64Layout::VL_B
@ VL_B
Definition:AArch64BaseInfo.h:704
llvm::AArch64Layout::VL_8B
@ VL_8B
Definition:AArch64BaseInfo.h:692
llvm::AArch64Layout::VL_4S
@ VL_4S
Definition:AArch64BaseInfo.h:699
llvm::AArch64Layout::VL_2S
@ VL_2S
Definition:AArch64BaseInfo.h:694
llvm::AArch64Layout::VL_4H
@ VL_4H
Definition:AArch64BaseInfo.h:693
llvm::AArch64Layout::VL_16B
@ VL_16B
Definition:AArch64BaseInfo.h:697
llvm::AArch64Layout::VL_2D
@ VL_2D
Definition:AArch64BaseInfo.h:700
llvm::AArch64Layout::Invalid
@ Invalid
Definition:AArch64BaseInfo.h:691
llvm::AArch64Layout::VL_D
@ VL_D
Definition:AArch64BaseInfo.h:707
llvm::AArch64Layout::VL_S
@ VL_S
Definition:AArch64BaseInfo.h:706
llvm::AArch64Layout::VL_H
@ VL_H
Definition:AArch64BaseInfo.h:705
llvm::AArch64Layout::VL_8H
@ VL_8H
Definition:AArch64BaseInfo.h:698
llvm::AArch64PACKey::ID
ID
Definition:AArch64BaseInfo.h:874
llvm::AArch64PACKey::IB
@ IB
Definition:AArch64BaseInfo.h:876
llvm::AArch64PACKey::DA
@ DA
Definition:AArch64BaseInfo.h:877
llvm::AArch64PACKey::LAST
@ LAST
Definition:AArch64BaseInfo.h:879
llvm::AArch64PACKey::DB
@ DB
Definition:AArch64BaseInfo.h:878
llvm::AArch64PACKey::IA
@ IA
Definition:AArch64BaseInfo.h:875
llvm::AArch64PHint::lookupPHintByName
const PHint * lookupPHintByName(StringRef)
llvm::AArch64PHint::lookupPHintByEncoding
const PHint * lookupPHintByEncoding(uint16_t)
llvm::AArch64SE::ShiftExtSpecifiers
ShiftExtSpecifiers
Definition:AArch64BaseInfo.h:669
llvm::AArch64SE::UXTB
@ UXTB
Definition:AArch64BaseInfo.h:677
llvm::AArch64SE::SXTH
@ SXTH
Definition:AArch64BaseInfo.h:683
llvm::AArch64SE::UXTH
@ UXTH
Definition:AArch64BaseInfo.h:678
llvm::AArch64SE::MSL
@ MSL
Definition:AArch64BaseInfo.h:672
llvm::AArch64SE::SXTW
@ SXTW
Definition:AArch64BaseInfo.h:684
llvm::AArch64SE::UXTX
@ UXTX
Definition:AArch64BaseInfo.h:680
llvm::AArch64SE::LSL
@ LSL
Definition:AArch64BaseInfo.h:671
llvm::AArch64SE::ROR
@ ROR
Definition:AArch64BaseInfo.h:675
llvm::AArch64SE::SXTB
@ SXTB
Definition:AArch64BaseInfo.h:682
llvm::AArch64SE::LSR
@ LSR
Definition:AArch64BaseInfo.h:673
llvm::AArch64SE::SXTX
@ SXTX
Definition:AArch64BaseInfo.h:685
llvm::AArch64SE::Invalid
@ Invalid
Definition:AArch64BaseInfo.h:670
llvm::AArch64SE::ASR
@ ASR
Definition:AArch64BaseInfo.h:674
llvm::AArch64SE::UXTW
@ UXTW
Definition:AArch64BaseInfo.h:679
llvm::AArch64SME::ToggleCondition
ToggleCondition
Definition:AArch64BaseInfo.h:661
llvm::AArch64SME::Always
@ Always
Definition:AArch64BaseInfo.h:662
llvm::AArch64SME::IfCallerIsNonStreaming
@ IfCallerIsNonStreaming
Definition:AArch64BaseInfo.h:664
llvm::AArch64SME::IfCallerIsStreaming
@ IfCallerIsStreaming
Definition:AArch64BaseInfo.h:663
llvm::AArch64SysReg::parseGenericRegister
uint32_t parseGenericRegister(StringRef Name)
Definition:AArch64BaseInfo.cpp:148
llvm::AArch64SysReg::genericRegisterString
std::string genericRegisterString(uint32_t Bits)
Definition:AArch64BaseInfo.cpp:169
llvm::AArch64::SVEMaxBitsPerVector
static constexpr unsigned SVEMaxBitsPerVector
Definition:AArch64BaseInfo.h:921
llvm::AArch64::SVEBitsPerBlock
static constexpr unsigned SVEBitsPerBlock
Definition:AArch64BaseInfo.h:920
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition:CallingConv.h:34
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:AddressRanges.h:18
llvm::AArch64StringToPACKeyID
static std::optional< AArch64PACKey::ID > AArch64StringToPACKeyID(StringRef Name)
Return numeric key ID for 2-letter identifier string.
Definition:AArch64BaseInfo.h:900
llvm::TailFoldingOpts
TailFoldingOpts
An enum to describe what types of loops we should attempt to tail-fold: Disabled: None Reductions: Lo...
Definition:AArch64BaseInfo.h:584
llvm::TailFoldingOpts::Simple
@ Simple
llvm::TailFoldingOpts::Reverse
@ Reverse
llvm::TailFoldingOpts::Reductions
@ Reductions
llvm::TailFoldingOpts::Disabled
@ Disabled
llvm::TailFoldingOpts::Recurrences
@ Recurrences
llvm::AArch64StringToVectorLayout
static AArch64Layout::VectorLayout AArch64StringToVectorLayout(StringRef LayoutStr)
Definition:AArch64BaseInfo.h:731
llvm::AllocationType::All
@ All
llvm::AArch64VectorLayoutToString
static const char * AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)
Definition:AArch64BaseInfo.h:712
llvm::getSVEPredPatternFromNumElements
std::optional< unsigned > getSVEPredPatternFromNumElements(unsigned MinNumElts)
Return specific VL predicate pattern based on the number of elements.
Definition:AArch64BaseInfo.h:549
llvm::atomicBarrierDroppedOnZero
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
Definition:AArch64BaseInfo.h:207
llvm::getXRegFromWReg
static MCRegister getXRegFromWReg(MCRegister Reg)
Definition:AArch64BaseInfo.h:70
llvm::getXRegFromXRegTuple
static MCRegister getXRegFromXRegTuple(MCRegister RegTuple)
Definition:AArch64BaseInfo.h:110
llvm::getWRegFromXReg
static MCRegister getWRegFromXReg(MCRegister Reg)
Definition:AArch64BaseInfo.h:30
llvm::getNumElementsFromSVEPredPattern
unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
Return the number of active elements for VL1 to VL256 predicate pattern, zero for all other patterns.
Definition:AArch64BaseInfo.h:521
llvm::getDRegFromBReg
static MCRegister getDRegFromBReg(MCRegister Reg)
Definition:AArch64BaseInfo.h:168
llvm::getBRegFromDReg
static MCRegister getBRegFromDReg(MCRegister Reg)
Definition:AArch64BaseInfo.h:129
llvm::AArch64PACKeyIDToString
static StringRef AArch64PACKeyIDToString(AArch64PACKey::ID KeyID)
Return 2-letter identifier string for numeric key ID.
Definition:AArch64BaseInfo.h:884
N
#define N
llvm::AArch64AT::AT
Definition:AArch64BaseInfo.h:410
llvm::AArch64BTIHint::BTI
Definition:AArch64BaseInfo.h:652
llvm::AArch64DB::DB
Definition:AArch64BaseInfo.h:419
llvm::AArch64DBnXS::DBnXS
Definition:AArch64BaseInfo.h:428
llvm::AArch64DC::DC
Definition:AArch64BaseInfo.h:437
llvm::AArch64ExactFPImm::ExactFPImm
Definition:AArch64BaseInfo.h:597
llvm::AArch64ExactFPImm::ExactFPImm::Enum
int Enum
Definition:AArch64BaseInfo.h:598
llvm::AArch64ExactFPImm::ExactFPImm::Repr
const char * Repr
Definition:AArch64BaseInfo.h:599
llvm::AArch64IC::IC
Definition:AArch64BaseInfo.h:446
llvm::AArch64ISB::ISB
Definition:AArch64BaseInfo.h:455
llvm::AArch64PHint::PHint
Definition:AArch64BaseInfo.h:632
llvm::AArch64PHint::PHint::Name
const char * Name
Definition:AArch64BaseInfo.h:633
llvm::AArch64PHint::PHint::haveFeatures
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition:AArch64BaseInfo.h:637
llvm::AArch64PHint::PHint::Encoding
unsigned Encoding
Definition:AArch64BaseInfo.h:634
llvm::AArch64PHint::PHint::FeaturesRequired
FeatureBitset FeaturesRequired
Definition:AArch64BaseInfo.h:635
llvm::AArch64PRFM::PRFM
Definition:AArch64BaseInfo.h:473
llvm::AArch64PSBHint::PSB
Definition:AArch64BaseInfo.h:623
llvm::AArch64PState::PStateImm0_15
Definition:AArch64BaseInfo.h:607
llvm::AArch64PState::PStateImm0_1
Definition:AArch64BaseInfo.h:614
llvm::AArch64RPRFM::RPRFM
Definition:AArch64BaseInfo.h:491
llvm::AArch64SVCR::SVCR
Definition:AArch64BaseInfo.h:401
llvm::AArch64SVEPRFM::SVEPRFM
Definition:AArch64BaseInfo.h:482
llvm::AArch64SVEPredPattern::SVEPREDPAT
Definition:AArch64BaseInfo.h:500
llvm::AArch64SVEPredPattern::SVEPREDPAT::Encoding
uint16_t Encoding
Definition:AArch64BaseInfo.h:502
llvm::AArch64SVEPredPattern::SVEPREDPAT::Name
const char * Name
Definition:AArch64BaseInfo.h:501
llvm::AArch64SVEVecLenSpecifier::SVEVECLENSPECIFIER
Definition:AArch64BaseInfo.h:510
llvm::AArch64SVEVecLenSpecifier::SVEVECLENSPECIFIER::Name
const char * Name
Definition:AArch64BaseInfo.h:511
llvm::AArch64SVEVecLenSpecifier::SVEVECLENSPECIFIER::Encoding
uint16_t Encoding
Definition:AArch64BaseInfo.h:512
llvm::AArch64SysReg::SysReg
Definition:AArch64BaseInfo.h:749
llvm::AArch64SysReg::SysReg::FeaturesRequired
FeatureBitset FeaturesRequired
Definition:AArch64BaseInfo.h:754
llvm::AArch64SysReg::SysReg::Encoding
unsigned Encoding
Definition:AArch64BaseInfo.h:751
llvm::AArch64SysReg::SysReg::Writeable
bool Writeable
Definition:AArch64BaseInfo.h:753
llvm::AArch64SysReg::SysReg::Readable
bool Readable
Definition:AArch64BaseInfo.h:752
llvm::AArch64SysReg::SysReg::haveFeatures
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition:AArch64BaseInfo.h:756
llvm::AArch64SysReg::SysReg::Name
const char Name[32]
Definition:AArch64BaseInfo.h:750
llvm::AArch64TLBI::TLBI
Definition:AArch64BaseInfo.h:771
llvm::AArch64TSB::TSB
Definition:AArch64BaseInfo.h:464
llvm::SysAliasImm
Definition:AArch64BaseInfo.h:392
llvm::SysAliasImm::SysAliasImm
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
Definition:AArch64BaseInfo.h:394
llvm::SysAliasImm::SysAliasImm
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
Definition:AArch64BaseInfo.h:396
llvm::SysAliasImm::ImmValue
uint16_t ImmValue
Definition:AArch64BaseInfo.h:393
llvm::SysAliasReg
Definition:AArch64BaseInfo.h:384
llvm::SysAliasReg::SysAliasReg
constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
Definition:AArch64BaseInfo.h:388
llvm::SysAliasReg::SysAliasReg
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
Definition:AArch64BaseInfo.h:386
llvm::SysAliasReg::NeedsReg
bool NeedsReg
Definition:AArch64BaseInfo.h:385
llvm::SysAlias
Definition:AArch64BaseInfo.h:367
llvm::SysAlias::haveFeatures
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition:AArch64BaseInfo.h:376
llvm::SysAlias::SysAlias
constexpr SysAlias(const char *N, uint16_t E)
Definition:AArch64BaseInfo.h:372
llvm::SysAlias::getRequiredFeatures
FeatureBitset getRequiredFeatures() const
Definition:AArch64BaseInfo.h:381
llvm::SysAlias::Name
const char * Name
Definition:AArch64BaseInfo.h:368
llvm::SysAlias::FeaturesRequired
FeatureBitset FeaturesRequired
Definition:AArch64BaseInfo.h:370
llvm::SysAlias::SysAlias
constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
Definition:AArch64BaseInfo.h:373
llvm::SysAlias::Encoding
uint16_t Encoding
Definition:AArch64BaseInfo.h:369

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