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Chisel RISC-V Vector 1.0 Implementation
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ucb-bar/saturn-vectors
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Microarchitectural manualhere.
This repository contains the Chisel source RTL for the Saturn Vector Unit, a parameterized RVV 1.0 vector unit.Saturn supports the entire RVV 1.0 application-profile specification, including
V-extension (Full application-profile V)Zve64d- supports FP64,ELEN=64Zvfh- supports FP16Zvbb- support basic vector bit manipulationZvl64/128/256/512/1024- configurableVLEN- Indexed/strided/segmented loads and stores
- Virtual memory with precise traps
- Full chaining with zero dead-time
- Configurable SIMD datapath width (64/128/256/512+)
This repository cannot be used stand-alone.Saturn is intended to be used to generate vector-enabled RISC-V cores and SoCs through theChipyard SoC design framework.
@techreport{Zhao:EECS-2024-215, Author = {Zhao, Jerry and Grubb, Daniel and Rusch, Miles and Wei, Tianrui and Anderson, Kevin and Nikolic, Borivoje and Asanović, Krste}, Title = {The Saturn Microarchitecture Manual}, Institution = {EECS Department, University of California, Berkeley}, Year = {2024}, Month = {Dec}, URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2024/EECS-2024-215.html}, Number = {UCB/EECS-2024-215}}