An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A Heterogeneous GPU Platform for Chipyard SoC

Software kernels for the Radiance GPU

Hammer: Highly Agile Masks Made Effortlessly from RTL

Chisel RISC-V Vector 1.0 Implementation

Generating Schedules for Robotic Workloads

Autocomp: AI-Driven Code Optimizer for Tensor Accelerators

Berkeley's Spatial Array Generator

On-device AI across mobile, embedded and edge for PyTorch