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#

yosys

Here are 166 public repositories matching this topic...

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  • UpdatedSep 15, 2025
  • Python

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

  • UpdatedJul 24, 2025
  • C

draws an SVG schematic from a JSON netlist

  • UpdatedJan 25, 2024
  • JavaScript

SystemVerilog to Verilog conversion

  • UpdatedNov 24, 2025
  • Haskell

A refreshed Python toolbox for building complex digital hardware. Seehttps://gitlab.com/nmigen/nmigen

  • UpdatedJan 8, 2022
  • Python

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

  • UpdatedFeb 26, 2025
  • Verilog

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

  • UpdatedNov 18, 2025
  • SystemVerilog

A Python package to use FPGA development tools programmatically.

  • UpdatedMar 22, 2025
  • Python

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

  • UpdatedFeb 22, 2022
  • Verilog

Examples for the Lushay Labs tang nano 9k series

  • UpdatedJun 12, 2024
  • GLSL

Physical Design Flow from RTL to GDS using Opensource tools.

  • UpdatedNov 23, 2020

A VHDL frontend for Yosys

  • UpdatedFeb 27, 2017
  • C++
fpga-tool-perf

Arduino compatible – Cortex M4F & FPGA Development Board

  • UpdatedMar 22, 2019

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

  • UpdatedDec 15, 2025
  • VHDL
yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

  • UpdatedMay 14, 2024
  • Verilog

RealtimeIO for LinuxCNC based on an FPGA

  • UpdatedSep 2, 2024
  • Python

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