yosys
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OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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Sep 15, 2025 - Python
An abstraction library for interfacing EDA tools
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Nov 17, 2025 - Python
A refreshed Python toolbox for building complex digital hardware. Seehttps://gitlab.com/nmigen/nmigen
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Jan 8, 2022 - Python
A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.
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Nov 18, 2025 - SystemVerilog
Examples for the Lushay Labs tang nano 9k series
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Jun 12, 2024 - GLSL
Physical Design Flow from RTL to GDS using Opensource tools.
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Nov 23, 2020
FPGA tool performance profiling
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Feb 24, 2024 - Python
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May 16, 2023 - Python
XCrypto: a cryptographic ISE for RISC-V
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Jan 5, 2023 - Verilog
Plugins for Yosys developed as part of the F4PGA project.
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May 14, 2024 - Verilog
RealtimeIO for LinuxCNC based on an FPGA
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Sep 2, 2024 - Python
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