vlsi-physical-design
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Deep learning toolkit-enabled VLSI placement
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Dec 14, 2025 - C++
A High-performance Timing Analysis Tool for VLSI Systems
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Dec 16, 2025 - Verilog
Standard Cell Library based Memory Compiler using FF/Latch cells
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Nov 10, 2025 - Verilog
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
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Mar 20, 2023 - C++
A Standalone Structural Verilog Parser
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Mar 31, 2022 - Verilog
VLSI EDA Global Router
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Jan 22, 2018 - C++
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
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Sep 17, 2022
Steiner Shallow-Light Tree for VLSI Routing
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Jul 11, 2024 - C++
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
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Aug 7, 2022 - C++
This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisa…
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Jul 9, 2021 - Verilog
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
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Jan 23, 2021 - C++
This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
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Feb 22, 2022
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
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May 20, 2020 - Verilog
Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference
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Dec 30, 2022 - Tcl
A LEF/DEF Utility.
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Aug 15, 2019 - Prolog
Some simple examples for the Magic VLSI physical chip layout tool.
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Mar 9, 2021
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
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Jan 23, 2024 - Verilog
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Feb 22, 2024 - Verilog
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