Library for VLSI CAD Design Useful parsers and solvers' api are implemented.

• UpdatedMay 19, 2025
• C++

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

• UpdatedDec 17, 2025
• SystemVerilog

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

• UpdatedJul 9, 2023
• Verilog

微电子和集成电路自学指南

• UpdatedDec 15, 2025

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

• UpdatedJan 23, 2021
• C++

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

• UpdatedJun 6, 2024
• Verilog

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

• UpdatedMar 22, 2019

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

• UpdatedMay 20, 2020
• Verilog

Microshift Compression: An Efficient Image Compression Algorithm for Hardware

• UpdatedApr 21, 2021
• Verilog

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

• UpdatedJul 21, 2025
• C

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

• UpdatedDec 9, 2018
• Jupyter Notebook

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

• UpdatedJan 23, 2024
• Verilog

Gatery, a library for circuit design.

• UpdatedDec 9, 2024
• C++

Spiking Neural Network Accelerator

• UpdatedMay 18, 2022
• SystemVerilog

Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)

• UpdatedDec 12, 2025
• Python

Contains all the necessary lab tasks (Cadence Virtuoso) for ECE3002 VLSI System Design (VIT).

• UpdatedAug 28, 2025

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

• UpdatedFeb 13, 2020
• C++

32-bit RISC-V microcontroller

• UpdatedSep 11, 2021
• C

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

• UpdatedSep 13, 2025
• SystemVerilog

The Repository contains the code of various Digital Circuits

• UpdatedAug 7, 2023
• Verilog