A High-performance Timing Analysis Tool for VLSI Systems

• UpdatedDec 16, 2025
• Verilog

Standard Cell Library based Memory Compiler using FF/Latch cells

• UpdatedNov 10, 2025
• Verilog

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

• UpdatedApr 23, 2023
• C++

A Standalone Structural Verilog Parser

• UpdatedMar 31, 2022
• Verilog

VLSI EDA Global Router

• UpdatedJan 22, 2018
• C++

Library of approximate arithmetic circuits

• UpdatedSep 8, 2022
• Verilog

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

• UpdatedAug 7, 2022
• C++

Electrical And Electronic Engineering Course Materials

• UpdatedMar 22, 2022
• MATLAB

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

• UpdatedMar 22, 2019

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

• UpdatedDec 9, 2018
• Jupyter Notebook

All the projects and assignments done as part of VLSI course.

• UpdatedSep 23, 2020
• Verilog

genetic algorithm usage for routing optimization ( pyqt )

• UpdatedMar 24, 2019
• Python

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

• UpdatedFeb 13, 2020
• C++

This paper presents an intelligent sizing method to improve the performance and efficiency of a CMOS Ring Oscillator (RO). The proposed approach is based on the simultaneous utilization of powerful and new multi-objective optimization techniques along with a circuit simulator under a data link. The proposed optimizing tool creates a perfect trad…

• UpdatedApr 2, 2021

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier

• UpdatedJun 1, 2021
• Verilog

VLSI Design, Magic, OpenCircuitDesign,CMOS VLSI Design, CMOS Inverter Magic

• UpdatedAug 7, 2020

VLSI Physical Design

• UpdatedJun 14, 2018

Some ramblings about my major. 一些有关我的专业的碎碎念

• UpdatedDec 15, 2025
• Shell

delay estimation, sequencing, power dissipation of digital circuits

• UpdatedMay 28, 2023
• Batchfile

Designed and simulated all fundamental and universal CMOS logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) using the Electric VLSI Design Tool. This project includes schematic design, DRC-clean layouts, ALS simulation, and waveform analysis.

• UpdatedMay 10, 2025