vivado-simulator

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

systemverilog hardware-designs verilator axi4-lite axi4-protocol vivado-simulator axi4-lite-interface

UpdatedMay 4, 2024
SystemVerilog

RipperJ /VerilogExpr2NAND-NOR

Star3

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

compiler simulation lex espresso ply verilog yacc boolean-expression nand logic-minimization nor xsim vivado-simulator pyeda

UpdatedJun 4, 2023
Python

Ammar-Bin-Amir /SystemVerilog_Practice

Star1

Practice Codes of SystemVerilog Language

vscode systemverilog vivado-simulator

UpdatedMay 19, 2024
SystemVerilog

amirah-sri /all_verilog

Star1

I am trying to develop my skills through daily practice and consistency.

verilog vivado vlsi verilog-hdl verilog-programs verilog-project verilog-code vivado-simulator

UpdatedJul 31, 2024
Verilog

bp0609 /Mini-Processor-Verilog-FPGA-Implemented

Star0

This repo contains a mini-processor design implemented on FPGA using verilog

verilog fpga-board vivado-simulator

UpdatedMay 27, 2024
Verilog

anr2311 /I2C_State_Machine

Star0

This repo contains an I2C transaction state machine modelled in Verilog targeted for the Zynq Zedboard

i2c-bus vivado-simulator

UpdatedNov 23, 2024
Verilog

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

simulation rtl verilog vivado uart systemverilog uart-verilog fpga-soc testbench verilog-hdl fpga-board vivado-hls nexys4ddr verilog-project uart-transmitter uart-receiver fpga-programming vivado-simulator

UpdatedFeb 28, 2025
SystemVerilog

rishz09 /digital-safe-verilog

Star0

A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board

verilog vivado digital-design verilog-project pynq-z2 vivado-simulator digital-safe

UpdatedJul 1, 2024
Tcl

WimukthiMadushan /Computer-Organization-and-Digital-Design

Star0

Includes lab exercises from my Computer Organization and Digital Design module. It features implementations of various components inside a processor using VHDL . Finally I make 4 bit nanoprocessor combining all components those build in previous labs.

vhdl vivado vhdl-code vivado-simulator nanoprocessor

UpdatedJan 25, 2024
VHDL

TahirZia-1 /Digital-Clock-Verilog

Star0

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.

fpga simulation verilog synthesis vivado systemverilog fpga-soc verilog-hdl 7segment systemverilog-hdl digitalclock nexys4ddr fpga-programming vivado-simulator