Verilator open-source SystemVerilog simulator and lint system

• UpdatedJul 18, 2025
• C++

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

• UpdatedJul 18, 2025
• Jupyter Notebook

5-stage pipelined 32-bit MIPS microprocessor in Verilog

• UpdatedApr 3, 2020
• Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

• UpdatedJul 18, 2020
• JavaScript

A place to keep my synthesizable verilog examples.

• UpdatedApr 20, 2025
• Verilog

Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.

• UpdatedApr 25, 2019
• Verilog

Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).

• UpdatedMar 5, 2020
• Makefile

Verilog HDL Parser

• UpdatedJun 14, 2021
• ANTLR

A playground based on the classic version of the Cloud V IDE

• UpdatedMar 23, 2021
• JavaScript

Digital System Design Verilog Implementation

• UpdatedFeb 26, 2022
• Verilog

32-bits MIPS Processor with 5-stage pipeline

• UpdatedMay 16, 2021
• Verilog

Computer Architecture Lab Course 2022/1400, Fall CSE & IT Dept., Shiraz University

• UpdatedFeb 4, 2022
• Verilog

"Repository containing a collection of Verilog code modules and test bench for digital design projects. "

• UpdatedApr 1, 2024
• Verilog

This Repository shows the implementation and results of various codes that I write in Verilog HDL

• UpdatedMay 17, 2024
• Verilog

A verilog program that mimics the circuitry of a 4-bit register implemented with four 4x1 multiplexers and four D-Flipflops

• UpdatedOct 30, 2021
• Verilog

32-bit MIPS processor fully supporting all core instructions

• UpdatedJan 12, 2018
• Verilog