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verilog-simulator

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All18 Verilog10 JavaScript3 ANTLR1 Jupyter Notebook1 Makefile1 SystemVerilog1 Zig1

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verilator

verilator /verilator

Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator

UpdatedDec 18, 2025
SystemVerilog

f4pga-arch-defs

f4pga /f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

python toolchain documentation fpga sphinx primitives verilog synthesis lattice hdl xilinx-fpga ice40 artix7 artix vpr kintex7 architecture-definitions verilog-simulator symbiflow verilog-simulations

UpdatedDec 16, 2025
Jupyter Notebook

neelkshah /MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

verilog microprocessor computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project

UpdatedApr 3, 2020
Verilog

JeffDeCola /my-verilog-examples

A place to keep my synthesizable verilog examples.

simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

UpdatedApr 20, 2025
Verilog

Arjun-Narula /Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

UpdatedJul 18, 2020
JavaScript

mateuspinto /FPGA_Verilog_Ballot_Box-TP2-ISL-UFV

Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.

fpga verilog verilog-hdl fpga-firmware altera-fpga verilog-simulator verilog-project altera-de2

UpdatedApr 25, 2019
Verilog

vb000 /vcs-slave-mode

Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).

verilog-simulator shared-object synopsys-vcs

UpdatedMar 5, 2020
Makefile

cw1997 /verilog-parser

Verilog HDL Parser

parser verilog parsers verilog-hdl verilog-simulator

UpdatedJun 14, 2021
ANTLR

AUCOHL /Classic-Playground

A playground based on the classic version of the Cloud V IDE

eda verilog verilog-hdl verilog-simulator online-ide

UpdatedMar 23, 2021
JavaScript

ShiV-0312 /MIPS_PROCESSOR

32-bits MIPS Processor with 5-stage pipeline

mips verilog mips-processor mips32 verilog-simulator verilog-project verilog-code

UpdatedMay 16, 2021
Verilog

galihru /logicsim

The Logic Simulator is an advanced tool designed to facilitate the understanding of sequential circuit design. This application implements fundamental concepts of computer architecture and digital systems engineering through an intuitive drag-and-drop interface, providin

logic-gates verilog-hdl pwa-apps verilog-simulator logic-simulator verilog-project

UpdatedAug 5, 2025
JavaScript

wasifijaz /Digital-System-Design-Verilog-Implementation

Digital System Design Verilog Implementation

verilog logic-gates fifo lifo adders verilog-simulator subtractor verilog-code digital-system-design

UpdatedFeb 26, 2022
Verilog

thuvasooriya /verilator

build verilator with zig

cpp zig rtl verilog compilers systemc system-verilog verilator verilog-simulator zig-package

UpdatedOct 11, 2025
Zig

jElhamm /Verilog-HDL-Codes-Collection

"Repository containing a collection of Verilog code modules and test bench for digital design projects. "

counter encoder decoder verilog alu multiplexer comparator testbench verilog-hdl gates 7segment shiftregister verilog-programs verilog-simulator verilog-project testbench-generator-verilog

UpdatedApr 1, 2024
Verilog

ali-asnaashari /Computer_Architecture_Lab

Computer Architecture Lab Course 2022/1400, Fall CSE & IT Dept., Shiraz University

architecture verilog mips-architecture architecture-lab verilog-simulator

UpdatedFeb 4, 2022
Verilog

Bhargav-962 /4-bit_Register-Verilog

A verilog program that mimics the circuitry of a 4-bit register implemented with four 4x1 multiplexers and four D-Flipflops

verilog-simulator

UpdatedOct 30, 2021
Verilog

Rudra-Joshi-002 /Verilog_Codes

This Repository shows the implementation and results of various codes that I write in Verilog HDL

verilog verilog-hdl verilog-programs verilog-simulator verilog-project verilog-code

UpdatedMay 17, 2024
Verilog

gokcedemir /Mips-processor

32-bit MIPS processor fully supporting all core instructions

32-bits mips-processor verilog-simulator

UpdatedJan 12, 2018
Verilog

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