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snbk001 /Verilog-Design-Examples

Star113

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…

verilog testbenches verilog-hdl verilog-programs verilog-project verilog-code verilog-design self-checking

UpdatedJan 29, 2024
Verilog

TheSUPERCD /8bit_MicroComputer_Verilog

Sponsor

Star53

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

verilog verilog-hdl 8bit iverilog verilog-project ben-eater verilog-code ben-eaters-cpu

UpdatedNov 30, 2022
Verilog

benitoss /UnAmiga

Star51

Implementation of Amiga 500/1200 in Altera Cyclone IV FPGA

verilog-code

UpdatedJun 4, 2019
VHDL

Arjun-Narula /Traffic-Light-Controller-using-Verilog

Star41

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

UpdatedJul 18, 2020
JavaScript

mihir8181 /VerilogHDL-Codes

Star34

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

counter fsm asynchronous verilog fifo testbenches verilog-hdl verilog-programs mealy-machine-code moore-machine-code verilog-project fifo-buffer verilog-code n-bit-alu verilogvalidation design-under-test asynchronous-fifo fifo-verilog

UpdatedMay 10, 2019
Verilog

aklsh /getting-started-with-verilog

Star26

Verilog modules for beginners

open-source verilog verilog-hdl verilog-snippets verilog-code

UpdatedMay 27, 2022
Verilog

geraked /verilog-rle

Star24

Verilog Implementation of Run Length Encoding for RGB Image Compression

fpga matlab rle image-processing computer-engineering verilog xilinx run-length-encoding image-compression ise student-project compression-algorithm verilog-hdl xilinx-fpga rle-compression-algorithm fpga-programming verilog-code geraked rabist yazd-university

UpdatedJun 28, 2021
Verilog

aut-ce /CE202-LC-Lab-Manual

Star17

Manual and Template Sources of Logic Circuit Laboratory (Verilog Templates)

homework-assignments verilog-code logic-circuit-laboratory

UpdatedJan 9, 2025
C

aditeyabaral /DDCO-Lab-UE18CS207

Star16

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

verilog logic-programming icarus-verilog digital-design computer-organization verilog-code

UpdatedApr 17, 2020
Verilog

djzenma /RV32IC-CPU

Star15

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

cpu verilog risc hdl pipeline-processor verilog-hdl risc-v rv32i verilog-snippets pipeline-cpu risc-processor riscv32 riscv-simulator rv32imc verilog-code riscv32im

UpdatedMay 29, 2020
Verilog

jge162 /verilog_compiler

Sponsor

Star14

Verilog_Compiler is now available in GitHub Marketplace! This tool can quickly compile Verilog code and check for errors, making it an essential tool for developers.

fast compiler verilog verilog-hdl github-action verilog-code verilog-compiler verilog-scanner