Verilog

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Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

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logisim-evolution /logisim-evolution

Star6.3k

Digital logic design tool and simulator

education simulator fpga vhdl logic circuits verilog circuit digital-logic logisim digital-circuit digital-circuits timing-diagram digital-logic-design logisim-evolution

UpdatedOct 7, 2025
Java

LeiWang1999 /FPGA

Star5k

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga verilog xilinx vivado pynq

UpdatedMay 15, 2022

chipsalliance /chisel

Star4.4k

Chisel: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

UpdatedOct 8, 2025
Scala

open-sdr /openwifi

Star4.4k

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

linux fpga zynq hls hardware wifi verilog xilinx sdr analog-devices ieee80211 xilinx-fpga dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi

UpdatedSep 23, 2025
C

verilator /verilator

Star3.1k

Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator

UpdatedOct 8, 2025
C++

SpinalHDL /VexRiscv

Star2.9k

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore

UpdatedJul 4, 2025
Assembly

SI-RISCV /e200_opensource

Star2.8k

Deprecated, please go to next generation Ultra-Low Power RISC-V Corehttps://github.com/riscv-mcu/e203_hbirdv2

cpu core verilog china nuclei risc-v ultra-low-power

UpdatedMar 24, 2021
Verilog

darklife /darkriscv

Star2.4k

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

fpga core riscv verilog risc-v

UpdatedJul 16, 2025
Verilog

The-OpenROAD-Project /OpenROAD

Star2.2k

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation athttps://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

UpdatedOct 8, 2025
Verilog

jbush001 /NyuziProcessor

Star2.1k

GPGPU microprocessor architecture

processor-architecture fpga hardware gpu graphics verilog microprocessor gpu-computing

UpdatedNov 8, 2024
C

cocotb /cocotb

Star2.1k

cocotb: Python-based chip (RTL) verification

python test vhdl verification verilog uvm

UpdatedOct 6, 2025
Python

SpinalHDL /SpinalHDL

Star1.9k

Scala based HDL

scala fpga vhdl rtl verilog

UpdatedOct 7, 2025
Scala

pConst /basic_verilog

Star1.8k

Must-have verilog systemverilog modules

spi-interface fpga hls encoder delay tcl verilog debounce xilinx synchronizer uart altera uart-verilog fifo pwm uart-protocol spi-master uart-controller uart-tx uart-receiver

UpdatedAug 2, 2025
Verilog

FPGAwars /icestudio

Star1.8k

❄️ Visual editor for open FPGA boards

javascript editor fpga ide blocks verilog icestorm lattice icestudio

UpdatedAug 19, 2025
JavaScript

analogdevicesinc /hdl

Star1.8k

HDL libraries and projects

fpga verilog hdl hacktoberfest analog-devices jesd204b

UpdatedOct 7, 2025
Verilog

olofk /serv

Star1.7k

SERV - The SErial RISC-V CPU

asic fpga verilog risc-v

UpdatedSep 25, 2025
Verilog

riscv-mcu /e203_hbirdv2

Star1.6k

The Ultra-Low Power RISC-V Core

cpu fpga core riscv verilog china hummingbird nuclei soc risc-v low-power e203

UpdatedAug 6, 2025
Verilog

The-OpenROAD-Project /OpenLane

Star1.6k

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds