verilator

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

embedded fpga iss vpn rtl verilog risc-v wireguard verilator cocotb vproc

UpdatedDec 17, 2025
Verilog

ultraembedded /biriscv

Sponsor

Star1.2k

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

UpdatedSep 18, 2021
Verilog

chipsalliance /Cores-VeeR-EH1

Star914

VeeR EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer

UpdatedMay 29, 2023
SystemVerilog

ultraembedded /cores

Sponsor

Star852

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

UpdatedJul 1, 2021
Verilog

olofk /edalize

Star731

An abstraction library for interfacing EDA tools

fpga simulation vhdl eda verilog xilinx synthesis vivado altera systemverilog icestorm lattice icarus-verilog modelsim ghdl yosys verilator riviera-pro fossi spyglass

UpdatedDec 18, 2025
Python

dpretet /async_fifo

Sponsor

Star402

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

UpdatedSep 16, 2025
Verilog

mshr-h /vscode-verilog-hdl-support

Sponsor

Star344

HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

UpdatedDec 18, 2025
TypeScript

ZipCPU /sdspi

Star339

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface

UpdatedOct 18, 2025
Verilog

ZipCPU /wbuart32

Star318

A simple, basic, formally verified UART controller

fpga verilog uart serialport uart-verilog wishbone verilator wishbone-bus

UpdatedJan 29, 2024
Verilog

chipsalliance /Cores-VeeR-EL2

Star309

VeeR EL2 Core

fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2

UpdatedDec 18, 2025
SystemVerilog

tymonx /logic

Star283

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

UpdatedNov 25, 2019
SystemVerilog

ZipCPU /dblclockfft

Star251

A configurable C++ generator of pipelined Verilog FFT cores

fpga gplv3 verilog fft verilog-components verilator

UpdatedApr 18, 2024
C++

ZipCPU /autofpga

Star185

A utility for Composing FPGA designs from Peripherals

c-plus-plus fpga verilog wishbone verilator wishbone-bus

UpdatedDec 23, 2024
C++

ZipCPU /vgasim

Star174

A Video display simulator

video fpga gplv3 verilog gtkmm vga verilator video-simulator

UpdatedMay 16, 2025
Verilog

ZipCPU /openarty

Star131

An Open Source configuration of the Arty platform

fpga fpga-soc wishbone verilator arty zipcpu wishbone-bus

UpdatedJan 17, 2024
Verilog

ZipCPU /dpll

Star115

A collection of phase locked loop (PLL) related projects

fpga gplv3 verilog verilator pll

UpdatedJan 18, 2024
Verilog

tscheipel /HaDes-V

Star95

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design

UpdatedJun 5, 2025
SystemVerilog

Improve this page

Add a description, image, and links to theverilator topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with theverilator topic, visit your repo's landing page and select "manage topics."

Learn more

Movatterモバイル変換

Navigation Menu

Search code, repositories, users, issues, pull requests...

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

verilator

Here are 184 public repositories matching this topic...

verilator /verilator

ultraembedded /riscv

ZipCPU /zipcpu

chili-chips-ba /wireguard-fpga

ultraembedded /biriscv

chipsalliance /Cores-VeeR-EH1

ultraembedded /cores

olofk /edalize

dpretet /async_fifo

mshr-h /vscode-verilog-hdl-support

ZipCPU /sdspi

ZipCPU /wbuart32

chipsalliance /Cores-VeeR-EL2

tymonx /logic

ZipCPU /dblclockfft

ZipCPU /autofpga

ZipCPU /vgasim

ZipCPU /openarty

ZipCPU /dpll

tscheipel /HaDes-V

Improve this page

Add this topic to your repo