uvm

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi antlr4-grammar parser-ast vpi-api vpi-standard

UpdatedMar 6, 2025
C++

rggen /rggen

Star373

Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

UpdatedFeb 19, 2025
Ruby

troyguo /awesome-dv

Star287

Awesome ASIC design verification

asic verification uvm formal-verification asic-verification

UpdatedFeb 9, 2022

tymonx /logic

Star276

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

UpdatedNov 25, 2019
SystemVerilog

Nic30 /hwt

Star208

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

simulator fpga compiler hls vhdl rtl verilog hcl codegenerator codegen systemverilog systemc uvm

UpdatedNov 23, 2024
Python

Juniper /open-register-design-tool

Star198

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

asic fpga eda systemverilog uvm registers systemrdl jspec register-descriptions systemrdl-compiler

UpdatedOct 21, 2024
Verilog

taichi-ishitani /tnoc

Sponsor

Star170

Network on Chip Implementation written in SytemVerilog

systemverilog uvm noc axi amba network-on-chip axi4 amba-axi

UpdatedAug 27, 2022
SystemVerilog

kumarrishav14 /AXI

Star122

VIP for AXI Protocol

uvm sv asic-verification amba-axi design-verification

UpdatedMay 24, 2022
SystemVerilog

SystemRDL /PeakRDL

Star116

Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

UpdatedMar 12, 2025
Python

gupta409 /Processor-UVM-Verification

Star100

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

processor verilog systemverilog uvm verilog-hdl systemverilog-simulation

UpdatedDec 29, 2024
Verilog

nelsoncsc /ISP_UVM

Star93

A Framework for Design and Verification of Image Processing Applications using UVM

opencv image-processing hardware-designs systemc uvm systemverilog-hdl functional-verification

UpdatedNov 27, 2017
SystemVerilog

erihsu /INT_FP_MAC

Star91

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

verilog systemverilog uvm accumulator

UpdatedSep 27, 2020
Verilog

Siddhi-95 /AHB-to-APB-Bridge-Verification

Star85

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

verilog systemverilog uvm

UpdatedJul 2, 2023
SystemVerilog

zhajio1988 /YASA

Star72

🐌Yet Another Simulation Architecture

uvm sv ic dv

UpdatedSep 17, 2020
Python

dadongshangu /async_FIFO

Star58

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

asynchronous fifo uvm verification-code async-fifo verilog-tb

UpdatedOct 19, 2023
SystemVerilog

SystemRDL /PeakRDL-uvm

Star52

Generate UVM register model from compiled SystemRDL input

asic fpga eda uvm registers uvm-ral-model uvm-register-model

UpdatedSep 3, 2024
Python

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uvm

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