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openhwgroup /cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

asic cpu fpga risc-v systemverilog-hdl rv64gc ariane

UpdatedJul 18, 2025
Assembly

VUnit /vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

unit-testing asic fpga vhdl verification testbench verilog-hdl systemverilog-hdl universal-verification-methodology

UpdatedMay 11, 2025
VHDL

nelsoncsc /ISP_UVM

A Framework for Design and Verification of Image Processing Applications using UVM

opencv image-processing hardware-designs systemc uvm systemverilog-hdl functional-verification

UpdatedNov 27, 2017
SystemVerilog

SystemRDL /PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

asic fpga csr systemverilog registers systemverilog-hdl systemrdl systemrdl-compiler

UpdatedJul 16, 2025
Python

pulp-platform /morty

A SystemVerilog source file pickler.

rust picklers rickandmorty systemverilog-hdl

UpdatedOct 20, 2024
Rust

pulp-platform /axi_mem_if

Simple single-port AXI memory interface

asic fpga axi systemverilog-hdl

UpdatedJun 7, 2024
SystemVerilog

nelsoncsc /easyUVM

A simple UVM example with DPI

uvm systemverilog-hdl functional-verification

UpdatedAug 7, 2017
SystemVerilog

snbk001 /100DaysofRTL

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

makefile verilog synthesis systemverilog hdl testbench systemverilog-hdl systemverilog-simulation rtl-design systemverilog-test-bench edge-detector-with-mealy

UpdatedNov 6, 2022
SystemVerilog

pulp-platform /uvm-components

Contains commonly used UVM components (agents, environments and tests).

uvm systemverilog-hdl

UpdatedAug 17, 2018
SystemVerilog

icglue /icglue

A Tcl-Library for scripted HDL generation

verilog systemverilog hdl verilog-hdl systemverilog-hdl tcl-applications

UpdatedApr 30, 2024
Tcl

NikhilMukraj /spiking-neural-networks-hardware

An FPGA design for simulating biological neurons

neural-network computational-biology fpga-accelerator systemverilog-hdl izhikevich-neurons verilog-project biological-neurons

UpdatedJul 5, 2024
SystemVerilog

vinodsake /Last-Level-Cache-Simulator

cache-simulator systemverilog-hdl

UpdatedApr 1, 2017
SystemVerilog

chenyangbing /UVM-example

UVM

systemverilog uvm systemverilog-hdl

UpdatedMar 16, 2020
SystemVerilog

ghosh17 /DualCoreProcessor

ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor

asic rtl systemverilog systemverilog-hdl

UpdatedAug 23, 2017
SystemVerilog

nelsoncsc /basic_uvmc_oct

A simple UVM testbench using UVM Connect and Octave

octave systemc uvm systemverilog-hdl functional-verification

UpdatedAug 7, 2017
SystemVerilog

stineje /ecen4243S25

Spring 2025 ecen4243 Computer Architecture Lab Material

architecture computer systemverilog systemverilog-hdl systemverilog-simulation systemverilog-test-bench

UpdatedMay 2, 2025
HTML

BertVerrycken /BERT

Bit-Efficient Replicator Tech for X, Y, Z axis motor control (3D printers)

fpga systemverilog-hdl vhdl-code 3dprinter

UpdatedAug 3, 2020
VHDL

ssayin /riscv32-cosim-model

RISC-V processor co-simulation using SystemVerilog HDL and UVM.

systemverilog-hdl riscv32 uvm-verification

UpdatedJun 15, 2024
SystemVerilog

SalomeDevkule7 /Neural-Network-Layer-Generator

Application Specific Integrated Circuit(ASIC)

neural-networks vlsi systemverilog-hdl asic-verification

UpdatedJun 7, 2018
SystemVerilog

jiadong5 /ECE385_SP23_ZJUI

Final Project third-perspective-shooting video game PokeHead and some other lab codes and design of ECE385 Digital Systems Laboratory

pokemon hardware-designs fpga-soc systemverilog-hdl boxhead ece385 uiuc-ece zjui

UpdatedJun 8, 2023
C

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