systemverilog

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chipsalliance /verible

Star1.6k

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

productivity parser formatter analysis style-linter linter language-server-protocol syntax-tree lexer yacc systemverilog hacktoberfest lsp-server systemverilog-parser systemverilog-developer sv-lrm verible

UpdatedJul 14, 2025
C++

clash-lang /clash-compiler

Star1.5k

Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

UpdatedJul 17, 2025
Haskell

pulp-platform /axi

Star1.3k

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

UpdatedJul 17, 2025
SystemVerilog

hdl-util /hdmi

Star1.2k

Send video/audio over HDMI on an FPGA

audio video fpga intel xilinx vivado altera hdmi systemverilog dvi quartus hdlmake

UpdatedFeb 3, 2024
SystemVerilog

splinedrive /kianRiscV

Star921

RISC-V Linux SoC, marchID: 0x2b

linux asic cpu fpga x11 riscv verilog xv6 systemverilog mmu soc bare-metal rv32ima chipdesign tinytapeout sv32

UpdatedJun 15, 2025
Verilog

MikePopoloski /slang

Star791

SystemVerilog compiler and language services

parse compiler slang verilog language-service systemverilog

UpdatedJul 16, 2025
C++

veryl-lang /veryl

Star742

Veryl: A Modern Hardware Description Language

rust rtl verilog systemverilog hdl

UpdatedJul 18, 2025
Rust

WangXuan95 /FPGA-FOC

Star717

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

fpga motor verilog systemverilog field-oriented-control bldc pmsm foc svpwm

UpdatedSep 15, 2023
Verilog

olofk /edalize

Star703

An abstraction library for interfacing EDA tools

fpga simulation vhdl eda verilog xilinx synthesis vivado altera systemverilog icestorm lattice icarus-verilog modelsim ghdl yosys verilator riviera-pro fossi spyglass

UpdatedJun 16, 2025
Python

zachjs /sv2v

Star649

SystemVerilog to Verilog conversion

conversion verilog systemverilog yosys

UpdatedJun 23, 2025
Haskell

TerosTechnology /vscode-terosHDL

Star626

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

fpga vhdl verilog systemverilog

UpdatedApr 4, 2025
VHDL

trivialmips /nontrivial-mips

Star603

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

cpu fpga mips xilinx fpga-soc-linux systemverilog fpga-soc

UpdatedJul 7, 2020
SystemVerilog

openhwgroup /core-v-verif

Star568

Functional verification project for the CORE-V family of RISC-V cores.

verification systemverilog uvm risc-v

UpdatedJul 3, 2025
Assembly

dalance /svls

Sponsor

Star517

SystemVerilog language server

rust language-server verilog systemverilog

UpdatedJul 11, 2025
Rust

dalance /sv-parser

Sponsor

Star444

SystemVerilog parser library fully compliant with IEEE 1800-2017

rust parser verilog systemverilog rust-crate

UpdatedMar 4, 2025
Rust

pymtl /pymtl3

Star420

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

python rtl verilog systemverilog hdl open-source-hardware pymtl hardware-generation open-source-eda multi-level-modeling cycle-level-modeling

UpdatedMay 4, 2025
Python

taichi-ishitani /tvip-axi

Sponsor

Star410

AMBA AXI VIP

vip systemverilog uvm axi amba axi4 amba-axi

UpdatedJun 28, 2024
SystemVerilog

WangXuan95 /USTC-RVSoC

Star408

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

cpu fpga riscv rtl verilog systemverilog soc risc-v rv32i softcore

UpdatedSep 14, 2023
SystemVerilog

rggen /rggen

Star406

Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

UpdatedJul 18, 2025
Ruby

jamieiles /80x86

Star402

80186 compatible SystemVerilog CPU core and FPGA reference design

fpga x86 systemverilog softcore 80186

UpdatedMar 22, 2024
C++

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systemverilog

Here are 1,186 public repositories matching this topic...

chipsalliance /verible

clash-lang /clash-compiler

pulp-platform /axi

hdl-util /hdmi

splinedrive /kianRiscV

MikePopoloski /slang

veryl-lang /veryl

WangXuan95 /FPGA-FOC

olofk /edalize

zachjs /sv2v

TerosTechnology /vscode-terosHDL

trivialmips /nontrivial-mips

openhwgroup /core-v-verif

dalance /svls

dalance /sv-parser

pymtl /pymtl3

taichi-ishitani /tvip-axi

WangXuan95 /USTC-RVSoC

rggen /rggen

jamieiles /80x86

Improve this page

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