system-verilog

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design

UpdatedJun 5, 2025
SystemVerilog

RomeoMe5 /DDLM

Star60

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

fsm mips tcl labs verilog alu hse modelsim system-verilog mips-architecture quartus-prime quartus miem terasic-de10-lite terasic verilog-designs ddlm schoolmips dmk-press verilog-book

UpdatedSep 15, 2023
Verilog

Weiyet /RTLStructLib

Star52

RTL data structure

data-structures rtl system-verilog verilog-hdl cocotb uvm-verification

UpdatedAug 10, 2025
SystemVerilog

jtgebert /fpganes_release

Star50

Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog

python java fpga nes verilog de1-soc system-verilog

UpdatedMay 12, 2017
HTML

cvonk /FPGA_SPI

Sponsor

Star25

Connecting FPGA and Arduino using SPI.

arduino fpga circuits spi system-verilog verilog-hdl

UpdatedApr 30, 2022
Verilog

pulp-platform /trace_debugger

Star19

Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.

system-verilog risc-v debugging-tool instruction-trace

UpdatedMar 13, 2024
SystemVerilog

pfnet-research /ATPG4SV

Star18

A prototype of Concolic Testing engine for SystemVerilog, developed as part of PFN summer internship 2018.

ocaml symbolic-execution smt-solver system-verilog concolic-execution atpg

UpdatedDec 21, 2018
OCaml

zeynepCankara /Computer_Organization_Labs

Star17

My solutions for Bilkent University CS224 Computer Organization Labs (Spring 2019). Includes assembly programming assignments together with various processor designs in System Verilog HDL

mips assembly verilog system-verilog computer-organization

UpdatedJun 10, 2019
Assembly

Amirarsalan-sn /RISCV-multi-cycle-processor

Star16

A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL

cpu hardware risc hdl modelsim system-verilog risc-v quartus multi-cycle-processor

UpdatedJun 5, 2023
SystemVerilog

kinap /AES-Processor

Star16

AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.

cryptography fpga aes emulation system-verilog veloce

UpdatedMar 22, 2017
SystemVerilog

esynr3z /pyhdlsim

Star15

Example of Python and PyTest powered workflow for a HDL simulation

python asic fpga pytest rtl verilog icarus-verilog hdl modelsim system-verilog vivado-simulator

UpdatedJan 17, 2021
Python

Nidhinchandran47 /my_rtl_code

Star13

Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

fpga vhdl verilog hdl vlsi system-verilog verilog-hdl verilog-programs verilog-project rtl-coding

UpdatedJun 3, 2024
Verilog

albaEDA /Nirah

Star12

Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.

python verification swig verilog system-verilog verilator