symbiflow
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Documenting the Xilinx 7-series bit-stream format.
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Mar 15, 2025 - Python
Test suite designed to check compliance with the SystemVerilog standard.
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Mar 13, 2025 - SystemVerilog
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
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Mar 16, 2025 - Jupyter Notebook
FPGA tool performance profiling
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Feb 24, 2024 - Python
FPGA Assembly (FASM) Parser and Generator
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Jul 25, 2022 - Python
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
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Feb 9, 2022 - SystemVerilog
Project X-Ray Database: XC7 Series
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Dec 14, 2021 - Shell
Sphinx Extension which generates various types of diagrams from Verilog code.
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Sep 25, 2023 - Python
SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
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Aug 21, 2024 - C++
Python library for working Standard Delay Format (SDF) Timing Annotation files.
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Jul 12, 2024 - Python
Tool for graphically viewing FPGA bitstream files and their connection to FASM features.
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Apr 6, 2022 - Python
Library to convert a FASM file into BELs importable into Vivado.
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Sep 25, 2023 - Verilog
Repository containing common Makefiles for setting up conda environments.
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Feb 10, 2023 - Makefile
An abstraction library for interfacing EDA tools
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Jan 19, 2023 - Python
generate C++ reader/writer from XSD schema
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Dec 1, 2024 - Python
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