static-timing-analysis

UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:

fault-tolerance electronic-design-automation static-timing-analysis fault-analysis single-event-transient

UpdatedJun 20, 2025
Verilog

Randy1005 /Ink

Star7

Incremental k-Critical Path Generation

graph static-timing-analysis

UpdatedAug 6, 2025
C++

MalakSadek /StaticTimingAnalyzer

Star6

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

python c html json graph-algorithms scl verilog logic-gates verilog-hdl logic-circuit static-timing-analysis

UpdatedMar 25, 2021
HTML

ramiomer94 /VLSI-design-projects

Star5

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

verilog semiconductor-physics genus custom-layout virtuoso digital-logic-design static-timing-analysis vlsi-design asic-design rtl-design innovus standard-cells eda-tools rtl-verification cmos-design rtl-to-gdsii cadence-tools

UpdatedJul 12, 2025
Verilog

coherent17 /NYCU-Special-Topics-in-Computer-Aided-Design

Star4

CAD in NYCU

quine-mccluskey-algorithm static-timing-analysis power-analyzer mix-signal-simulation

UpdatedDec 22, 2023
Verilog

kanndil /PathView

Star3

An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

eda primetime critical-path-analysis pathview static-timing-analysis opensta schematic-layout electronic-design

UpdatedOct 22, 2024
HTML

YubiYubi719 /NYCU-Special-Topics-in-Computer-Aided-Design

Star2

quine-mccluskey cad quine-mccluskey-algorithm static-timing-analysis

UpdatedSep 19, 2024
Verilog

Pa1mantri /TCL_Scripting

Star1

TCL Script to automate the generation of Pre-layout QoR results

linux open-source tcl synthesis yosys hardware-description-language static-timing-analysis tcl-procedures opentimer

UpdatedJun 30, 2025
Verilog

Ritvik2103 /vending-machine-design

Star0

Vending Machine Design using Verilog HDL built and tested in Vivado Design Suite

vivado logic-synthesis verilog-hdl static-timing-analysis

UpdatedDec 10, 2024
Verilog

Ritvik2103 /microprocessor-design

Star0

Microprocessor Design using Verilog HDL built and tested in Vivado Design Suite

vivado logic-synthesis verilog-hdl static-timing-analysis

UpdatedDec 7, 2024
Verilog

Crepopcorn /sta_check_temporary

Star0

This project is the script for STA report violated path checks temporarily (not final version due to confidentiality).

python c testing linux shell bash perl bash-script checking static-timing-analysis

UpdatedOct 16, 2024
C

shrishail7 /Router_1X3_PD

Star0

Executed the complete physical design flow of a 1x3 router, encompassing synthesis, floorplanning, placement, clock tree synthesis, routing, and static timing analysis using Synopsys Fusion Compiler on a 32nm technology node.

router routing tcl synthesis cts placement floorplan static-timing-analysis physical-design 32nm-technology

UpdatedDec 14, 2024
Tcl

Brmanzo /MIS-Timer

Star0

Given an OPENRoad subcircuit file, this program will use SPICE to simulate worst-case speed-up and slow-down due to the Multiple-Input-Switching effect. Designed for CSE 222B Advanced VLSI SQ25 with Mitchell Tansey.

spice static-timing-analysis openroad subcircuits multiple-input-switching