A FPGA friendly 32 bit RISC-V CPU implementation

• UpdatedJul 4, 2025
• Assembly

CNN accelerator implemented with Spinal HDL

• UpdatedJan 29, 2024
• Scala

[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning

• UpdatedAug 27, 2024
• Scala

客制化机械键盘——从0开始全套资料

• UpdatedAug 10, 2023
• C

A reimplementation of a tiny stack CPU

• UpdatedDec 8, 2023
• Scala

High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)

• UpdatedAug 29, 2023
• Scala

Clio, ASPLOS'22.

• UpdatedFeb 8, 2022
• C

An High-Performance SLAM Hardware Accelerator Implementation for FPGA

• UpdatedNov 10, 2024
• Scala

SpinalHDL - Cryptography libraries

• UpdatedJul 19, 2024
• Scala

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

• UpdatedAug 26, 2025
• Scala

Translated SpinalHDL-Doc(v1.7.2) into Chinese

• UpdatedJun 11, 2023
• HTML

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

• UpdatedOct 23, 2024
• Scala

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

• UpdatedApr 23, 2021
• VHDL

Wrappers for open source FPU hardware implementations.

• UpdatedApr 10, 2024
• Verilog

The sources of the online SpinalHDL doc

• UpdatedSep 17, 2025
• Python

shdl6800: A 6800 processor written in SpinalHDL

• UpdatedJan 12, 2020
• Scala

Docker Development Environment for SpinalHDL

• UpdatedAug 8, 2024
• Dockerfile

Forth for the J1-CPU

• UpdatedMar 13, 2017
• Forth

List of SpinalHDL projects, libraries, and learning resources.

• UpdatedApr 2, 2025

CNN accelerator implemented with Spinal HDL

• UpdatedDec 27, 2021
• Scala