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soc-kit
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透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
fpgadigitalvhdlveriloglearnxilinxdigital-logicsystemveriloghdlverilog-hdlxilinx-fpgaxilinx-vivadodigital-logic-designaltera-fpgaaltera-cyclone-v-sockitaltera-cyclone-iii-de0altera-quartussoc-kitaltera-cyclonevhdl-verilog
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Oct 25, 2023 - Verilog
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