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ultraembedded /cores

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

UpdatedJul 1, 2021
Verilog

nullobject /sdram-fpga

A FPGA core for a simple SDRAM controller.

fpga controller memory sdram

UpdatedNov 13, 2021
VHDL

SPD-Reader-Writer

1a2m3 /SPD-Reader-Writer

SPD Reader & Writer with Software Write Protection capabilities supporting Arduino and SMBus

windows arduino amd ddr intel nvidia smbus spd eeprom-programmer eeprom-reader sdram ddr3 ddr4 ddr2 spd-reader spd-writer ddr5 rswp

UpdatedJun 23, 2024
C#

hdl-util /sdram-controller

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

fpga controller systemverilog dram quartus sdram as4c4m16sa

UpdatedSep 7, 2020
Verilog

jasonsbeer /Amiga-N2630

A re-imagining of the Amiga A2630 processor card.

unix motorola accelerator ide amiga commodore amigaos coprocessor sdram pata 2000 68030 amix amigados a2630 68882

UpdatedApr 23, 2024
KiCad Layout

ghent360 /riscvOnColorlight-5A-75B

RISC-V soft core running on Colorlight 5B-74B.

fpga riscv risc-v litex sdram ecp5 colorlight lattice-fpga 5a-75 5a-75b ehternet

UpdatedFeb 14, 2021
C

AngeloJacobo /FPGA_SDRAM_Controller

SDRAM controller optimized to a memory bandwidth of 316MB/s

fpga verilog sdram sdram-controller

UpdatedAug 16, 2021
Verilog

iliasam /stm32f429_vga_examples

Code examples of using STM32F429 for generating VGA image.

sdio sdram dcmi stm32f429 ltdc

UpdatedApr 29, 2023
C

machdyne /kuchen

Kuchen Computer

fpga usb computer hdmi ice40 sdram ice40hx8k computer-hardware

UpdatedJun 26, 2024
OpenSCAD

qubeck78 /tangerineA7_200

RiscV based SOC for Qmtech Artix A7-200 board. Includes nekoRv: RISC-V 32 IM Zicsr core. And yes, it runs DOOM :)

vhdl riscv hdmi sdram

UpdatedJan 13, 2025
VHDL

SDRAM_Controller

perehinik /SDRAM_Controller

Verilog SDR SDRAM controller for FPGA Xilinx and Lattice

fpga verilog xilinx lattice sdram

UpdatedJan 3, 2021
VHDL

oscc-ip /sdram

An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

fpga verilog sdram axi4 tapeout

UpdatedMar 12, 2025
Scala

andrempmattos /harsh-payload

Harsh Environment CubeSat Payload designed to evaluate three different manufacturing nodes SDR SDRAM technologies under space radiation conditions. It was developed for the FloripaSat-2 CubeSat mission.

fpga freertos smartfusion2 sdram armcortexm3 cubesat-payload m2s010 m2s025 radiation-experiment spacelab-ufsc

UpdatedSep 7, 2021
VHDL

yigitbektasgursoy /SDRAM_Verilog

Verilog HDL implementation of SDRAM controller and SDRAM model

verilog vivado verilog-hdl sdram sdram-controller verilog-project

UpdatedJun 19, 2024
Verilog

MinatsuT /CYC1000_SDRAM

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

fpga quartus-prime nios2 sdram sdram-controller cyclone-10lp cyc1000

UpdatedJul 8, 2021
Verilog

har-in-air /SIPEED_TANG_PRIMER

Projects using the Sipeed Tang Primer FPGA development board

fpga ov7670 sdram sipeed-tang-primer audio-crossover

UpdatedDec 6, 2020
Verilog

Arkowski24 /sdram-controller

Simple SDRAM Controller for DE10-Lite.

fpga verilog sdram sdram-controller

UpdatedJan 20, 2019
Verilog

cw1997 /SDRAM-Controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

hardware systemverilog hardware-designs sdram sdram-controller verilog-project

UpdatedJul 1, 2022
HTML

jakubcabal /sdram-tester-fpga

SDRAM Tester implemented in FPGA

python fpga vhdl sdram sdram-controller cyc1000 measures-throughput sdram-tester

UpdatedMay 1, 2021
VHDL

egk696 /EDAC_SDRAM_Controller

Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

fpga vhdl embedded-systems vivado fault-tolerant quartus-prime sdram sdram-controller cots-sdram

UpdatedOct 30, 2017
Verilog

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