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pulp-platform /ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

asic cpu vector riscv ara rvv rv64gcv

UpdatedMar 13, 2025
C

camel-cdr /rvv-bench

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

benchmark risc-v rvv

UpdatedMar 3, 2025
Assembly

ucb-bar /saturn-vectors

Chisel RISC-V Vector 1.0 Implementation

cpu chisel vectors risc-v microarchitecture rvv

UpdatedFeb 11, 2025
Assembly

chipsalliance /riscv-vector-tests

Unit tests generator for RVV 1.0

generator spike riscv testsuite rvv

UpdatedMar 11, 2025
Go

dzaima /intrinsics-viewer

x86-64, ARM, and RVV intrinsics viewer

neon x86-64 avx avx2 avx512 risc-v simd-intrinsics sve rvv

UpdatedMar 16, 2025
JavaScript

howjmay /neon2rvv

A translator from ARM NEON intrinsics to RISCV-V Extension implementation

arm neon simd riscv intrinsics armv7 arm64 aarch64 armv8 riscv64 armv8-a rvv apple-silicon sse2neon

UpdatedAug 26, 2024
C++

camel-cdr /rvv-bench-results

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)

benchmark risc-v rvv

UpdatedDec 5, 2024
HTML

jiegec /rvv-kernels

Implements kernels with RISC-V Vector

vector riscv rvv

UpdatedMar 24, 2023
Assembly

hushenwei2000 /rvv-atg

RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Compliance test).

UpdatedApr 3, 2024
Python

plctlab /riscv-vectorized-benchmark-suite

RISC-V Vectorized Bencmark Suite. based onhttps://github.com/RALC88/riscv-vectorized-benchmark-suite

benchmark risc-v rvv

UpdatedOct 28, 2022
C++

dkurt /hair_segmentation

Hair recoloring on RISC-V with OpenCV

opencv deep-learning risc-v licheepi tflite riscv64 mediapipe rvv mangopi-mq-pro

UpdatedApr 19, 2023
Python

UCTECHIP /rocket_chip_vpu

scala rocket-chip chisel vpu rvv

UpdatedJan 9, 2021
Scala

cbalint13 /rvv-kernels

RISCV Vector Kernel C/LLVM-IR generator

kernel math vector llvm riscv int8 tvm rvv

UpdatedDec 16, 2024
C

sebikolon /MMM-RVV

MagicMirror² module: Departure monitor for the RVV (Regensburger Verkehrsverbund) bus system (ÖPNV, public transport)

magicmirror bus transport bayern departure-monitor rvv

UpdatedJan 21, 2021
JavaScript

Nuclei-Software /nuclei-ai-library

Nuclei AI Library Optimized For RISC-V Vector

riscv risc-v ai-library rvv

UpdatedDec 24, 2024
C

YADRO-KNS /halide_riscv

Examples of Halide language algorithms running on RISC-V

llvm halide vectorization risc-v riscv64 rvv allwinner-d1 c906 xuantie

UpdatedMar 1, 2023
Assembly

dkurt /llvm-rvv-071

Patched version of LLVM to unblock RISC-V vectorization with 0.7.1 ISA

risc-v rvv c906

UpdatedFeb 21, 2023

MarekPikula /RISC-V-Summit-Europe-ORConf-2024

Resources for RISC-V Summit Europe 2024 and ORConf 2024 with topic: Accelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study

conference risc-v rvv

UpdatedOct 21, 2024
TeX

dkurt /halide_riscv

Examples of Halide language algorithms running on RISC-V

llvm halide vectorization risc-v riscv64 rvv allwinner-d1 c906 xuantie

UpdatedFeb 9, 2024
Assembly

einFreak /ha-regensburg-transport

Regensburg (RVV) transport sensor for Home Assistant

python transport home-assistant regensburg rvv rvv-regensburg

UpdatedNov 27, 2024
Python

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