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chipsalliance /chisel

Star4.4k

Chisel: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

UpdatedOct 7, 2025
Scala

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITab…

android ios ui uitableview uicollectionview xcode view css3 layout cocoapods xib storyboard constraints rtl grid-layout autolayout uiscrollview flexbox-layout layoutsubviews sizeclasses

UpdatedApr 16, 2024
Objective-C

chipsalliance /rocket-chip

Star3.6k

Rocket Chip Generator

scala rocket-chip chip-generator chisel riscv rtl

UpdatedSep 2, 2025
Scala

verilator /verilator

Star3.1k

Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator

UpdatedOct 7, 2025
C++

layoutBox /PinLayout

Star2.4k

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

swift language swift-library ios cocoapod layout carthage layout-engine rtl swift-framework swift-3 ios-swift anchor ios-ui ios-lib margin chainable-methods uiview-extension left-language

UpdatedJul 23, 2025
Swift

The-OpenROAD-Project /OpenROAD

Star2.2k

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation athttps://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

UpdatedOct 7, 2025
Verilog

ucb-bar /chipyard

Star2k

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha

UpdatedOct 6, 2025
Scala

riscv-boom /riscv-boom

Star2k

SonicBOOM: The Berkeley Out-of-Order Machine

scala berkeley boom rocket-chip chisel riscv rtl riscv-boom

UpdatedMay 6, 2025
Scala

SpinalHDL /SpinalHDL

Star1.9k

Scala based HDL

scala fpga vhdl rtl verilog

UpdatedOct 7, 2025
Scala

MohammadYounes /rtlcss

Star1.7k

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

css i18n postcss css3 mirror ltr rtl cascading-style-sheets postcss-plugin flip rtlcss right-to-left left-to-right

UpdatedFeb 18, 2025
JavaScript

The-OpenROAD-Project /OpenLane

Star1.6k

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

UpdatedSep 15, 2025
Python

pulp-platform /axi

Star1.4k

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

UpdatedOct 7, 2025
SystemVerilog

siliconcompiler /siliconcompiler

Star1.1k

Modular hardware build system

asic fpga hls vhdl eda rtl verilog make synthesis cmos

UpdatedOct 7, 2025
Python

kartik-v /bootstrap-star-rating

Star1.1k

A simple yet powerful JQuery star rating plugin with fractional rating support.

javascript css jquery rating css-styles rtl caption star bootstrap-star-rating rate-control change-stars star-symbols fractional

UpdatedMar 22, 2023
JavaScript

syntacore /scr1

Star935

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core riscv rtl ip verilog risc-v rv32i rv32e rv32imc rv32emc

UpdatedNov 15, 2024
SystemVerilog

chipsalliance /Cores-VeeR-EH1

Star900

VeeR EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer

UpdatedMay 29, 2023
SystemVerilog

eldraco /Salamandra

Star837

Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

python threshold microphone sound rtl sdr microphones spy spy-microphones salamandra find-microphones detect-microphones

UpdatedJan 11, 2021
Python

ultraembedded /cores

Sponsor

Star835

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

UpdatedJul 1, 2021
Verilog

WangXuan95 /FPGA-USB-Device

Star816

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。