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#

risc-v

riscv logo

Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.

Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.

Here are 2,134 public repositories matching this topic...

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.

  • UpdatedJul 14, 2025
  • Assembly

Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, x86_64 servers, websocket server/client, support 12 programming languages

  • UpdatedJul 17, 2025
  • C++

Open-source high-performance RISC-V processor

  • UpdatedJul 18, 2025
  • Scala

A secure embedded operating system for microcontrollers

  • UpdatedJul 18, 2025
  • Rust
DietPi

Lightweight justice for your single-board computer!

  • UpdatedJul 18, 2025
  • Shell

面向IoT领域的、高可伸缩的物联网操作系统,可去官网了解更多信息https://www.aliyun.com/product/aliosthings

  • UpdatedJul 4, 2023
  • C

OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32

  • UpdatedJan 27, 2023
  • Rust

A fully compliant RISC-V computer made inside the game Terraria

  • UpdatedMar 24, 2025
  • Rust
Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

  • UpdatedMay 12, 2025
  • C++

Deprecated, please go to next generation Ultra-Low Power RISC-V Corehttps://github.com/riscv-mcu/e203_hbirdv2

  • UpdatedMar 24, 2021
  • Verilog

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  • UpdatedJul 18, 2025
  • Assembly
arduino-pico

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

  • UpdatedJul 14, 2025
  • C

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  • UpdatedJul 16, 2025
  • Verilog

Modern, advanced, portable, multiprotocol bootloader and boot manager.

  • UpdatedJul 14, 2025
  • C

The official repository for the gem5 computer-system architecture simulator.

  • UpdatedJul 17, 2025
  • C++

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

  • UpdatedJul 18, 2025
  • C++
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github.com/topics/riscv
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