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#

risc-v

riscv logo

Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.

Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.

Here are 2,419 public repositories matching this topic...

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Parsing gigabytes of JSON per second : used by Facebook/Meta Velox, the Node.js runtime, ClickHouse, WatermelonDB, Apache Doris, Milvus, StarRocks

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A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.

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Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages

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OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32

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A fully compliant RISC-V computer made inside the game Terraria

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A graphical processor simulator and assembly editor for the RISC-V ISA

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Modern, advanced, portable, multiprotocol bootloader and boot manager. (Official mirror ofhttps://codeberg.org/Limine/Limine)

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Deprecated, please go to next generation Ultra-Low Power RISC-V Corehttps://github.com/riscv-mcu/e203_hbirdv2

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The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

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The official repository for the gem5 computer-system architecture simulator.

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