priority-encoder

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Vedant-02 /Verilog-HDL-Lab-Experiments

Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

verilog hacktoberfest barrel-shifter full-adder carry-look-ahead-adder 4-bit-comparator carry-select-adder adder-subtractor bcd-adder binary-multiplier binary-to-gray hacktoberfest2022 32-bit-alu priority-encoder 4-bit-parallel-adder 4-bit-combinational-adder bcd-to-7-segment 32-bit-fast-adder carry-skip-adder bcd-subtractor

UpdatedOct 23, 2022
Verilog

MuballighHossain /Full_Adder_Priority_Encoder_VLSI

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encoder fulladder vlsi vlsi-circuits vlsi-design priority-encoder

UpdatedAug 20, 2022
Verilog

CodiieSB /VHDL-PriorityEncoder4x2

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A 4x2 priority encoder is a digital circuit that takes four input lines and encodes them into a two-bit binary output based on the priority of the input lines.

encoder vhdl priority xilinx-vivado vhdl-examples 4x2 priority-encoder