pnr

This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II

asic dft verilog synthesis uart fm pnr

UpdatedApr 29, 2024
Verilog

abdelazeem201 /ICC2_scripts

Star16

This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.

tcl soc pnr tcl-extension

UpdatedFeb 11, 2024
Tcl

abdelazeem201 /ASIC-Implementation-UART

Star10

This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…

asic fpga vhdl eda rtl verilog synthesis uart soc pnr

UpdatedMar 30, 2022
Verilog

porglezomp /minecraft-eda

Star9

Electronic design automation for Minecraft

minecraft eda logic-synthesis pnr place-and-route

UpdatedMay 3, 2019
Python

AkshayXPatil /Physical-Layout-Design

Star4

Complete design of USART interface with baud rate selection

scripting rtl verilog uart vlsi-physical-design gds2 pnr gdsii

UpdatedAug 24, 2022
Verilog

crackCodeLogn /PNR_Enquiry_IndianRailways_v2.0

Star4

This project caters to the extraction of the status of PNR number (Passenger Name Record) of Indian Railways. PNR number is unique to each and every ticket bought in the railways. With the help of it, we can get the exact details of the ticket in hand

java ticket slf4j lombok gson guava mockito assertj java-8 java-swing pnr indian-railways apache-commons slf4j-api openfeign

UpdatedDec 9, 2021
Java

Transavia /ShoppingCartExample

Star4

Shopping Cart Example

shopping-cart airline flights pnr flights-api airlines-booking

UpdatedApr 23, 2018
JavaScript

mohamedtareq24 /ASICs_Design_Diploma

Star4

RTL to GDSII flow of a low Power configurable multi clock digital system

project rtl verilog-hdl pnr asics

UpdatedMar 3, 2024
Verilog

abdelazeem201 /RV32E201X

Star3

RV32E201X is a 5-stage pipelined 32-bit RISC-V processor core.

fpga icc rtl verilog synthesis hdl soc risc-v pnr rv32e201x risc-v32 designcomp

UpdatedMay 1, 2023
Verilog

kholoud0 /ASIC-implementation-of-CV32E40P-RISC-V-core-

Star2

This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).

asic synthesis implementation synopsys pnr synopsys-dc synopsys-iccii

UpdatedMay 12, 2024
SystemVerilog

Li-Yueting /aloe-sky130

Star2

eda pnr analog-design

UpdatedNov 15, 2024
Verilog

crackCodeLogn /PNR_Enquiry_IndianRailways

Star2

java java-swing java-network pnr indian-railways

UpdatedJun 19, 2019
Java

mohamedtareq24 /ASIC_implementation_of_PULPino_SoC

Star2

My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools

asic risc-v pnr synopsys-dc synopsys-iccii