openlane-flow

In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS)

asic-design openlane-flow rtltogds2

UpdatedAug 19, 2024

harshithsn /Universal-Shift-Register

Star11

This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.

vlsi vlsi-physical-design openlane universal-shift-register openlane-flow

UpdatedJul 19, 2022
Verilog

CodePurble /sap

Star9

The SAP-1 in Verilog, and now as an ASIC!

asic verilog openlane-flow sap-computers

UpdatedNov 5, 2022
Verilog

krutideepanpanda /RISC-V-based-micro-controller-using-OpenLane

Star9

This is part of EC383 - Mini Project in VLSI Design.

verilog vlsi verilog-project vlsi-design openlane verilog-processor openlane-flow

UpdatedMay 8, 2022
Verilog

MayurTA /VSD-IAT_workshop

Star5

Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry

vsd vlsi vlsi-cad openlane gdsii-flow openlane-flow

UpdatedFeb 25, 2021

ShyamRazesh /DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING

Star2

2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)

open-source vlsi-physical-design sky130 openlane-flow

UpdatedDec 14, 2025

arhamhashmi01 /openlane-verification

Star2

This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.

opensource verification synthesis gds cts netlist placement klayout floorplan openlane openlane-flow openlane-github-netlist-simulation-

UpdatedMar 8, 2024
Verilog

Pa1mantri /VSDMemSOC

Star2

VSDMemSOC Implementation flow:: RTL2GDSII

macros riscv yosys gdsii physical-design openroad opensta openlane-flow sram-macro

UpdatedMar 1, 2024
Verilog

Pa1mantri /NASSCOM_SoC_Design

Star1

Complete RTL to GDSII flow of a picorv32a core

opensource opensta rtl2gds openlane-flow

UpdatedJun 6, 2025

Mummanajagadeesh /inverter-rtl-2-gdsii

Star1

Complete ASIC design flow for a Simple Inverter — from RTL (Verilog) to GDSII — using the OpenLane toolchain and the SkyWater 130nm PDK (sky130)

open-source opensource asic rtl abc yosys gdsii openlane gdsii-flow openlane-flow rtl-to-gdsii

UpdatedSep 28, 2025
Verilog

muhammadtalhasami /openlane

Star1

This is my openlane repository in which we perform synthesis of our design/module.

synthesis netlist klayout openlane openlane-flow muhammadtalhasami-github-openlanegithub-openlane-github-muhammad-talha-github-desgin-synthesis-netlist-simulation-floorplan-placement-rounting-cts-

UpdatedMar 17, 2024
Tcl

Pa1mantri /Characterisation_of_a_standard_cell

Star1

Characterised a standard inverter and adding to the openlane flow

magic lef cmos-inverter sky130 openlane-flow

UpdatedMar 5, 2024

Preethigrace-7 /RTL-TO-GDSII-FLOW-OF-RISC_V-32-BIT-PROCESSOR

Star1

Build up myself with extendable knowledge from Fundamentals of VLSI to Chip Tapeout. Worked on RISCV 32bit processor from RTL to GDSII flow with specified Industry standard constraints using Open source tool Openlane.

open-source riscv32 physical-design tcl-script openlane-flow rtltogds2