Network on Chip Simulator

• UpdatedJan 22, 2024
• C++

A Chisel RTL generator for network-on-chip interconnects

• UpdatedMar 10, 2025
• Scala

Network on Chip Implementation written in SytemVerilog

• UpdatedAug 27, 2022
• SystemVerilog

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

• UpdatedNov 18, 2024
• SystemVerilog

Official read only mirror for

• UpdatedMar 17, 2025
• Python

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

• UpdatedMar 19, 2018
• SystemVerilog

OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores

• UpdatedMar 8, 2021
• C

A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network

• UpdatedFeb 22, 2025
• Verilog

HLS for Networks-on-Chip

• UpdatedFeb 18, 2021
• C++

Development of a Network on Chip Simulation using SystemC.

• UpdatedJul 14, 2017
• C++

DevJam 2020: In-game NOC boards

• UpdatedApr 14, 2023
• Java

cycle accurate Network-on-Chip Simulator

• UpdatedApr 25, 2023
• C

Network on Chip for MPSoC

• UpdatedMar 16, 2025
• SystemVerilog

Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator

• UpdatedDec 22, 2023
• Verilog

System-on-Chip Interconnection Network - Simulation Environment (front-end)

• UpdatedOct 5, 2023
• C++

Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research

• UpdatedJan 21, 2024
• TypeScript

Fork of the gem5 simulator with Garnet2.0 and DSENT extensions

• UpdatedJan 28, 2019
• C++

experiments in the vector field

• UpdatedApr 1, 2017
• Processing

External Network Operations Center for EPFL SI ISAS-FSD

• UpdatedMar 5, 2025
• Shell

Core mapping on to NOC

• UpdatedNov 7, 2019
• C