AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

• UpdatedMar 21, 2025
• SystemVerilog

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

• UpdatedMar 8, 2025
• C

A Chisel RTL generator for network-on-chip interconnects

• UpdatedMar 10, 2025
• Scala

Network on Chip Implementation written in SytemVerilog

• UpdatedAug 27, 2022
• SystemVerilog

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

• UpdatedNov 18, 2024
• SystemVerilog

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

• UpdatedMar 19, 2018
• SystemVerilog

HLS for Networks-on-Chip

• UpdatedFeb 18, 2021
• C++

Ratatoskr NoC Simulator

• UpdatedApr 13, 2021
• Python

HLS code for Network on Chip (NoC)

• UpdatedSep 11, 2020
• C++

System-on-Chip Interconnection Network - Simulation Environment (front-end)

• UpdatedOct 5, 2023
• C++

Development and simulation framework for Application Specific Vector Processor

• UpdatedMar 8, 2020
• C++

My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA

• UpdatedJun 26, 2018
• Verilog

RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer units, routing units, switch allocators, switches, routers, and nodes, along with comprehensive high-level testing scenarios. Developed as part of a Core-Based Embedded System Design course.

• UpdatedJul 12, 2024
• SystemVerilog

Fork of the gem5 simulator with Garnet2.0 and DSENT extensions

• UpdatedJan 28, 2019
• C++

Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research

• UpdatedJan 21, 2024
• TypeScript

A Voting Approach for Adaptive Network-on-Chip Power-Gating

• UpdatedDec 14, 2022
• C++

A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs

• UpdatedOct 30, 2017
• VHDL

System-on-Chip Interconnect Network Simulation Environment back-end (simulator)

• UpdatedSep 26, 2019
• C++

In this project, I investigate and design a NoC system consisting of the router/switch, IPs (CPU or other hardware module), and interconnection structure (topology) such as Mesh.

• UpdatedNov 23, 2024
• VHDL

A Network-on-Chip for the System-of-Systems Era, Enabling mixed interface communication between embedded devices (MCU, sensors etc.) over a common protcol stack

• UpdatedJun 7, 2018
• VHDL