A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL

• UpdatedJun 5, 2023
• SystemVerilog

A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.

• UpdatedAug 31, 2020
• SystemVerilog

Single and Multi-cycle ARM processors implemented using VHDL

• UpdatedJan 26, 2021
• VHDL

Micro-Programmed Multi-Cycle Processor

• UpdatedSep 9, 2020
• SystemVerilog

This rep contains neighbour's cpu. Single-cycle/Multi-cycle CPU implementation in vhdl using ISE Xiling for the course 'Computer Organization' at TUC

• UpdatedJul 29, 2024
• VHDL

Mips Multi-Cycle, Computer Architecture course, University of Tehran

• UpdatedAug 4, 2020
• SystemVerilog

Implementation of an ARM processor with hazard and forwarding units, along with SRAM and cache memory

• UpdatedNov 1, 2024
• Verilog

Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor

• UpdatedJun 28, 2024
• Verilog

MIPS processor designed in Verilog.

• UpdatedAug 18, 2023
• Verilog

Computer Architecture Course Projects

• UpdatedAug 19, 2022
• Verilog

Verilog descriptions of MIPS single-cycle, multi-cycle & booth multiplier.

• UpdatedAug 18, 2023
• Verilog

Code files related to the Computer Architecture course, taught by M. Movahedin

• UpdatedSep 5, 2024
• Verilog

• UpdatedNov 26, 2022
• VHDL

👷‍♀️Computer Architecture Course Projects, University of Tehran

• UpdatedSep 5, 2021