ip-core
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Implementation of a Tensor Processing Unit for embedded systems and the IoT.
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Jan 5, 2019 - VHDL
An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。
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Jan 26, 2024 - Verilog
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
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Feb 27, 2024 - Verilog
🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
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Nov 22, 2025 - Python
USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
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Oct 24, 2017 - Verilog
Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)
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Jul 29, 2020 - C++
Synthesizable SystemVerilog IP-Core of the I2S Receiver
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Jun 7, 2020 - SystemVerilog
Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.
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Feb 14, 2017 - Verilog
📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
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Jan 26, 2024 - Python
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
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Jul 12, 2017 - VHDL
A Python-based IP Core Management Infrastructure.
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Apr 29, 2021 - Python
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
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Jun 7, 2020 - SystemVerilog
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
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Jun 6, 2020 - SystemVerilog
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