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instruction-decoding

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RVVM

LekKit /RVVM

The RISC-V Virtual Machine

c linux emulator vm translation virtual-machine emulation jit riscv risc emulators risc-v riscv32 riscv-linux riscv64 tracing-jit riscv-simulator riscv-emulator instruction-decoding rvvm

UpdatedDec 11, 2025
C

DispatchCode /x64-Instruction-Decoder

An x86/x64 instruction disassembler written in C

c assembly x64 reverse-engineering disassembler x86 low-level machine-code instruction-set architectures disassembler-library instruction-decoding

UpdatedDec 2, 2025
C

CGuardProbe

OPSphystech420 /CGuardProbe

Memory Engine and Scanner for iOS/MacOS using Mach API

macos api hooks security ios cpp memory reverse-engineering mach-o ida memory-scanning error-logging instruction-decoding vmt-hooking

UpdatedNov 16, 2024
C++

Danijel-Korent /RISC-V-emulator

RISC-V emulator/simulator in Python

python education processor-architecture cpu python3 riscv bare-metal risc-v baremetal cpu-simulator riscv32 riscv-linux riscv-simulator riscv-emulator rv32ima instruction-decoding risc-v-emulator risc-v-simulator system-emulation

UpdatedAug 25, 2025
Python

BeRo1985 /pasriscv

PasRISCV is a RV64GC RISC-V emulator, which is implemented in Object Pascal

emulator delphi pascal vm virtual-machine freepascal riscv emulators risc-v object-pascal virtio riscv-linux riscv64 riscv-emulator rv64gc rv64 instruction-decoding

UpdatedNov 29, 2025
Pascal

uros-bojanic /8-bit-computer

[Computer Engineering] Programmable 8-bit computer based on von Neumann architecture, designed and implemented from scratch in Logisim.

logisim cpu-architecture von-neumann-architecture instruction-decoding

UpdatedApr 25, 2022

BeRo1985 /pasriscvemu

The PasVulkan-based emulator frontend for the PasRISCV RV64GC RISC-V emulator

emulator delphi pascal vm virtual-machine vulkan freepascal riscv emulators risc-v object-pascal virtio riscv-linux riscv64 riscv-emulator rv64gc rv64 instruction-decoding

UpdatedOct 8, 2025
Pascal

keneoneth /InstrHexBinDecConvertDecoder-Release

a web based front end only helper tool that provides Instruction Decoder and Converter in hexadecimal binary decimal form encoding of different ISA

instructions opcodes instruction-set-architecture binary-hexadecimal-converter binary-to-decimal-number-converter instruction-decoding

UpdatedFeb 6, 2023
HTML

gaidardzhiev /tortoise

custom CPU emulator and assembler

assembler assembly-language instruction-set-architecture cpu-emulator cpu-architecture fetch-decode-execute bitwise-operations instruction-decoding emulator-development cpu-architecture-design

UpdatedNov 10, 2025
C

leonlafa /sap1-logisim

A simulation of a Simple-As-Possible (SAP) computer, implemented in Logisim Evolution.

ram binary electronics logic-gates alu 8bit sap1 registers digital-electronics memory-address program-counter electronics-engineering full-adder control-sequences sap-1 arithmetic-logic-unit bus-system 8bitcomputer instruction-decoding sap-1-computer

UpdatedMay 26, 2025

christalphilip /mips-disassembler

A Java-based MIPS disassembler that converts binary machine code into readable MIPS assembly instructions, supporting key R- and I-format instructions with branch target address resolution.

java mips assembly disassembler computer-architecture instruction-decoding

UpdatedJul 31, 2025
Java

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