hdl

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Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

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langhuihui /monibuca

Star2.2k

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

relay rtsp mp4 hls livestream rtmp websocket webrtc flv ts srt record rtp mediaserver hdl webtransport

UpdatedOct 6, 2025
Go

stnolting /neorv32

Star1.9k

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller embedded cpu fpga processor vhdl riscv smp multi-core rtos hdl soc risc-v soft-core system-on-chip rv32 asip neorv32 on-chip-debbuger

UpdatedOct 7, 2025
VHDL

amaranth-lang /amaranth

Star1.8k

A modern hardware definition language and toolchain based on Python

fpga hdl amaranth-hdl

UpdatedSep 4, 2025
Python

analogdevicesinc /hdl

Star1.8k

HDL libraries and projects

fpga verilog hdl hacktoberfest analog-devices jesd204b

UpdatedOct 7, 2025
Verilog

aappleby /metroboy

Star1.2k

A repository of gate-level simulators and tools for the original Game Boy.

emulator simulator gameboy gameboy-emulator verilog hdl

UpdatedFeb 23, 2025
C++

drom /awesome-hdl

Star1.1k

Hardware Description Languages

awesome vhdl verilog awesome-list hdl hacktoberfest hardware-description-language

UpdatedJul 14, 2025

veryl-lang /veryl

Star801

Veryl: A Modern Hardware Description Language

rust rtl verilog systemverilog hdl

UpdatedOct 6, 2025
Rust

m-labs /nmigen

Star679

A refreshed Python toolbox for building complex digital hardware. Seehttps://gitlab.com/nmigen/nmigen

fpga hdl yosys nmigen

UpdatedJan 8, 2022
Python

WangXuan95 /BSV_Tutorial_cn

Star587

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

fpga verilog bluespec hdl bluespec-systemverilog bsv hardware-description-language

UpdatedSep 15, 2023
Bluespec

intel /rohd

Star446

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

framework simulator hardware verification rtl hdl hardware-verification hardware-design

UpdatedOct 6, 2025
Dart

Nuand /bladeRF-wiphy

Star436

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

vhdl rtl hdl ofdm bladerf ofdm-wireless-communications 80211 dsss

UpdatedApr 15, 2024
VHDL

pymtl /pymtl3

Star430

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

python rtl verilog systemverilog hdl open-source-hardware pymtl hardware-generation open-source-eda multi-level-modeling cycle-level-modeling

UpdatedAug 24, 2025
Python

slaclab /surf

Star402

A huge VHDL library for FPGA and digital ASIC development

python asic fpga firmware vhdl hdl

UpdatedOct 7, 2025
VHDL

analogdevicesinc /plutosdr-fw

Star400

PlutoSDR Firmware

linux fpga sdr iio transceiver rf hdl plutosdr adalm-pluto active-learning-module plutosdr-fw plutosdr-firmware

UpdatedOct 15, 2024
Shell

tensil-ai /tensil

Star388

Open source machine learning accelerators

machine-learning scala asic fpga artificial-intelligence hdl silicon

UpdatedMar 24, 2024
Scala

dpretet /async_fifo

Sponsor

Star382

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

UpdatedSep 16, 2025
Verilog

viduraakalanka /HDL-Bits-Solutions

Star363

This is a repository containing solutions to the problem statements given in HDL Bits website.

verilog hdl

UpdatedJul 16, 2023
Verilog

chipsalliance /sv-tests

Star344

Test suite designed to check compliance with the SystemVerilog standard.

rtl verilog systemverilog hdl compliance-testing symbiflow

UpdatedOct 8, 2025
SystemVerilog

spamegg1 /reviews

Star331

Reviewing some online CS courses I took

javascript ruby kotlin python c java scala networking algorithms racket assembly computer-graphics logic mathematics databases programming-languages nand2tetris operating-systems hdl smlnj

UpdatedMar 10, 2025
JavaScript

Kitware /VeloView

Star324

VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror ofhttps://gitlab.kitware.com/LidarView/VeloView-Velodyne.

lidar velodyne-sensor velodyne sensor-data hdl lidar-measurements lidar-data-manipulation lidar-camera-calibration velodyne-hdl-sensors sensor-streaming

UpdatedSep 29, 2021
C++

Followers: 491 followers
Website: github.com/topics/verilog
Wikipedia: Wikipedia

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