hardware-description-language

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Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

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clash-lang /clash-compiler

Star1.6k

Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

UpdatedDec 16, 2025
Haskell

drom /awesome-hdl

Star1.1k

Hardware Description Languages

awesome vhdl verilog awesome-list hdl hacktoberfest hardware-description-language

UpdatedJul 14, 2025

JulianKemmerer /PipelineC

Star692

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

python c fpga hls hardware vhdl pipelines open-source-hardware high-level-synthesis hardware-description-language fpga-accelerators fpga-acceleration fpga-programming hardware-description

UpdatedDec 4, 2025
VHDL

WangXuan95 /BSV_Tutorial_cn

Star595

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

fpga verilog bluespec hdl bluespec-systemverilog bsv hardware-description-language

UpdatedSep 15, 2023
Bluespec

jofrfu /tinyTPU

Star525

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

linux iot fpga zynq tensorflow assembly vhdl embedded-systems internet-of-things hardware-architectures verilog xilinx vivado tensor hardware-designs hardware-acceleration fpga-accelerator hardware-description-language ip-core tpu

UpdatedJan 5, 2019
VHDL

SystemRDL /systemrdl-compiler

Star268

SystemRDL 2.0 language compiler front-end

asic fpga eda csr registers systemrdl register-descriptions systemrdl-compiler hardware-description-language design-automation register-description-language

UpdatedNov 26, 2025
C++

cucapra /filament

Star184

Fearless hardware design

fpga type-system hardware-description-language hardware-accelerator

UpdatedAug 20, 2025
Verilog

mit-plv /koika

Star166

A core language for rule-based hardware design 🦑

semantics coq programming-languages formal-methods compilation hardware-description-language

UpdatedDec 10, 2025
Rocq Prover

mit-plv /kami

Star163

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

coq proof-assistant bluespec hardware-description-language hardware-verification

UpdatedNov 20, 2025
Rocq Prover

SystemRDL /PeakRDL

Star159

Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

UpdatedDec 3, 2025
Python

asyncvlsi /act

Star122

ACT hardware description language and core tools.

language eda circuit-simulator cad dataflow chp dataflow-programming prs hdl vlsi hardware-description-language production-rules design-automation asynchronous-circuits vlsi-cad asynchronous-vlsi communicating-hardware-processes

UpdatedDec 16, 2025
C++

pc2 /sus-compiler

Star118

A new Hardware Design Language that keeps you in the driver's seat

programming-language tree-sitter fpga hdl hardware-description-language fpga-programming

UpdatedDec 17, 2025
Rust

cyber-anubis /The-HACK-General-Purpose-Computer

Star104

Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone compute…

cpu compiler virtual-machine assembler operating-system nand2tetris computer-architecture nand machine-language hardware-description-language arithmetic-logic-unit