Movatterモバイル変換

Skip to content

#

fpga

Here are 5,467 public repositories matching this topic...

Language:All

Filter by language

All5,467 Verilog1,464 VHDL1,191 C410 SystemVerilog377 Python345 C++288 Tcl177 HTML134 Jupyter Notebook97 Scala55

Sort:Most stars

Sort options

Most stars Fewest stars Most forks Fewest forks Recently updated Least recently updated

openwall /john

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

c fpga gpu opencl ripper assembler openmp mpi password hash simd gpgpu cracker john jtr crypt

UpdatedDec 12, 2025
C

PaddlePaddle /Paddle-Lite

PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）

arm mobile embedded fpga deep-learning neural-network mali baidu mdl mobile-deep-learning

UpdatedMay 22, 2025
C++

logisim-evolution

logisim-evolution /logisim-evolution

Digital logic design tool and simulator

education simulator fpga vhdl logic circuits verilog circuit digital-logic logisim digital-circuit digital-circuits timing-diagram digital-logic-design logisim-evolution

UpdatedDec 17, 2025
Java

LeiWang1999 /FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga verilog xilinx vivado pynq

UpdatedMay 15, 2022

openwifi

open-sdr /openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

linux fpga zynq hls hardware wifi verilog xilinx sdr analog-devices ieee80211 xilinx-fpga dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi

UpdatedDec 16, 2025
C

enjoy-digital /litex

Build your hardware, easily!

fpga hardware system-on-chip

UpdatedDec 16, 2025
C

SpinalHDL /VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore

UpdatedDec 15, 2025
Assembly

openhwgroup /cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

asic cpu fpga risc-v systemverilog-hdl rv64gc ariane

UpdatedDec 8, 2025
Assembly

darklife /darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

fpga core riscv verilog risc-v

UpdatedJul 16, 2025
Verilog

jbush001 /NyuziProcessor

GPGPU microprocessor architecture

processor-architecture fpga hardware gpu graphics verilog microprocessor gpu-computing

UpdatedNov 8, 2024
C

GlasgowEmbedded /glasgow

Scots Army Knife for electronics

fpga hardware debugging-tool glasgow-interface-explorer

UpdatedDec 15, 2025
Python

corundum /corundum

Open source FPGA-based NIC and platform for in-network compute

linux networking fpga nic in-network-compute

UpdatedJul 5, 2024
Verilog

neorv32

stnolting /neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller asic cpu fpga processor vhdl verilog soc risc-v soft-core

UpdatedDec 16, 2025
VHDL

SpinalHDL /SpinalHDL

Scala based HDL

scala fpga vhdl rtl verilog

UpdatedDec 17, 2025
Scala

pConst /basic_verilog

Must-have verilog systemverilog modules

spi-interface fpga hls encoder delay tcl verilog debounce xilinx synchronizer uart altera uart-verilog fifo pwm uart-protocol spi-master uart-controller uart-tx uart-receiver

UpdatedAug 2, 2025
Verilog

amaranth-lang /amaranth

A modern hardware definition language and toolchain based on Python

fpga hdl amaranth-hdl

UpdatedDec 3, 2025
Python

icestudio

FPGAwars /icestudio

❄️ Visual editor for open FPGA boards

javascript editor fpga ide blocks verilog icestorm lattice icestudio

UpdatedDec 6, 2025
JavaScript

analogdevicesinc /hdl

HDL libraries and projects

fpga verilog hdl hacktoberfest analog-devices jesd204b

UpdatedDec 17, 2025
Verilog

hls4ml

fastmachinelearning /hls4ml

Machine learning on FPGAs using HLS

python machine-learning fpga neural-network hls keras pytorch vivado vivado-hls onnx intel-hls

UpdatedDec 15, 2025
Python

serv

olofk /serv

SERV - The SErial RISC-V CPU

asic fpga verilog risc-v

UpdatedDec 16, 2025
Verilog

Improve this page

Add a description, image, and links to thefpga topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with thefpga topic, visit your repo's landing page and select "manage topics."

[8]ページ先頭

©2009-2025 Movatter.jp