fault-simulation

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litmuschaos /litmus

Star5k

Litmus helps SREs and developers practice chaos engineering in a Cloud-native way. Chaos experiments are published at the ChaosHub (https://hub.litmuschaos.io). Community notes is athttps://hackmd.io/a4Zu_sH4TZGeih-xCimi3Q

kubernetes golang devops reliability-engineering site-reliability-engineering cncf k8s cloud-native google-summer-of-code resilience-testing fault-injection hacktoberfest chaos-testing chaos-engineering fault-simulation operator-sdk chaoshub chaos-experiments litmuschaos lfx

UpdatedNov 28, 2025
Go

AUCOHL /Fault

Star169

A complete open-source design-for-testing (DFT) Solution

testing dft eda verilog verilog-hdl jtag atpg fault-simulation vlsi-cad scan-chains stuck-at

UpdatedAug 30, 2025
Swift

NTU-LaDS-II /FAN_ATPG

Star102

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

cli cpp eda lex verilog yacc vlsi fan-out atpg electronic-design-automation fault-simulation sequential-circuits stuck-at combinational-circuits test-pattern vlsi-testing

UpdatedJul 2, 2025
Verilog

amamory-verification /hw-formal-verif

Star16

Hardware Formal Verification

vhdl model-checking systemverilog formal-verification fault-simulation equivalence-checker jasper-gold

UpdatedAug 10, 2020
Verilog

kalexio /fault-simulator

Star7

Simple fault simulator

fault-injection atpg fault-simulation stuck-at

UpdatedJun 20, 2021
C

MakisChristou /ParallelCircuitSimulator

Star5

A serial and parallel logic fault simulator on gate level netlists.

simulator parallel-computing vlsi iscas fault-simulation

UpdatedMay 18, 2020
TeX

AndreasKaratzas /circuit-simulation

Star4

This is a Combinational Circuit Logic Simulation Tool. There is a C++ version and a C version.

c cpp circuit-simulation iscas combinational-logic fault-simulation combinational-circuit stuck-at

UpdatedMay 17, 2022
C++

Mrcuve0 /TFT-RI5CY-Assignment

Star3

Source files and documentation for the final assignment of the "Testing and Fault Tolerance" course.

testing riscv pulp atpg fault-simulation ri5cy

UpdatedFeb 12, 2020
Verilog

kanndil /PodemQuest

Star2

Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG).

testing dft eda gsoc design-for-testability atpg fault-simulation vlsi-design path-oriented stuck-at-faults podem gsoc-2024

UpdatedSep 30, 2024
Python

celine-hsieh /VLSI-Testing-LAB-1

Star1

Fault Simulation | Parallel Fault Simulation | Deductive fault Simulation | Test Coverage

dft test-coverage controllability observability atpg fault-simulation parallel-testing deductive-fault-simulation

UpdatedDec 15, 2022
Verilog

cad-polito-it /r4ves

Star1

RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.

questasim risc-v fault-simulation logic-simulation stuck-at-faults zoix