branch-predictor

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MIPT-ILab /mipt-mips

Star358

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

simulator cpu pipeline mips simulation mipt cpu-cache optimizations computer-architecture risc cpu-model risc-v branch-prediction computer-architecture-lesson branch-predictor clock-precise pre-silicon mips-binutils prediction-algorithms

UpdatedJun 11, 2022
C++

CMU-SAFARI /Pythia

Star157

A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

machine-learning reinforcement-learning computer-architecture prefetcher microarchitecture cache-replacement branch-predictor champsim-simulator champsim-tracer

UpdatedMar 25, 2025
C++

bcrafton /processor

Star24

A compiler, assembler, and processor.

performance compiler processor assembler os simd out-of-order superscalar branch-predictor memory-simulator

UpdatedFeb 1, 2018
OCaml

lingbai-kong /MIPS89-pipeline-CPU

Star16

同济大学CS《计算机系统实验》实验一TongJi University CS computer system experiment assignment 1

fpga mips big-endian branch-predictor tongji-university dynamic-pipelines

UpdatedMay 19, 2023
VHDL

yashpatel5400 /neuropath

Star15

A neural branch predictor tested using CPU emulator, testing both supervised learning and reinforcement learning (for COS 583: Great Moments in Computing at Princeton University)

UpdatedMay 17, 2017
HTML

hibagus /TwoLevelBPSimulator

Star8

Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4

simulator computer-engineering computer-architecture superscalar branch-prediction branch-predictor computer-engineering-lab

UpdatedMay 19, 2020
C++

Sanskar777 /Dynamic-branch-predictor-in-pipelined-processors

Star6

verilog-hdl branch-predictor pipelined-processors

UpdatedNov 18, 2019
Verilog

maxislash /branchPredictor

Star6

VHDL code of three branch predictors

vhdl computer-engineering computer-architecture branch-prediction branch-predictor

UpdatedJul 15, 2019
VHDL

SystemVerilog implementation of RISC-V RV32I_Zmmul & custom packed SIMD ISA as 5-stage single-issue CPU core with branch predictor and L1 caches, tied up in lockstep with ISA sim over DPI for verification

cpu cache simd riscv rtl risc-v branch-prediction rv32i branch-predictor dpi-c

UpdatedDec 18, 2025
SystemVerilog

AleksandarLilic /ama-riscv-sim

Star5

C++ Instruction Set Simulator for RISC-V RV32IMC & custom packed SIMD ISA with cache and branch predictor models, C/ASM workloads, and Python analysis tools

emulator cache simd riscv performance-visualization performance-analysis risc-v instruction-set-simulator cache-simulator baremetal branch-prediction coremark rv32i branch-predictor dhrystone rv32im rv32imc riscv-emulator dpi-c embench

UpdatedDec 18, 2025
C++

csbanon /branch-predictor

Star4

Branch Predictor is a C# program that runs a gshare branch prediction simulation, according to a specified number of Global Buffer Table (GBT) and Global History Record (GHR) bits. 2019.

branch-prediction branch-predictor gbt ghr global-branch-predictor global-buffer-table globar-history-record gshare gshare-table

UpdatedJun 4, 2020
C#

MIPT-ILab /PipelineFlowchartVis

Star2

MIPT-V Pipeline Flowchart Visualizer

simulator cpu pipeline mips simulation mipt cpu-cache optimizations computer-architecture cycle-accurate risc cpu-model prediction-algorithm risc-v branch-prediction computer-architecture-lesson branch-predictor clock-precise pre-silicon

UpdatedJun 25, 2022
CSS

NishadSaraf /Championship-Simulator

Star2

c computer-architecture branch-predictor ip-prefetcher

UpdatedMay 25, 2018
C++

nicolavianello95 /DLX

Star2

Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.

cpu mips vhdl microprocessor forwarding computer-architecture hazard-detection risc dlx multiplier branch-predictor digital-electronics btb bht

UpdatedDec 10, 2019
VHDL

jianfeiZhao /CSA

Star2

Labs in NYU Tandon 2019 Fall CSA course

branch-predictor pipeline-cpu

UpdatedMay 11, 2020
C++

yadav-sachin /spectre-attack-image

Star2

Spectre attack variant 1 is used here to extract an image data buffer from a program. The output image data is then decoded and median filters are applied to remove the hot pixels in the output image. Here I have included files for RGB and base64 format.

image-processing timing-attack security-vulnerability image-filters branch-predictor speculative-execution spectre-demo spectre-vulnerability