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pulp-platform /axi

Star1.5k

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

UpdatedFeb 20, 2026
SystemVerilog

taichi-ishitani /tvip-axi

Sponsor

Star447

AMBA AXI VIP

vip systemverilog uvm axi amba axi4 amba-axi

UpdatedJun 28, 2024
SystemVerilog

rggen /rggen

Star445

Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

UpdatedJan 7, 2026
Ruby

ZipCPU /sdspi

Star354

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface

UpdatedOct 18, 2025
Verilog

taichi-ishitani /tnoc

Sponsor

Star197

Network on Chip Implementation written in SytemVerilog

systemverilog uvm noc axi amba network-on-chip axi4 amba-axi

UpdatedAug 27, 2022
SystemVerilog

hdl-modules /hdl-modules

Star197

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

asic fpga hardware amd vhdl intel eda rtl ip xilinx vivado altera fifo cdc axi microsemi clock-domain-crossing asynchronous-fifo axi-lite efinix

UpdatedFeb 3, 2026
VHDL

SystemRDL /PeakRDL

Star175

Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

UpdatedDec 3, 2025
Python

lucky-wfw /ARM_AMBA_Design

Star139

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

arm verilog axi amba apb ahb

UpdatedMay 14, 2021
Verilog

hdl-registers /hdl-registers

Star83

An open-source HDL register code generator fast enough to run in real time.

python c html asic generator fpga cplusplus register vhdl eda rtl csr axi axi-lite register-interface

UpdatedFeb 2, 2026
Python

pulp-platform /axi_mem_if

Star49

Simple single-port AXI memory interface

asic fpga axi systemverilog-hdl

UpdatedJun 7, 2024
SystemVerilog

esynr3z /axi_vip_demo

Star43

Xilinx AXI VIP example of use

fpga xilinx systemverilog axi

UpdatedApr 24, 2021
SystemVerilog

d953i /Custom_Part_Data_Files

Star40

Xilinx PCIe to MIG DDR4 example designs and custom part data files

csv fpga ddr tcl calibration verilog xilinx vivado mig axi sqrl ddr4 vcu1525 bcu1525 dimm udimm rdimm sodimm

UpdatedFeb 4, 2024
Tcl

RSPwFPGAs /opae-xilinx

Star39

OPAE porting to Xilinx FPGA devices.

fpga xilinx pcie fpga-accelerator axi partial-reconfiguration opae platform-reuse

UpdatedAug 5, 2020
Coq

wyvernSemi /mem_model

Star27

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches

UpdatedFeb 2, 2026
VHDL

atfox272 /AXI4-Interconnect

Star25

RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.

axi interconnect axi4

UpdatedMar 13, 2025
Verilog

Wissance /QuickSPI

Star21

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

spi-interface fpga spi altera verilog-hdl xilinx-fpga xilinx-vivado verilog-components axi verilog-snippets spi-hdl spi-ip-core spi-pld spi-fpga verilog-spi axi-interfaces bit-oriented-spi soft-spi hard-spi dragster-spi

UpdatedNov 21, 2017
Verilog

pulp-platform /axi_node

Star19

AXI X-Bar

asic fpga systemverilog axi

UpdatedApr 8, 2020
SystemVerilog

hplp /aes_chisel

Star19

Implementation of the Advanced Encryption Standard in Chisel

aes chisel firrtl verilog avalon axi advanced-encryption-standard parameterized rocc

UpdatedApr 18, 2022
Scala

mwrnd /innova2_xcku15p_ddr4_bram_gpio

Star19

XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA

fpga vivado pcie axi ddr4 xdma innova2 xcku15p mnv303212a innova-2-flex mnv303212a-adlt 4xc7a16683 01pg974 pcie-xdma

UpdatedMar 7, 2024
Tcl

rggen /rggen-sv-rtl

Star16

Common SystemVerilog RTL modules for RgGen

rtl systemverilog axi apb axi4

UpdatedFeb 5, 2026
SystemVerilog

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axi

Here are 101 public repositories matching this topic...

pulp-platform /axi

taichi-ishitani /tvip-axi

rggen /rggen

ZipCPU /sdspi

taichi-ishitani /tnoc

hdl-modules /hdl-modules

SystemRDL /PeakRDL

lucky-wfw /ARM_AMBA_Design

hdl-registers /hdl-registers

pulp-platform /axi_mem_if

esynr3z /axi_vip_demo

d953i /Custom_Part_Data_Files

RSPwFPGAs /opae-xilinx

wyvernSemi /mem_model

atfox272 /AXI4-Interconnect

Wissance /QuickSPI

pulp-platform /axi_node

hplp /aes_chisel

mwrnd /innova2_xcku15p_ddr4_bram_gpio

rggen /rggen-sv-rtl

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