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Deep Learning Accelerator (Convolution Neural Networks)

This is an implementation of MIT Eyeriss-like deep learning accelerator in Verilog

Note: clacc stands forconvolutional layer accelerator

This is originally a course project of Deep Learning Hardware Accelerator Design at National Tsing Hua University, lectured by Prof.Youn-Long Lin. The course is an equivalent ofCS231n from stanford.

1. The Eyeriss project:http://eyeriss.mit.edu/
2. Y.-H. Chen, T. Krishna, J. Emer, V. Sze, "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks," IEEE Journal of Solid State Circuits (JSSC), ISSCC Special Issue, Vol. 52, No. 1, pp. 127-138, January 2017.
3. Y.-H. Chen, J. Emer, V. Sze, "Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks," International Symposium on Computer Architecture (ISCA), pp. 367-379, June 2016.
4. Y.-H. Chen, T. Krishna, J. Emer, V. Sze, "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks," IEEE International Conference on Solid-State Circuits (ISSCC), pp. 262-264, February 2016.
5. Suyog Gupta, Ankur Agrawal, Kailash Gopalakrishnan, and Pritish Narayanan. 2015. Deep learning with limited numerical precision. In Proceedings of the 32nd International Conference on International Conference on Machine Learning - Volume 37 (ICML'15), Francis Bach and David Blei (Eds.), Vol. 37. JMLR.org 1737-1746.

MIT License

Copyright (c) 2017 Michael (Tao-Yi) Lee

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